Search results for "delay overhead"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
2	Chi-Hong Hwang, Allen C.-H. Wu	A predictive system shutdown method for energy saving of event-driven computation.	ICCAD	1997	DBLP DOI BibTeX RDF	VLSI circuit design, delay overhead, event-driven computation, exponential-average approach, low delay penalties, pre-wakeup, prediction-miss correction, predictive system shutdown method, sleep mode operations, system-level power management, VLSI, finite state machine, logic CAD, energy saving, power saving, hit ratio, idle period
2	Harry Hollander, Bradley S. Carlson, Toby D. Bennett	Synthesis of SEU-tolerant ASICs using concurrent error correction.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	radiation hardening (electronics), SEU-tolerant ASIC synthesis, single error correction/double error detection Hamming code, delay overhead, memory element set partitioning, error correction codes, sequential circuits, sequential circuit, application specific integrated circuits, logic CAD, circuit layout CAD, single event upsets, logic partitioning, Hamming codes, fault tolerant design, area overhead, memory elements, design experiments, concurrent error correction
1	Weiguang Sheng, Liyi Xiao, Zhigang Mao	Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.	DAC	2009	DBLP DOI BibTeX RDF	genetic algorithm, optimization, soft error, multi-objective
1	Shucai Xiao, Jung-Min Park 0001, Yanzhu Ye	Tamper Resistance for Software Defined Radio Software.	COMPSAC	2009	DBLP DOI BibTeX RDF
1	Ji-Hye Bong, Yong-Jin Kwon, Kyeong-Sik Min, Sung-Mo Kang	New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs.	ISQED	2009	DBLP DOI BibTeX RDF
1	Kevin Brownell, Gu-Yeon Wei, David Brooks	Evaluation of voltage interpolation to address process variations.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy	An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.	JETC	2008	DBLP DOI BibTeX RDF	Low-temperature polycrystalline silicon (LTPS), grain boundary (GB), inherent variation, thin-film transistor (TFT), generic, reconfigurable, hybrid system, BIST, DFT, 3D integration
1	Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan	Fault tolerant bit parallel finite field multipliers using LDPC codes.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Maryam Ashouei, Adit D. Singh, Abhijit Chatterjee	Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan	Single Error Correcting Finite Field Multipliers Over GF(2m).	VLSI Design	2008	DBLP DOI BibTeX RDF	Galois Field Multiplier, VLSI, Cryptography, Error Correcting Codes
1	Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas	A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Sobeeh Almukhaizim, Yiorgos Makris	Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires.	IEEE Transactions on Reliability	2008	DBLP DOI BibTeX RDF
1	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy	Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Enhanced scan, Supply gating, Delay fault testing, Two-pattern testing
1	Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	layout, leakage power, insertion, standard-cell, sleep transistor
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Timing-driven row-based power gating.	ISLPED	2007	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
1	Vineet Agarwal, Jin Sun, Alexander V. Mitev, Janet Meiling Wang	Delay Uncertainty Reduction by Interconnect and Gate Splitting.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Chia-Hui Wang, Mei-Wen Li, Wanjiun Liao	A Distributed Key-Changing Mechanism for Secure Voice Over IP (VoIP) Service.	ICME	2007	DBLP DOI BibTeX RDF
1	Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri	A Structured ASIC Design Approach Using Pass Transistor Logic.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Martin Hansson, Atila Alvandpour	Comparative Analysis of Process Variation Impact on Flip-Flop Power-Performance.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Vishwanadh Tirumalashetty, Hamid Mahmoodi	Clock Gating and Negative Edge Triggering for Energy Recovery Clock.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Nima Honarmand, Ali Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi	High Level Synthesis of Degradable ASICs Using Virtual Binding.	VTS	2007	DBLP DOI BibTeX RDF
1	Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano	Concurrent Error Detection in Reed-Solomon Encoders and Decoders.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Joonhyoung Lee, Youngha Jung, Yoonsik Choe	Unequal Error Recovery Scheme for Multimedia Streaming in Application-Level Multicast.	International Conference on Computational Science	2007	DBLP DOI BibTeX RDF	multicast, multimedia streaming, error recovery, ALM
1	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt	PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures.	ASP-DAC	2006	DBLP DOI BibTeX RDF	granularity selection, linear placement, scheduling, data-parallelism, partial dynamic reconfiguration
1	Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy	Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi	A design approach for radiation-hard digital electronics.	DAC	2006	DBLP DOI BibTeX RDF	radiation-hard, SEU
1	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment.	DATE	2006	DBLP DOI BibTeX RDF
1	Nima Honarmand, Ali Afzali-Kusha	Low Power Combinational Multipliers using Data-driven Signal Gating.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Love Singhal, Elaheh Bozorgzadeh	Physically-aware exploitation of component reuse in a partially reconfigurable architecture.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Hossein Asadi, Mehdi Baradaran Tahoori	Soft error hardening for logic-level designs.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Kun-Lin Tsai, Ju-Yueh Lee, Shanq-Jang Ruan, Feipei Lai	Low power scheduling method using multiple supply voltages.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Behnam Amelifard, Massoud Pedram, Farzan Fallah	Low-leakage SRAM Design with Dual V_t Transistors.	ISQED	2006	DBLP DOI BibTeX RDF
1	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai	Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh	Power minimization for dynamic PLAs.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Ioannis Priggouris, Stathes Hadjiefthymiades	A distributable security management architecture for enterprise systems spanning multiple security domains.	Electronic Commerce Research	2006	DBLP DOI BibTeX RDF	Security, XML, Access control, LDAP, Enterprise systems, Distributable management
1	Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh	Power minimization for dynamic PLAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Srivathsan Krishnamohan, Nihar R. Mahapatra	Analysis and design of soft-error hardened latches.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	multiple-upset, single-event, soft errors, single-event upset, latch, radiation hardening
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy	A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.	DATE	2005	DBLP DOI BibTeX RDF
1	Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano	A Self Checking Reed Solomon Encoder: Design and Analysis.	DFT	2005	DBLP DOI BibTeX RDF
1	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra	Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits.	IOLTS	2005	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy	Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.	ISQED	2005	DBLP DOI BibTeX RDF
1	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance.	VTS	2005	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy	Low-power scan design using first-level supply gating.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Arjan Durresi, Vamsi Paruchuri, Mimoza Durresi, Leonard Barolli	A Hierarchical Anonymous Communication Protocol for Sensor Networks.	EUC	2005	DBLP DOI BibTeX RDF
1	Nikhil Jayakumar, Sunil P. Khatri	A metal and via maskset programmable VLSI design methodology using PLAs.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy	First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.	DFT	2004	DBLP DOI BibTeX RDF
1	Li Ding 0002, Pinaki Mazumder	On circuit techniques to improve noise immunity of CMOS dynamic logic.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu	A cost-effective scan architecture for scan testing with non-scan test power and test application cost.	DAC	2003	DBLP DOI BibTeX RDF
1	Benton H. Calhoun, Frank Honoré, Anantha Chandrakasan	Design methodology for fine-grained leakage control in MTCMOS.	ISLPED	2003	DBLP DOI BibTeX RDF	fine-grain sleep regions, sneak leakage, low power, design methodology, leakage, circuit design, sleep mode, MTCMOS
1	Nestoras Tzartzanis, William W. Walker	A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File.	ICCD	2003	DBLP DOI BibTeX RDF
1	Masayoshi Fujino, Vasily G. Moshnyaga	Dynamic operand transformation for low-power multiplier-accumulator design.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains.	ISQED	2003	DBLP DOI BibTeX RDF
1	Ashok K. Murugavel, N. Ranganathan	A Game-Theoretic Approach for Binding in Behavioral Synthesis.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Peter Wohl, Leendert M. Huisman	Analysis and Design of Optimal Combinational Compactors.	VTS	2003	DBLP DOI BibTeX RDF
1	Mahesh Mamidipaka, Daniel S. Hirschberg, Nikil D. Dutt	Adaptive low-power address encoding techniques using self-organizing lists.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Chris H. Kim, Kaushik Roy	Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors.	ISLPED	2002	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Testing Digital Circuits with Constraints. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
1	Henning Sanneck, Nguyen Tuong, Long Le, Adam Wolisz, Georg Carle	Intra-flow loss recovery and control for VoIP.	ACM Multimedia	2001	DBLP DOI BibTeX RDF	loss concealment, loss metrics, loss sensitivity, objective speech quality measurement, differentiated services, voice over IP, queue management
1	Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian	Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers.	VTS	2001	DBLP DOI BibTeX RDF
1	Junghwan Choi, Jinhwan Jeon, Kiyoung Choi	Power minimization of functional units partially guarded computation.	ISLPED	2000	DBLP DOI BibTeX RDF	partially guarded computation, low power
1	Chi-Hong Hwang, Allen C.-H. Wu	A predictive system shutdown method for energy saving of event-driven computation.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	event-drive, system shutdown, predictive, power management, sleep mode
1	Abderrahim Doumar, Hideo Ito	Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. (PDF / PS)	DFT	2000	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Edward J. McCluskey	Word Voter: A New Voter Design for Triple Modular Redundant Systems.	VTS	2000	DBLP DOI BibTeX RDF	Word-Voter, TMR-Simplex, data integrity, Triple Modular redundancy (TMR), Voter
1	G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos	Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, Paulo J. Teixeira, Marcelino B. Santos	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis.	DAC	1998	DBLP DOI BibTeX RDF
1	Ki-Seok Chung, C. L. Liu	Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction.	ISLPED	1998	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey	Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	Respecification, Synthesis for Testability, Don't Cares, High Level Testing
1	Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey	Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	controller resynthesis, test synthesis, high-level testing
1	Sandeep Bhatia, Niraj K. Jha	Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
1	Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen	Cost-free scan: a low-overhead scan path design methodology.	ICCAD	1995	DBLP DOI BibTeX RDF	Testing, DFT, Scan design
1	S. M. Aziz	A C-testable modified Booth's array multiplier.	VLSI Design	1995	DBLP DOI BibTeX RDF	C-testable multiplier, modified Booth algorithm, gate-level design, parallel processing, logic testing, integrated circuit testing, digital arithmetic, stuck-at faults, CMOS logic circuits, multiplying circuits, logic arrays, array multiplier, parallel multiplier
1	Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man	Design of a C-testable booth multiplier using a realistic fault model.	J. Electronic Testing	1994	DBLP DOI BibTeX RDF	test generation, design for testability, fault modelling, Array multipliers, C-testability
1	Ted E. Williams	Performance of iterative computation in self-timed rings.	VLSI Signal Processing	1994	DBLP DOI BibTeX RDF
1	Andres R. Takach, Niraj K. Jha	Easily testable gate-level and DCVS multipliers.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF