Search results for "design and test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Bruce C. Kim, Craig Force	Guest Editors' Introduction: The Evolution of RFIC Design and Test.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	RFIC chips, RF measurement, wireless, CMOS technology, design and test
3	Luigi Carro	Adding value to design and test through education: What are the challenges?	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	LATW, education, universities, industry, design and test
3	Nur Engin, Hans G. Kerkhoff, Ronald J. W. T. Tangelder, Han Speek	Integrated Design and Test of Mixed-Signal Circuits.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	design and test integration, test plan generation, specification-based testing, mixed-signal test
3	Irith Pomeranz, Sudhakar M. Reddy	On improving genetic optimization based test generation.	ED&TC	1997	DBLP DOI BibTeX RDF	propagation Citation: I. Pomeranz, S.M. Reddy, On improving genetic optimization based test generation, edtc, pp.506, 1997 European Design and Test Conference (ED&TC '97), 1997 Peer Review Notice, Give Us Feedback Usage of this product signifies your acceptance of the Terms of Use. var addtoMethod=1, var AddURL = escape(http://doi.ieeecomputersociety.org/), var AddTitle = escape(On improving genetic optimization based test generation), Open Download Liferay.Portlet.onLoad({ canEditTitle: false, columnPos: 1, isStatic: 'end', namespacedId: 'p_p_id_digitallibraryabstract_WAR_plugins_INSTANCE_DjbO_', portletId: 'digitallibraryabstract_WAR_plugins_INSTANCE_DjbO' }), genetic algorithms, test generation, fault coverage, activation, benchmark circuit, crossover operator, genetic optimization
2	Mohammad Tehranipoor, Farinaz Koushanfar	A Survey of Hardware Trojan Taxonomy and Detection.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	hardware Trojans, Trojan taxonomy and detection, security, design and test, ICs
2	Danilo Garbi Zutin, Michael E. Auer	Design and test of Application-Specific Integrated Circuits by use of mobile clients.	ICDIM	2008	DBLP DOI BibTeX RDF
2	Fabian Vargas	Design and test on chip for EMC.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	electromagnetic compatibility, EMC, portable electronics, electromagnetic environment
2	T. M. Mak, Sani R. Nassif	Guest Editors' Introduction: Process Variation and Stochastic Design and Test.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	silicon manufacturing processes, adaptive circuits, process variation, process monitoring, subthreshold leakage
2	Kwang-Ting (Tim) Cheng	The Need for a SiP Design and Test Infrastructure.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	SiP, system in package
2	Pui-In Mak, Seng-Pan U., Rui Paulo Martins	Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Kwang-Ting Cheng	New beginnings, continued success.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	transistor mismatch, jitter-tolerance testing, design for testability, heterogeneous systems, dependability analysis, design and test, nanometer technology, design debugging
2	Vladimir Hahanov	East-West Design & Test Workshop.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	Eastern Europe, Western Europe, electronic systems, design and test
2	Vladimir Hahanov	2005 IEEE East-West Design and Test Workshop.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	EWDTW 2005, formal verification, fault diagnosis, debug, BIST, EDA, system-level modeling
2	Byeongdo Kang, Young-Jik Kwon, Roger Y. Lee	A Design and Test Technique for Embedded Software.	SERA	2005	DBLP DOI BibTeX RDF	Software Test, Software Design, Embedded Software
2	Nelson Ou, Touraj Farahmand, Andy Kuo, Sassan Tabatabaei, André Ivanov	Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects.	IEEE Design & Test of Computers	2004	DBLP DOI BibTeX RDF
2	Kaidi Zhao, Bing Liu 0001, Thomas M. Tirpak, Andreas Schaller	V-Miner: using enhanced parallel coordinates to mine product design and test data.	KDD	2004	DBLP DOI BibTeX RDF	change patterns, parallel coordinate visualization, rules
2	Mike P. Li, Jan B. Wilstrup	Paradigm Shift For Jitter and Noise In Design and Test > GB/s Communication Systems.	ICCD	2003	DBLP DOI BibTeX RDF
2	Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira	Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	fault simulation, safety-critical, self-checking
2		Design and Test Education in Latin America.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
2	André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng	Integrated Design and Test Generation Under Internet Based Environment MOSCITO.	DSD	2002	DBLP DOI BibTeX RDF
2	Rong Lin	Bit-Matrix Decomposition and Dynamic Reconfiguration: A Unified Arithmetic Processor Architecture, Design and Test. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF
2	Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka	A SoC Test Strategy Based on a Non-Scan DFT Method.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	non-scan DFT, high level design and test, SoC test
2	Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira	Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro.	IOLTW	2001	DBLP DOI BibTeX RDF
2	V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff	Design and Test Space Exploration of Transport-Triggered Architectures.	DATE	2000	DBLP DOI BibTeX RDF
2	Chih-Ang Chen, Sandeep K. Gupta	Efficient BIST TPG design and test set compaction via input reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Sudhakar M. Reddy	Testing-what's missing? An incomplete list of challenges. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	testing area, quality guarantees, special-purpose procedures, integrated design and test, high-level failure models, program testing, computer testing, benchmark circuits, design cycle
2	Kuen-Jong Lee, Melvin A. Breuer	Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	1992	DBLP DOI BibTeX RDF
2	Karlheinz Hafner, Hartmut C. Ritter, Thomas M. Schwair, Stefan Wallstab, Michael Deppermann, Jürgen Gessner, Stefan Koesters, Wolf-Dietrich Moeller, Gerd Sandweg	Design and Test of an Integrated Cryptochip.	IEEE Design & Test of Computers	1991	DBLP DOI BibTeX RDF
1	M. Anthony Lewis, Matthew R. Bunting, Behnam Salemi, Heiko Hoffmann	Toward Ultra High Speed Locomotors: Design and test of a cheetah robot hind limb.	ICRA	2011	DBLP DOI BibTeX RDF
1	Cheng-Wen Wu	Special session: Hot topic design and test of 3D and emerging memories.	VTS	2011	DBLP DOI BibTeX RDF
1	Xiaoqing Yu, Pute Wu, Zenglin Zhang	Design and Test of Nodes for Field Information Acquisition Based on WUSN.	ICICA (LNCS)	2011	DBLP DOI BibTeX RDF
1	Sandip Kundu, Aswin Sreedhar	Modeling manufacturing process variation for design and test.	DATE	2011	DBLP BibTeX RDF
1	Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez	On using a SPICE-like TSTAC™ eFlash model for design and test.	DDECS	2011	DBLP DOI BibTeX RDF
1	C. Cortes Alcala, Siyu Lin, Ruisi He, Cesar Briso-Rodríguez	Design and Test of a High QoS Radio Network for CBTC Systems in Subway Tunnels.	VTC Spring	2011	DBLP DOI BibTeX RDF
1	Peter A. Beerel, Georgios D. Dimou, Andrew Lines	Proteus: An ASIC Flow for GHz Asynchronous Designs.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	slack matching, asynchronous place and route, high performance, design and test, communicating sequential processes, asynchronous design
1	Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Pascal Vivet, Jérôme Willemin, Nicolas Leblond, Christian Piguet	Bringing Robustness and Power Efficiency to Autonomous Energy-Harvesting Microsystems.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	power management, design and test, energy harvesting, microsystem, asynchronous controller
1	Al Davis	Asynchronous FUD.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	design and test, asynchronous design
1	Jo C. Ebergen, Daniel Finchelstein, Russell Kao, Jon K. Lexau, David Hopkins	An Evaluation of Asynchronous Stacks.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	static-energy consumption, dynamic-energy consumption, asynchronous circuits, stack, design and test, LIFO
1	Ran Ginosar	Metastability and Synchronizers: A Tutorial.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	FIFO synchronizer, mesochronous, multisynchronous, synchronizer, asynchronous, design and test, metastability
1	Mariagrazia Graziano, Marco Vacca, Davide Blua, Maurizio Zamboni	Asynchrony in Quantum-Dot Cellular Automata Nanocomputation: Elixir or Poison?	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	magnetic quantum-dot cellular automata, magnetic memory, VHDL modeling, asynchronous architecture, design and test, Null Convention Logic, latency-insensitive design
1	Andrew B. Kahng	Roadmapping Power.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	design and test, roadmapping
1	Stan Krolikoski	Explicit and Implicit Contributions to Standards Groups.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	explicit contributions, implicit contributions, standards, design and test
1	Steven M. Nowick, Montek Singh	High-Performance Asynchronous Pipelines: An Overview.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	elastic circuits, latch controllers, pipelines, asynchronous, dynamic logic, design and test, micropipelines
1	Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres	A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	cryptography attacks, DPA, asynchronous, SCA, GALS, design and test, DEMA
1	Nicolas Troquard	Learning and Practice of the Property Specification Language.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	design, verification, specification, temporal logic, standards, design and test, PSL
1	Kun Young Chung, Sandeep K. Gupta	Design and test of latch-based circuits to maximize performance, yield, and delay test quality.	ITC	2010	DBLP DOI BibTeX RDF
1	Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara	Enabling False Path Identification from RTL for Reducing Design and Test Futileness.	DELTA	2010	DBLP DOI BibTeX RDF	path mapping, false path, functional equivalence, high level testing
1	Magdy S. Abadir	Design for reality: knowledge discovery in design and test data.	SBCCI	2010	DBLP DOI BibTeX RDF
1	Heinz-Dietrich Wuttke, Raimund Ubar, Karsten Henke	Remote and Virtual Laboratories in Problem-Based Learning Scenarios.	ISM	2010	DBLP DOI BibTeX RDF	remote and virtual laboratories, problem based learning scenarios, digital systems design and test, applets
1	Gabor Karsai, Fabio Massacci, Leon J. Osterweil, Ina Schieferdecker	Evolving Embedded Systems.	IEEE Computer	2010	DBLP DOI BibTeX RDF	Embedded systems, Software evolution, Systems engineering, Design and test, Critical systems
1	Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Peter F. Sweeney	The Effect of Omitted-Variable Bias on the Evaluation of Compiler Optimizations.	IEEE Computer	2010	DBLP DOI BibTeX RDF	Omitted-variable bias, Cache memories, Design and test, Computer performance, Measurement errors
1	Dale Sartor, Mark Wilson	Money for Research, Not Energy Bills: Finding Energy and Cost Savings in High-Performance Computer Facility Designs.	Computing in Science and Engineering	2010	DBLP DOI BibTeX RDF	computational research and theory facility, CRTF, energy-efficient computing, scientific computing, Design and test, standards and best practices
1	Alex Baumgarten, Akhilesh Tyagi, Joseph Zambreno	Preventing IC Piracy Using Reconfigurable Logic Barriers.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	hardware metering, IC fabrication, IC piracy, IC security, reconfigurable-logic barriers, selection heuristics, design and test
1	Binjie Cheng, Daryoosh Dideban, Negin Moezi, Campbell Millar, Gareth Roy, Xingsheng Wang, Scott Roy, Asen Asenov	Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	statistical variability, statistical compact modeling, design and test, MOSFET, mismatch
1	Lingkan Gong, Jingfen Lu	Verification-Purpose Operating System for Microprocessor System-Level Functions.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	microprocessor verification, system-level function, Verification-Purpose Operating System, VPOS, FPGA, design and test
1	Yier Jin, Yiorgos Makris	Hardware Trojans in Wireless Cryptographic ICs.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	hardware Trojan, wireless cryptographic IC, statistical analysis, design and test
1	Xi-Wei Lin, Victor Moroz	Layout Proximity Effects and Modeling Alternatives for IC Designs.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	mobility, CMOS, layout, variability, extraction, proximity, design and test, stress, lithography, threshold voltage, compact model
1	Darsen D. Lu, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu	Compact Modeling of Variation in FinFET SRAM Cells.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	multigate MOSFETs, variability, design for manufacturing, SRAM, design and test, FinFET, compact modeling
1	Colin C. McAndrew, Xin Li, Ivica Stevanovic, Gennady Gildenblat	Extensions to Backward Propagation of Variance for Statistical Modeling.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	backward propagation of variance, PSP model, Spice modeling, statistical modeling, design and test
1	Kurt Rosenfeld, Ramesh Karri	Attacks and Defenses for JTAG.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	security, design and test, hardware security, embedded test, JTAG
1	Samar K. Saha	Modeling Process Variability in Scaled CMOS Technology.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	compact variability modeling, gate-oxide thickness variability, high-k dielectric, line-edge roughness, polysilicon granularity, random discrete dopants, scaled CMOS technology, statistical compact modeling, design and test, process variability, metal gate
1	Mohammad Tehranipoor, Kenneth M. Butler	Power Supply Noise: A Survey on Effects and Research.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	power supply noise (PSN), transition delay fault testing, timing analysis, design and test, path delay testing
1	Mohammad Tehranipoor, Farinaz Koushanfar	Guest Editors' Introduction: Confronting the Hardware Trustworthiness Problem.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	hardware Trojans, Trojan attack, design and test, security measures, secret key, IP protection
1		Compact variability modeling to the rescue.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	compact variability modeling, nanometer CMOS technology, CMOS technology, design and test
1		Design & Test in the new decade: Continuity and new directions.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	physical trustworthiness, Trojans, VPOS, verification, design and test
1	Meng-Day (Mandel) Yu, Srinivas Devadas	Secure and Robust Error Correction for Physical Unclonable Functions.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	index-based syndrome coding, syndrome coding, error-correcting code, ECC, error correction, design and test, physical unclonable function, key generation
1	Danilo Garbi Zutin, Michael E. Auer	Design and Test of Application-Specific Integrated Circuits by use of Mobile Clients.	iJOE	2009	DBLP DOI BibTeX RDF
1	Seoksoo Kim, Soongohn Kim, Geuk Lee	Structure design and test of enterprise security management system with advanced internal security.	Future Generation Comp. Syst.	2009	DBLP DOI BibTeX RDF
1	Blair E. Sawyer, J. Todd Reinking, Aaron Corder, Teng K. Ooi	Methodologies to Design and Test Scintillation-Hardened Communication Links (abstract).	HSC	2009	DBLP BibTeX RDF
1	Xiaofeng Yang, Lingyong Meng, Fengqi Yu, Liwu Yang, Qinyang Wu, Jiankun Su, Jiefei Lu, Guangbo Li	Design and Test of a RFID UHF Tag.	PACCS	2009	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Portal, Ch. Muller	Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections.	European Test Symposium	2009	DBLP DOI BibTeX RDF	ReRAM, Defect Injection, Electrical Simulation, Memory Testing
1	Holger Reckter, Christian Geiger, Jürgen Singer, Stephan Streuber	Tech-note: Iterative design and test of a multimodal experience.	3DUI	2009	DBLP DOI BibTeX RDF
1	Xiaoyao Liang, Benjamin C. Lee, Gu-Yeon Wei, David Brooks	Design and test strategies for microarchitectural post-fabrication tuning.	ICCD	2009	DBLP DOI BibTeX RDF
1	Rick Kuhn, Raghu Kacker, Yu Lei, Justin Hunter	Combinatorial Software Testing.	IEEE Computer	2009	DBLP DOI BibTeX RDF	Combinatorial software testing, Efficient test design methods, Design and test, Software technologies, Pairwise testing
1	Noëlle Lewis, Michel Billaud, Didier Geoffroy, Philippe Cazenave, Thomas Zimmer	A Distance Measurement Platform Dedicated to Electrical Engineering.	TLT	2009	DBLP DOI BibTeX RDF	e-Learning tools, analog design and test, integrated circuits, remote laboratories, electrical engineering
1	Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara	Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.	ASP-DAC	2009	DBLP DOI BibTeX RDF	TAM design, thermal-aware test, wrapper design, test scheduling, SOC test
1	Farhad Aghili, Alessio Salerno	Attitude determination and localization of mobile robots using two RTK GPSs and IMU.	IROS	2009	DBLP DOI BibTeX RDF
1	Bijit Hore, Jehan Wickramasuriya, Sharad Mehrotra, Nalini Venkatasubramanian, Daniel Massaguer	Privacy-Preserving Event Detection in Pervasive Spaces.	PerCom	2009	DBLP DOI BibTeX RDF
1	Yervant Zorian	Guest Editor's Introduction: Examples of Management Decision Criteria.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Eduardo Werneck, Maiga Chang	Where Academics Meet the Real World: Difficulties Encountered When Conducting a Project for Designing a Game-Based Learning in a Company.	Edutainment	2009	DBLP DOI BibTeX RDF	game-learning learning, joy, training, computer game, educational games
1	Anssi Jääskeläinen	User eXperience: Tools for Developers.	INTERACT	2009	DBLP DOI BibTeX RDF	query tool, database, User experience, software development, UX
1	Luca Ascari, Ulisse Bertocchi, Paolo Corradi, Cecilia Laschi, Paolo Dario	Bio-inspired grasp control in a robotic hand with massive sensorial input.	Biological Cybernetics	2009	DBLP DOI BibTeX RDF
1	X. George Xu, Yong Hum Na, Tiantian Zhang	Design and test of a PC-based portable three-dimensional ultrasound software system Ultra3D.	Comp. in Bio. and Med.	2008	DBLP DOI BibTeX RDF
1	Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, Paulo J. Teixeira	Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems.	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	Lukás Sekanina, Lukás Starecek, Zdenek Kotásek, Zbysek Gajda	Polymorphic Gates in Design and Test of Digital Circuits.	IJUC	2008	DBLP BibTeX RDF
1	Kwang-Ting (Tim) Cheng	Design and test for reliability and efficiency.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF
1	Christopher M. Twigg, Paul E. Hasler	Incorporating Large-Scale FPAAs Into Analog Design and Test Courses.	IEEE Trans. Education	2008	DBLP DOI BibTeX RDF
1	Ernst Aderholz, Heiko Ahrens, Michael Rohleder	Bridging the gap between Design and Test Engineering for Functional Pattern Development.	ITC	2008	DBLP DOI BibTeX RDF
1	Shaojie Zhao, Lixin Zhang 0001, Zhongjun Zhang	Design and Test of a New Truck-Mounted Microwave Radiometer for Remote Sensing Research.	IGARSS	2008	DBLP DOI BibTeX RDF
1	Najmeh Farajipour, S. Behdad Hosseini, Zainalabedin Navabi	Utilizing HDL simulation engines for accelerating design and test processes.	EWDTS	2008	DBLP DOI BibTeX RDF
1	G. Belloni, M. Feroli, Antonio Ficola, Stefano Pagnottelli, Paolo Valigi	A COTS-Based Mini Unmanned Aerial Vehicle (SR-H3) for Security, Environmental Monitoring and Surveillance Operations: Design and Test.	EUROS	2008	DBLP DOI BibTeX RDF
1	Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini	A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Christian Geiger, Robin Fritze, Anke Lehmann, Jörg Stöcklein	HYUI: a visual framework for prototyping hybrid user interfaces.	Tangible and Embedded Interaction	2008	DBLP DOI BibTeX RDF	3D authoring, hybrid user interfaces, prototyping
1	Fang Liu, Sule Ozev, Plamen K. Nikolov	Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Hierarchical variance analysis, parameter correlations, performance model, process variations, analog circuits
1	Alberto González Téllez, Miguel Mateo Pla	Multithreaded Translation of Ptolemy II Designs on Multicore Platforms.	CISIS	2008	DBLP DOI BibTeX RDF
1	Hans A. R. Manhaeve	The Quest for Test: Will Redundancy Cover All?	DDECS	2008	DBLP DOI BibTeX RDF
1	Jose Luis Lima, José Alexandre Gonçalves, Paulo Gomes Costa, Antonio Paulo Moreira	Humanoid robot simulation with a joint trajectory optimized controller.	ETFA	2008	DBLP DOI BibTeX RDF
1	Moufid Harb, Rami S. Abielmona, Emil M. Petriu, Kamal Naji	Neural control system of a mobile robot.	IJCNN	2008	DBLP DOI BibTeX RDF
1	Yu-Shiang Lin, Scott Hanson, Fabio Albano, Carlos Tokunaga, Razi-Ul Haque, Kensall Wise, Ann Marie Sastry, David Blaauw, Dennis Sylvester	Low-voltage circuit design for widespread sensing applications.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Uranmandakh Amgalan, Christian Hachmann, Sybille Hellebrand, Hans-Joachim Wunderlich	Signature Rollback - A Technique for Testing Robust Circuits.	VTS	2008	DBLP DOI BibTeX RDF	Rollback and Recovery, Test Quality and Reliability, Robust Design, Time Redundancy, Embedded Test