Search results for "design errors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Sanghee Kim	From Design Errors to Design Opportunities Using a Machine Learning Approach.	PAKM	2006	DBLP DOI BibTeX RDF	Human and Design Errors, supervised learning approach, natural language processing
2	Ilya Wagner, Valeria Bertacco, Todd M. Austin	Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler	Using unsatisfiable cores to debug multiple design errors.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	sat-based debugging, unsatisfiable core, fault localization
2	Smruti R. Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, Josep Torrellas	Patching Processor Design Errors with Programmable Hardware.	IEEE Micro	2007	DBLP DOI BibTeX RDF	hardware errors, microarchitecture for fault-tolerance, design defects in real processors, processor errata analysis
2	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Fixing Design Errors with Counterexamples and Resynthesis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	simulation-based verification, digital design errors, error-correction framework, resynthesis techniques, goal-directed search, entropy-guided search, counterexamples, digital designs, combinational equivalence-checking
2	Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton	Automating Logic Rectification by Approximate SPFDs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	SAT-based algorithm, approximate SPFD, digital VLSI cycle, incremental rewiring-based optimization operations, automated logic rectification tools, predefined logic transformations, memory/time explosion problem, design errors
2	AnnMarie Ericsson, Mikael Berndtsson	Detecting Design Errors in Composite Events for Event Triggered Real-Time Systems Using Timed Automata.	SCW	2006	DBLP DOI BibTeX RDF
2	Fabrizio Ferrandi, Franco Fummi, Graziano Pravadelli, Donatella Sciuto	Identification of design errors through functional testing.	IEEE Transactions on Reliability	2003	DBLP DOI BibTeX RDF
2	A. Castelnuovo, Alessandro Fin, Franco Fummi, F. Sforza	Emulation-Based Design Errors Identification. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
2	Andreas G. Veneris, Ibrahim N. Hajj	Correcting multiple design errors in digital VLSI circuits.	ISCAS	1999	DBLP DOI BibTeX RDF
2	David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown	High-level design verification of microprocessors via error modeling.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	design verification, error modeling, design errors
2	Pi-Yu Chung, Ibrahim N. Hajj	Diagnosis and correction of multiple logic design errors in digital circuits.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
2	Andreas G. Veneris, Ibrahim N. Hajj	A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
2	Antti Valmari, Konsta Karsisto, Manu Setälä	Visualisation of Reduced Abstracted Behaviour as a Design Tool.	PDP	1996	DBLP DOI BibTeX RDF	reduced abstracted behaviour visualisation, software design tool, user-friendly formal method, incorrect actions, simultaneous analysis, communication protocol development, distributed system, formal specification, distributed processing, concurrency control, feedback, transport protocols, deadlocks, data visualisation, program diagnostics, graphical representation, livelocks, graphical display, design errors
2	Irith Pomeranz, Sudhakar M. Reddy	On correction of multiple design errors.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik	Automated correction of design errors by edge redirection on High-Level Decision Diagrams.	ISQED	2012	DBLP DOI BibTeX RDF
1	Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González	Implementing End-to-End Register Data-Flow Continuous Self-Test.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	end-to-end protection, Online testing, degradation, design errors, control logic
1	Jon Crowcroft	Internet Failures: an Emergent Sea of Complex Systems and Critical Design Errors?	Comput. J.	2010	DBLP DOI BibTeX RDF
1	Alexander Reder, Alexander Egyed	Model/analyzer: a tool for detecting, visualizing and fixing design errors in UML.	ASE	2010	DBLP DOI BibTeX RDF
1	Kypros Constantinides, Todd M. Austin	Using introspective software-based testing for post-silicon debug and repair.	DAC	2010	DBLP DOI BibTeX RDF
1	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair		2009	DBLP DOI BibTeX RDF
1	Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González	End-to-end register data-flow continuous self-test.	ISCA	2009	DBLP DOI BibTeX RDF	end-to-end protection, online testing, degradation, design errors, control logic
1	Haïthem Mansouri, Frederic Kleinermann, Olga De Troyer	Detecting inconsistencies in the design of virtual environments over the web using domain specific rules.	Web3D	2009	DBLP DOI BibTeX RDF	domain specific rules, virtual reality, semantics, virtual environments, X3D
1	Yingpan Wu, Lixin Yu, Wei Zhuang, Jianyong Wang	A Coverage-Driven Constraint Random-Based Functional Verification Method of Pipeline Unit.	ACIS-ICIS	2009	DBLP DOI BibTeX RDF
1	Jesse C. Himmelstein, Etienne Ferre, Jean-Paul Laumond	'Teleportation'-Based Motion Planner for Design Error Analysis.	ICRA	2009	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty	Unified Challenges in Nano-CMOS High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou	Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Ho Fai Ko, Nicola Nicolici	Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska	Spare Cells With Constant Insertion for Engineering Change.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Mark R. Greenstreet	Verifying VLSI Circuits.	ATVA	2009	DBLP DOI BibTeX RDF
1	Saar Drimer, Steven J. Murdoch, Ross J. Anderson	Optimised to Fail: Card Readers for Online Banking.	Financial Cryptography	2009	DBLP DOI BibTeX RDF	banking security, chip and PIN, authentication, reverse engineering, liability
1	Jameleddine Hassine	Early Schedulability Analysis with Timed Use Case Maps.	SDL Forum	2009	DBLP DOI BibTeX RDF
1	Vanessa Stricker, Stefan Hanenberg, Dominik Stein	Designing Design Constraints in the UML Using Join Point Designation Diagrams.	TOOLS	2009	DBLP DOI BibTeX RDF
1	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Fixing Design Errors With Counterexamples and Resynthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Miodrag Potkonjak, Farinaz Koushanfar	(Bio)-behavioral CAD.	DAC	2008	DBLP DOI BibTeX RDF	fMRI, behavioral science
1	Nathaniel Nystrom, Vijay A. Saraswat, Jens Palsberg, Christian Grothoff	Constrained types for object-oriented languages.	OOPSLA	2008	DBLP DOI BibTeX RDF	constraints, dependent types, object-oriented programming languages
1	Hana Chockler, Joseph Y. Halpern, Orna Kupferman	What causes a system to satisfy a specification&quest;.	ACM Trans. Comput. Log.	2008	DBLP DOI BibTeX RDF	Model checking, causality, responsibility, coverage metrics
1	Nuno Laranjeiro, Salvador Canelas, Marco Vieira	wsrbench: An On-Line Tool for Robustness Benchmarking.	IEEE SCC	2008	DBLP DOI BibTeX RDF	robustness benchmarking, web services, fault injection
1	Jinfeng Huang, Jeroen Voeten, Serge Wolfs, Mark Coopmans	An Executable Interface Specification for Industrial Embedded System Design.	QSIC	2008	DBLP DOI BibTeX RDF
1	Banit Agrawal, Timothy Sherwood, Chulho Shin, Simon Yoon	Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Erik Jan Marinissen	Bugs, moths, grasshoppers, and whales.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF
1	Joern Ploennigs, Mario Neugebauer, Klaus Kabitzsch	Diagnosis and Consulting for Control Network Performance Engineering of CSMA-Based Networks.	IEEE Trans. Industrial Informatics	2008	DBLP DOI BibTeX RDF
1	Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir	Validating Power ArchitectureTM Technology-Based MPSoCs Through Executable Specifications.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Jorge Campos, Hussain Al-Asaad	A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Yunja Choi, Christian Bunse	Towards Component-Based Design and Verification of a µ-Controller.	CBSE	2008	DBLP DOI BibTeX RDF
1	Jin Song Dong, Jing Sun 0002, Jun Sun 0001, Kenji Taguchi, Xian Zhang	Specifying and Verifying Sensor Networks: An Experiment of Formal Methods.	ICFEM	2008	DBLP DOI BibTeX RDF
1	Nuno Laranjeiro, Marco Vieira, Henrique Madeira	Robustness Validation in Service-Oriented Architectures.	WADS	2008	DBLP DOI BibTeX RDF	Online Information Services, Reliability and robustness, Benchmarking, Testing and Debugging
1	Bran Selic	Challenges in generating qos-constrained software implementations.	GPCE	2007	DBLP DOI BibTeX RDF	model-driven development
1	Philip Chong, Christian Szegedy	A morphing approach to address placement stability.	ISPD	2007	DBLP DOI BibTeX RDF	incremental placement, stability, morphing
1	Tathagato Rai Dastidar, P. P. Chakrabarti	A verification system for transient response of analog circuits.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Ana CTL, model checking, query language, Analog circuits, equivalence checking, transient response
1	Jeff Yan, Ahmad Salah El Ahmad	Breaking Visual CAPTCHAs with Naive Pattern Recognition Algorithms.	ACSAC	2007	DBLP DOI BibTeX RDF
1	Wei Dong, Ji Wang, Zhichang Qi, Ni Rong	Compositional Verification of UML Dynamic Models.	APSEC	2007	DBLP DOI BibTeX RDF
1	Mohsen Rouached, Claude Godart	Requirements-driven Verification of WSBPEL Processes.	ICWS	2007	DBLP DOI BibTeX RDF
1	Andrew DeOrio, Adam Bauserman, Valeria Bertacco	Chico: An On-chip Hardware Checker for Pipeline Control Logic.	MTV	2007	DBLP DOI BibTeX RDF
1	Subir K. Roy	Top Level SOC Interconnectivity Verification Using Formal Techniques.	MTV	2007	DBLP DOI BibTeX RDF
1	Marco Vieira, Nuno Laranjeiro, Henrique Madeira	Benchmarking the Robustness of Web Services.	PRDC	2007	DBLP DOI BibTeX RDF
1	Ben Shneiderman	Human Responsibility for Autonomous Agents.	IEEE Intelligent Systems	2007	DBLP DOI BibTeX RDF	human-computer interaction, robots, autonomous systems
1	Ilya Wagner, Valeria Bertacco, Todd M. Austin	Microprocessor Verification via Feedback-Adjusted Markov Models.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Jie Luo, Krishna R. Pattipati, Liu Qiao, Shunsuke Chigusa	An Integrated Diagnostic Development Process for Automotive Engine Control Systems.	IEEE Transactions on Systems, Man, and Cybernetics, Part C	2007	DBLP DOI BibTeX RDF
1	Luca Minin, Roberto Montanari, Stefano Marzani, Francesco Tesauri, Luca Canovi	Method to Select the Most Suitable Software Tool for the Development of an Hmi Virtual Prototype.	HCI	2007	DBLP DOI BibTeX RDF	user interface, user centered design, virtual prototyping, HMI
1	Hanmei Cui, Jessica Chen	On Formal MOM Modeling.	ISPA	2007	DBLP DOI BibTeX RDF	model checking, distributed applications, nondeterminism, message-oriented middleware
1	Satish Narayanasamy, Bruce Carneal, Brad Calder	Patching Processor Design Errors.	ICCD	2006	DBLP BibTeX RDF
1	Lada Gorlenko, Paul Englefied	Usability error classification: qualitative data analysis for UX practitioners.	CHI Extended Abstracts	2006	DBLP DOI BibTeX RDF	business value of usability, qualitative data analysis, usability errors, evaluation methodology
1	Ilya Wagner, Valeria Bertacco, Todd M. Austin	Shielding against design flaws with field repairable control logic.	DAC	2006	DBLP DOI BibTeX RDF	hardware patching, processor verification
1	Ian G. Harris	A coverage metric for the validation of interacting processes.	DATE	2006	DBLP DOI BibTeX RDF
1	T. Chan	RaceCheck: A Race Logic Audit Program For SoC Designs.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Xiangyu Wang, Phillip S. Dunston	Usability Evaluation of a Mixed Reality Collaborative Tool for Design Review.	CGIV	2006	DBLP DOI BibTeX RDF
1	Tsung-Hsi Chiang, Lan-Rong Dung	System-level verification on high-level synthesis of dataflow graph.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Yanping Yang, QingPing Tan, Yong Xiao, Jinshan Yu, Feng Liu	Exploiting Hierarchical CP-Nets to Increase the Reliability of Web Services Workflow.	SAINT	2006	DBLP DOI BibTeX RDF
1	Douglas Herbert, Yung-Hsiang Lu, Saurabh Bagchi, Zhiyuan Li	Detection and Repair of Software Errors in Hierarchical Sensor Networks.	SUTC	2006	DBLP DOI BibTeX RDF
1	Qingwei Wu, Michael S. Hsiao	State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Jiachen Hou, Daizhong Su	Service and Components Oriented Environment for Conducting Product Design Specification.	CSCWD (Selected Papers)	2006	DBLP DOI BibTeX RDF
1	Marco Mesiti, Roberto Celle, Matteo Alberto Sorrenti, Giovanna Guerrini	X-Evolution: A System for XML Schema Evolution and Document Adaptation.	EDBT	2006	DBLP DOI BibTeX RDF
1	B. Meenakshi, Abhishek Bhatnagar, Sudeepa Roy	Tool for Translating Simulink Models into Input Language of a Model Checker.	ICFEM	2006	DBLP DOI BibTeX RDF
1	Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone	Design and design automation of rectification logic for engineering change.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Ilya Wagner, Valeria Bertacco, Todd M. Austin	StressTest: an automatic approach to test generation via activity monitors.	DAC	2005	DBLP DOI BibTeX RDF	directed-random simulation, architectural simulation, high-performance simulation
1	Eduardo Romero-Aguirre, Juan Carlos Murrieta-Lee	A Survey of the Graphic Alternate Method for Boolean Functions Simplification.	CONIELECOMP	2005	DBLP DOI BibTeX RDF	Subminiterms, logic adjacency, variable-entered, miniterms rings, prime implicant
1	William Bradley Glisson, Ray Welland	Web Development Evolution: The Assimilation of Web Engineering Security.	LA-WEB	2005	DBLP DOI BibTeX RDF
1	Dezhuang Zhang, Rance Cleaveland	Fast On-the-Fly Parametric Real-Time Model Checking.	RTSS	2005	DBLP DOI BibTeX RDF
1	Tarek Sadani, Pierre de Saqui-Sannes, Jean-Pierre Courtiat	From RT-LOTOS to Time Petri Nets New Foundations for a Verification Platform.	SEFM	2005	DBLP DOI BibTeX RDF
1	Tathagato Rai Dastidar, P. P. Chakrabarti	A Verification System for Transient Response of Analog Circuits Using Model Checking.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Donald C. Gause	Why Context Matters--And What Can We Do about It?	IEEE Software	2005	DBLP DOI BibTeX RDF	software design, visibility, ambiguity
1	Sharad Malik	A Case for Runtime Validation of Hardware.	Haifa Verification Conference	2005	DBLP DOI BibTeX RDF
1	Xiaoming Fu, Dieter Hogrefe	Modeling Soft State Protocols with SDL.	NETWORKING	2005	DBLP DOI BibTeX RDF
1	Gerard J. Holzmann, Theo C. Ruys	Effective Bug Hunting with Spin and Modex.	SPIN	2005	DBLP DOI BibTeX RDF
1	Frédéric Badeau, Arnaud Amelot	Using B as a High Level Programming Language in an Industrial Project: Roissy VAL.	ZB	2005	DBLP DOI BibTeX RDF
1	Anand L. D'Souza, Michael S. Hsiao	Error Diagnosis of Sequential Circuits Using Region-Based Model.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	non-enumerative, diagnosis, sequential, region-based
1	Andreas G. Veneris, Jiang Brandon Liu	Incremental Design Debugging in a Logic Synthesis Environment.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	simulation, VLSI, CAD, debugging, design error
1	Martin Mutz	Metriken und Regeln für eine zustandsbasierte SW-Entwicklung im Automobilbereich.	Inform., Forsch. Entwickl.	2005	DBLP DOI BibTeX RDF	Modelling guidelines, Rule checker, UML, Software metrics, Statecharts, Automotive
1	Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou	On compliance test of on-chip bus for SOC.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Yuan Lu, Mike Jorda	Verifying a gigabit ethernet switch using SMV.	DAC	2004	DBLP DOI BibTeX RDF	Verification
1	Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel	Automatic generation of breakpoint hardware for silicon debug.	DAC	2004	DBLP DOI BibTeX RDF	hardware-breakpoints, design-flow, silicon-debug, design-for-debug
1	Jean-Pierre Talpin, David Berner, Sandeep K. Shukla, Paul Le Guernic, Abdoulaye Gamatié, Rajesh Gupta	A Behavioral Type Inference System for Compositional System-on-Chip Design.	ACSD	2004	DBLP DOI BibTeX RDF
1	Hasan Arslan, Shantanu Dutt	A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits.	ICCD	2004	DBLP DOI BibTeX RDF
1	Yukio Okuda	Panel Synopsis - Diagnosis Meets Physical Failure Analysis: How Long Can We Succeed?	ITC	2004	DBLP DOI BibTeX RDF
1	Qingwei Wu, Michael S. Hsiao	State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation.	ITC	2004	DBLP DOI BibTeX RDF
1	Rafael H. Bordini, Michael Fisher, Willem Visser, Michael Wooldridge	Model Checking Rational Agents.	IEEE Intelligent Systems	2004	DBLP DOI BibTeX RDF
1	Katarzyna Radecka, Zeljko Zilic	Design Verification by Test Vectors and Arithmetic Transform Universal Test Set.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	arithmetic transform, Verification, spectral methods, error modeling, Universal Test Set, Reed-Muller transform, Walsh-Hadamard transform
1	Te-Chang Lee, Pao-Ann Hsiung	Mutation Coverage Estimation for Model Checking.	ATVA	2004	DBLP DOI BibTeX RDF
1	Ross Anderson	The Dancing Bear: A New Way of Composing Ciphers.	Security Protocols Workshop	2004	DBLP DOI BibTeX RDF