Search results for "deterministic test generation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs	Identification of unsettable flip-flops for partial scan and faster ATPG.	ICCAD	1996	DBLP DOI BibTeX RDF	ISCAS89 circuits, deterministic test generation, difficult-to-set hip-hops, hip-hops, state elements, state justification, transformed circuits, unsettable flip-flops identification, logic testing, ATPG, partial scan, sequential circuits test generation
1	Bo Yao, Irith Pomeranz, Sudhakar M. Reddy	Deterministic broadside test generation for transition path delay faults.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	broadside test, deterministic test generation, path delay fault, transition fault
1	Milos Gligoric, Tihomir Gvero, Vilas Jagannath, Sarfraz Khurshid, Viktor Kuncak, Darko Marinov	Test generation through programming in UDITA.	ICSE	2010	DBLP DOI BibTeX RDF	Pex, UDITA, test filtering, test predicates, test generation, automated testing, test programs, Java PathFinder
1	Irith Pomeranz, Sudhakar M. Reddy	Forming N-detection test sets without test generation.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	test generation, stuck-at faults, Bridging faults, n-detection test sets
1	Stelios Neophytou, Maria K. Michael, Spyros Tragoudas	Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	irredundant faults, built-in test generation, test generation, synchronous sequential circuits, Initial states
1	Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy	MIX: A Test Generation System for Synchronous Sequential Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	deterministic test generation genetic optimization based test generation restricted multiple observation time approach state based test generation synchronous sequential circuits
1	Huy Nguyen, Abhijit Chatterjee, Rabindra K. Roy	Impact of Partial Reset on Fault Independent Testing and BIST.	VLSI Design	1997	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	LOCSTEP: a logic-simulation-based test generation procedure.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
1	Udo Mahlstedt	DELTEST: Deterministic Test Generation for Gate-Delay Faults.	ITC	1993	DBLP DOI BibTeX RDF
1	Kwang-Ting Cheng	Transition fault testing for sequential circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Hi-Keung Tony Ma, Srinivas Devadas, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli	Test generation for sequential circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1988	DBLP DOI BibTeX RDF
1	Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli	PLATYPUS: a PLA test pattern generation tool.	DAC	1985	DBLP DOI BibTeX RDF