Search results for "device optimization"

Found 12 publication records. Showing 12 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Javid Jaffari, Mohab Anis	Variability-aware device optimization under ION and leakage current constraints.	ISLPED	2006	DBLP DOI BibTeX RDF	device design, optimization, performance, process variation, leakage current
2	Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy	Device optimization for ultra-low power digital sub-threshold operation.	ISLPED	2004	DBLP DOI BibTeX RDF	device optimization, sub-threshold operation, ultra-low power applications
1	S. D. Pable, Mohd. Hasan	High speed interconnect through device optimization for subthreshold FPGA.	Microelectronics Journal	2011	DBLP DOI BibTeX RDF
1	Artem Artamonov, Vladislav Nelayev, Ibrahim Shelibak, Arkady Turtsevich	IGBT technology design and device optimization.	EWDTS	2011	DBLP DOI BibTeX RDF
1	Wei Zhang 0032, Ki Chul Chun, Chris H. Kim	Variation aware performance analysis of gain cell embedded DRAMs.	ISLPED	2010	DBLP DOI BibTeX RDF	bitline delay, gain cell, process variation, monte carlo simulation, embedded DRAM
1	David Corbel, Olivier Company, François Pierrot	Optimal design of a 6-dof parallel measurement mechanism integrated in a 3-dof parallel machine-tool.	IROS	2008	DBLP DOI BibTeX RDF
1	Javid Jaffari, Mohab Anis	Variability-Aware Bulk-MOS Device Design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Ravishankar Rao, Sarma B. K. Vrudhula	Energy optimal speed control of a producer--consumer device pair.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	joint optimization, processor, Energy optimization, disk drive, speed control
1	Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He	Device and Architecture Cooptimization for FPGA Power Reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He	Device and architecture co-optimization for FPGA power reduction.	DAC	2005	DBLP DOI BibTeX RDF	Psim, Ptrace, powergating, FPGA, low power
1	Natarajan Mahadeva Iyer, M. K. Radhakrishnan	ESD Reliability Challenges for RF/Mixed Signal Design & Processing.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Mikako Miyama, Shiro Kamohara	Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters.	ASP-DAC	2000	DBLP DOI BibTeX RDF

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