Search results for "diagnostic test generation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi	Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	diagnostic test generation, VLSI, test generation, fault
2	Irith Pomeranz, Sudhakar M. Reddy	Output-Dependent Diagnostic Test Generation.	VLSI Design	2010	DBLP DOI BibTeX RDF	diagnostic test generation, stuck-at faults, full-scan circuits
2	Irith Pomeranz, Sudhakar M. Reddy	Diagnostic Test Generation Based on Subsets of Faults.	European Test Symposium	2007	DBLP DOI BibTeX RDF
2	Xiaoming Yu, Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz	Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation.	VTS	2003	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Maheshwar Chandrasekar, Nikhil P. Rahagude, Michael S. Hsiao	Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test Generation.	J. Electronic Testing	2010	DBLP BibTeX RDF
1	Yu Zhang, Vishwani D. Agrawal	A diagnostic test generation system.	ITC	2010	DBLP DOI BibTeX RDF
1	Shujun Deng, Kwang-Ting Cheng, Jinian Bian, Zhiqiu Kong	Mutation-based diagnostic test generation for hardware design error diagnosis.	ITC	2010	DBLP DOI BibTeX RDF
1	Yu Zhang, Vishwani D. Agrawal	A diagnostic test generation system and a coverage metric.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Diagnostic fault simulation, diagnostic test generation, fault diagnosis, fault collapsing, fault equivalence, fault dominance
1	Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu	Diagnostic test generation for transition faults using a stuck-at ATPG tool.	ITC	2009	DBLP DOI BibTeX RDF
1	Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy, Yu Huang 0005	On Improving Diagnostic Test Generation for Scan Chain Failures.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Maheshwar Chandrasekar, Michael S. Hsiao	Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility.	HLDVT	2009	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits.	Electr. Notes Theor. Comput. Sci.	2007	DBLP DOI BibTeX RDF
1	Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume	Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines.	DFT	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman	z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Naresh K. Bhatti, Ronald D. Blanton	Diagnostic Test Generation for Arbitrary Faults.	ITC	2006	DBLP DOI BibTeX RDF
1	Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng	Accurate Diagnosis of Multiple Faults.	ICCD	2005	DBLP DOI BibTeX RDF
1	Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri	Fault equivalence and diagnostic test generation using ATPG.	ISCAS	2004	DBLP BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	On diagnosis and diagnostic test generation for pattern-dependenttransition faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Xiaoming Yu, Jue Wu, Elizabeth M. Rudnick	Diagnostic test generation for sequential circuits.	ITC	2000	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	A diagnostic test generation procedure for synchronous sequential circuits based on test elimination.	ITC	1998	DBLP DOI BibTeX RDF
1	Irith Pomeranz, W. Kent Fuchs	A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Yiming Gong, Sreejit Chakravarty	Using fault sampling to compute I/sub DDQ/ diagnostic test set.	VTS	1997	DBLP DOI BibTeX RDF	fault sampling, IDDQ diagnostic test set generation, combinational circuits, combinational circuit, bridging faults
1	Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs	Diagnostic Test Pattern Generation for Sequential Circuits.	VTS	1997	DBLP DOI BibTeX RDF
1	Yiming Gong, Sreejit Chakravarty	On adaptive diagnostic test generation.	ICCAD	1995	DBLP DOI BibTeX RDF