Search results for "digital circuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Jacques Losq	Efficiency of Random Compact Testing.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	sequential digital circuits, Combinational digital circuits, compact testing of digital circuits, random testing of digital circuits
3	Erika Matsak	Representing Logical Inference Steps with Digital Circuits.	HCI	2009	DBLP DOI BibTeX RDF	Logical inference steps, digital circuits representing logical inference steps, logic gates
3	Zbysek Gajda, Lukás Sekanina	Reducing the number of transistors in digital circuits using gate-level evolutionary design.	GECCO	2007	DBLP DOI BibTeX RDF	digital circuits, evolvable hardware, evolutionary design
3	Florent de Dinechin	Libraries of schedule-free operators in Alpha.	ASAP	1997	DBLP DOI BibTeX RDF	schedule-free operators, digital circuits synthesis, bit-level, binary implementation, bit-level dependency analysis, bit-parallel array, parallelism, digital circuits, arithmetic operators, affine recurrence equations, matrix-vector product
3	Masami Nakajima, Michitaka Kameyama	Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	highly parallel circuits, linear digital circuits, multiplicated redundant symbol, k-ary operations, multiple-valued logic
3	Trevor J. Smedley	A High-Level Visual Language for the Graphical Description of Digital Circuits. (PDF / PS)	VL	1995	DBLP DOI BibTeX RDF	pulse circuits, high-level visual language, graphical description, programming language systems, digital design systems, full-featured visual programming language, complex circuit specification, repetitive structures, conditional structures, visual languages, circuit analysis computing, circuit CAD, digital circuits, engineering graphics, program structures, digital circuit design
3	Anirudh Devgan, Ronald A. Rohrer	Efficient simulation of interconnect and mixed analog-digital circuits in ACES.	VLSI Design	1995	DBLP DOI BibTeX RDF	adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation
3	Stefan Radtke, Jens Bargfrede, Walter Anheier	Distributed automatic test pattern generation with a parallel FAN algorithm. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	distributed automatic test pattern generation, parallel FAN algorithm, backtracking mechanism, heterogeneous cluster of workstations, test vector compaction, genetic algorithms, genetic algorithm, parallel algorithms, computational complexity, logic testing, digital circuits, digital circuits, NP hard problem, sequential algorithms
3	Debashis Bhattacharya, John P. Hayes	A hierarchical test generation methodology for digital circuits.	J. Electronic Testing	1990	DBLP DOI BibTeX RDF	high-level circuit models, test generation, fault modeling, digital circuits, hierarchical testing
2	Stelios Neophytou, Kyriakos Christou, Maria K. Michael	An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment Enumeration.	European Test Symposium	2011	DBLP DOI BibTeX RDF	zero-supressed binary decision diagrams, digital circuits, path similarity
2	Hamed F. Dadgour, Muhammad M. Hussain, Kaustav Banerjee	A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs.	ISLPED	2010	DBLP DOI BibTeX RDF	Boolean logic minimization, energy-efficient electronics, laterally-actuated NEMS, nanoelectromechanical switches, XOR gates
2	Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala	Design of self correcting radiation hardened digital circuits using decoupled ground bus.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	self-repairing circuits, soft errors, radiation hardening
2	Satish Sivaswamy, Kia Bazargan, Marc D. Riedel	Estimation and optimization of reliability of noisy digital circuits.	ISQED	2009	DBLP DOI BibTeX RDF
2	Javid Jaffari, Mohab Anis	Timing yield estimation of digital circuits using a control variate technique.	ISQED	2009	DBLP DOI BibTeX RDF
2	Ashish Goel, Morteza Ibrahimi	Renewable, Time-Responsive DNA Logic Gates for Scalable Digital Circuits.	DNA	2009	DBLP DOI BibTeX RDF
2	Gustavo Neuberger, Gilson I. Wirth, Ricardo Reis	Protecting digital circuits against hold time violation due to process variability.	SBCCI	2009	DBLP DOI BibTeX RDF	flip-flop characterization, hold time violations, race immunity, clock skew, process variability
2	Jorge Semião, Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Leonardo Bisch Piccoli, Fabian Vargas, Marcelino Bicho Dos Santos, Isabel Maria Cacho Teixeira, João Paulo Teixeira	Signal Integrity Enhancement in Digital Circuits.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF
2	Mihai Oltean, Laura Diosan	An Adaptive GP Strategy for Evolving Digital Circuits.	KES	2008	DBLP DOI BibTeX RDF
2	Adam Slowik, Michal Bialko	Design and Multi-Objective Optimization of Combinational Digital Circuits Using Evolutionary Algorithm with Multi-Layer Chromosomes.	ICAISC	2008	DBLP DOI BibTeX RDF
2	Ludek Zaloudek, Lukás Sekanina	Transistor-Level Evolution of Digital Circuits Using a Special Circuit Simulator.	ICES	2008	DBLP DOI BibTeX RDF
2	Jamie Cullen	Evolving Digital Circuits in an Industry Standard Hardware Description Language.	SEAL	2008	DBLP DOI BibTeX RDF
2	Javid Jaffari, Mohab Anis	On efficient Monte Carlo-based statistical static timing analysis of digital circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Martin Simlastík, Viera Stopjaková	Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey.	PATMOS	2008	DBLP DOI BibTeX RDF	Asynchronous Digital Circuits, Self-time Digital Circuits, Synchronous-to-asynchronous Conversion, DLAP, De-synchronization, Phased Logic, LEDR, Low Power, Null Convention Logic, SADT
2	Fatima Zohra Hadjam, Claudio Moraga, Mohamed Benmohamed	Cluster-based evolutionary design of digital circuits using all improved multi-expression programming.	GECCO (Companion)	2007	DBLP DOI BibTeX RDF	improved multi-expression programming, genetic programming, combinational circuits, islands model, computational effort
2	Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar	NBTI-Aware Synthesis of Digital Circuits.	DAC	2007	DBLP DOI BibTeX RDF
2	Edson Pedro Ferlin, Heitor S. Lopes, Carlos R. Erig Lima, Ederson Cichaczewski	Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits.	ARC	2007	DBLP DOI BibTeX RDF
2	A. K. Mrunal, M. A. Shirasgaonkar, R. Patrikar	Stacked Active Loads For Low Power, High Speed GaAs Digital Circuits (SALFL).	APCCAS	2006	DBLP DOI BibTeX RDF
2	Hayssam El-Razouk, Zine Abid	A New Transistor-Redundant Voter for Defect-Tolerant Digital Circuits.	CCECE	2006	DBLP DOI BibTeX RDF
2	Qing Wu, Jingyi Zhang, Qinru Qiu	Design considerations for digital circuits using organic thin film transistors on a flexible substrate.	ISCAS	2006	DBLP DOI BibTeX RDF
2	József Sziray	Test Calculation for Logic and Delay Faults in Digital Circuits.	MTV	2006	DBLP DOI BibTeX RDF	Test-pattern calculation, logic faults, CMOS transistor structures, functional testing, delay faults, multi-valued logic
2	James Alfred Walker, Julian Francis Miller, Rachel Cavill	A multi-chromosome approach to standard and embedded cartesian genetic programming.	GECCO	2006	DBLP DOI BibTeX RDF	automatically defined functions, embedded cartesian genetic programming, multi-chromosome, multi-chromosome evolutionary strategy, evolution, digital circuits, cartesian genetic programming, module acquisition
2	Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen P. Boyd	A New Method for Design of Robust Digital Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
2	Radu Zlatanovici, Borivoje Nikolic	Power - Performance Optimization for Custom Digital Circuits.	PATMOS	2005	DBLP DOI BibTeX RDF
2	Josep Rius, José Pineda de Gyvez, Maurice Meijer	An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits.	PATMOS	2005	DBLP DOI BibTeX RDF
2	Santosh Biswas, P. Srikanth, R. Jha, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar	On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
2	Nadia Nedjah, Luiza de Macedo Mourelle	Pareto-Optimal Hardware for Digital Circuits Using SPEA.	IEA/AIE	2005	DBLP DOI BibTeX RDF
2	Osama Neiroukh, Xiaoyu Song	Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques.	DATE	2005	DBLP DOI BibTeX RDF
2	Wieland Fischer, Berndt M. Gammel	Masking at Gate Level in the Presence of Glitches.	CHES	2005	DBLP DOI BibTeX RDF	random masking, masked logic circuits, Cryptanalysis, side-channel attacks, DPA, power analysis, logic circuits, digital circuits, masking, glitches
2	Soumitra Bose	Modeling Custom Digital Circuits for Test.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	ATPG, fault simulation, logic simulation, switch-level modeling
2	Leonardo Valencia	Low Level Adaptive Frequency in Synthesis of High Speed Digital Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
2	Eunseok Song, Young-Kil Park, Soon Kwon, Soo-Ik Chae	A Cycle-Accurate Energy Estimator for CMOS Digital Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
2	Mihai Oltean, Crina Grosan, Mihaela Oltean	Designing Digital Circuits for the Knapsack Problem.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
2	Ivan Blunno, Guy Alain Narboni, Claudio Passerone	An Automated Methodology for Low Electro-Magnetic Emissions Digital Circuits Design.	DSD	2004	DBLP DOI BibTeX RDF
2	Shuji Tsukiyama	Toward stochastic design for digital circuits: statistical static timing analysis.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Adam Slowik, Michal Bialko	Design and Optimization of Combinational Digital Circuits Using Modified Evolutionary Algorithm.	ICAISC	2004	DBLP DOI BibTeX RDF
2	Ganesh K. Venayagamoorthy, Venu G. Gudise	Swarm Intelligence for Digital Circuits Implementation on Field Programmable Gate Arrays Platforms.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
2	Mihai Oltean, Crina Grosan	Evolving Digital Circuits using Multi Expression Programming.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
2	J. Soares Augusto, Carlos Beltrán Almeida, H. C. Campos Neto	A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits.	FPL	2003	DBLP DOI BibTeX RDF
2	Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida	Design Tools and Reusable Libraries for FPGA-Based Digital Circuits.	DSD	2003	DBLP DOI BibTeX RDF
2	Régis Leveugle, K. Hadjiat	Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	VHDL, fault injection, VLSI design, dependability analysis, digital circuits
2	Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu	Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh	Predicting potential performance for digital circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	C. Baena, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos J. Jiménez, Manuel Valencia	Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.	PATMOS	2002	DBLP DOI BibTeX RDF
2	Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen	Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.	DAC	2002	DBLP DOI BibTeX RDF	di/dt noise, low-noise digital design, supply current shaping, optimization, substrate noise, clock distribution networks
2	Soumitra Bose	Automated Modeling of Custom Digital Circuits for Test.	DATE	2002	DBLP DOI BibTeX RDF
2	Fernando Mendoza-Hernandez, M. Linares, Víctor H. Champac, A. Diaz-Sanchez	A new technique for noise-tolerant pipelined dynamic digital circuits.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner	Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Testing Digital Circuits with Constraints. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
2	Peter Verplaetse, Dirk Stroobandt, Jan M. Van Campenhout	A stochastic model for the interconnection topology of digital circuits.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
2	Hendrawan Soeleman, Kaushik Roy, Tan-Li Chou	Estimating Circuit Activity in Combinational CMOS Digital Circuits.	IEEE Design & Test of Computers	2000	DBLP DOI BibTeX RDF
2	Shiyi Xu, Wei Cen	Forecasting the efficiency of test generation algorithms for digital circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
2	Ruchir Puri, Ching-Te Chuang	SOI Digital Circuits: Design Issues.	VLSI Design	2000	DBLP DOI BibTeX RDF	Design, Digital Circuits, SOI
2	Vesselin K. Vassilev, Dominic Job, Julian F. Miller	Towards the Automatic Design of More Efficient Digital Circuits.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
2	Francisco Azevedo, Pedro Barahona	Modelling Digital Circuits Problems with Set Constraints.	Computational Logic	2000	DBLP DOI BibTeX RDF
2	Catherine Dezan, Loïc Lagadec, Bernard Pottier	Object Oriented Approach for Modeling Digital Circuits.	MSE	1999	DBLP DOI BibTeX RDF
2	T. P. E. Broekaert, B. Brar, F. Morris, A. C. Seabaugh, G. Frazier	Resonant Tunneling Technology for Mixed Signal and Digital Circuits in the 10-100 GHz Domain.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
2	Debashis Nayak, D. M. H. Walker	Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits.	VTS	1999	DBLP DOI BibTeX RDF
2	Karim Arabi, Hassan Ihs, Christian Dufaza, Bozena Kaminska	Digital oscillation-test method for delay and stuck-at fault testing of digital circuits.	ITC	1998	DBLP DOI BibTeX RDF
2	Vishwani D. Agrawal, Sharad C. Seth	Mutually Disjoint Signals and Probability Calculation in Digital Circuits.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Testing, Digital circuits, Signal probabilities, Syndrome
2	Dariusz Bojanowicz	How Faults can be Simulated in Self-Testable VLSI Digital Circuits.	EUROMICRO	1998	DBLP DOI BibTeX RDF
2	Ram K. Krishnamurthy, L. Richard Carley	Exploring the design space of mixed swing quadrail for low-power digital circuits.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
2	M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf	The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
2	Kris Gaj, Eby G. Friedman, Marc J. Feldman	Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits.	VLSI Signal Processing	1997	DBLP DOI BibTeX RDF
2	K. Nanda, S. K. Desai, S. K. Roy	A New Methodology for the Design of Asynchronous Digital Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF
2	Premal Buch, Ernest S. Kuh	SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF
2	Gerhard Fettweis	Design methodology for digital signal processing.	ASAP	1997	DBLP DOI BibTeX RDF	semiconductor integration density, architecture heterogeneity, hardwired digital circuits, software programmed signal processors, flexibly mapping, system simulation tools, system design, signal processing, digital signal processing, design methodology, data transfer, data manipulation
2	Julien Dunoyer, Nizar Abdallah, Pirouz Bazargan-Sabet	A symbolic simulation approach in resolving signals' correlation.	Annual Simulation Symposium	1996	DBLP DOI BibTeX RDF	signal resolution, signal correlation resolution, symbolic simulation approach, evaluation package, signal transition density, specification levels, first order clue, independent inputs, binary decision diagram concept, algorithms, VLSI, probability, logic CAD, digital simulation, design process, decision theory, circuit analysis computing, integrated circuit design, circuit CAD, digital circuits, subroutines, symbol manipulation, power dissipation, correlation methods, digital integrated circuits, signal probability, probabilistic approach, synthesis tools
2	Karl M. Fant, Scott A. Brandt	NULL Convention Logic/sup TM/: A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis.	ASAP	1996	DBLP DOI BibTeX RDF	consistent logic, asynchronous digital circuit synthesis, symbolically complete logic, asynchronous digital circuits, asynchronous circuits, multivalued logic, three value logic, Boolean logic, NULL Convention Logic, four value logic
2	Hans-Georg Martin	Retiming for Circuits with Enable Registers.	EUROMICRO	1996	DBLP DOI BibTeX RDF	enable registers, circuit retiming, combinational paths, D-Flipflops, retiming algorithm, sequential elements, high level synthesis, high level synthesis, digital circuits
2	Come Rozon	On the Use of VHDL as a Multi-Valued Logic Simulator. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	multi-valued logic simulator, ternary circuits, simulation, VHDL, logic CAD, functionality, circuit analysis computing, hardware description languages, digital circuits, multivalued logic circuits, timing specifications
2	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.	VTS	1996	DBLP DOI BibTeX RDF	GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm
2	Janusz Rzeszut, Bozena Kaminska, Yvon Savaria	A new method for testing mixed analog and digital circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	charge-coupled device circuits, mixed analog and digital circuits, analog test points, simultaneous observation, analog multiplexer, signal path, analog shift register, input voltage, integrated circuit testing, shift registers, mixed analogue-digital integrated circuits, charge coupled device, analogue processing circuits
2	Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia	Fast discrete function evaluation using decision diagrams.	ICCAD	1995	DBLP DOI BibTeX RDF	address lookups, cycle-based logic simulation, decision-diagram based function evaluation, fast discrete function evaluation, latch ports, orders-of-magnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multi-valued decision diagrams
2	C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal	A STAFAN-like functional testability measure for register-level circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
2	Luben Boianov, Innes Jelly	Distributed logic circuit simulation on a network of workstations.	PDP	1995	DBLP DOI BibTeX RDF	logic circuit simulation, distributed digital logic simulation, logical simulation algorithms, distributed processing, logic CAD, digital simulation, Parallel Virtual Machine, digital circuits
2	Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak	An improved output compaction technique for built-in self-test in VLSI circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	output compaction technique, space compression technique, compaction tree generation, detectable error probability, Boolean difference method, syndrome counter, VLSI, logic testing, probability, built-in self test, built-in self-test, Boolean functions, integrated circuit testing, design for testability, BIST, combinational circuits, combinational circuits, automatic testing, DFT, fault coverage, integrated logic circuits, digital circuits, VLSI circuits, digital integrated circuits
2	Nagaraj Subramanyam, K. G. Praveen, Ramesh Ramani, D. Suryanarayana	CODAC-a characterization system for digital and analog circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	CODAC, characterization system, electrical simulator, procedural interface, customized analysis functions, parallel processing, circuit analysis computing, Monte Carlo methods, circuit CAD, SPICE, SPICE, analog circuits, digital circuits, CAD tool, digital integrated circuits, analogue integrated circuits, circuit analysis, Monte Carlo analysis
2	Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu	Greedy hardware optimization for linear digital circuits using number splitting and refactorization.	IEEE Trans. VLSI Syst.	1993	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Zvi Kohavi	A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion.	IEEE Trans. on CAD of Integrated Circuits and Systems	1992	DBLP DOI BibTeX RDF
2	Karem A. Sakallah, Trevor N. Mudge, Oyekunle A. Olukotun	Analysis and design of latch-controlled synchronous digital circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1992	DBLP DOI BibTeX RDF
2	A. Boneh, Jacob Savir	Statistical Resistance to Detection.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	digital circuits testing, random pattern test, simulation cost, logic testing, integrated circuit testing, automatic testing, fault coverage, fault location, statistical method, digital circuit, digital circuits, detection probabilities
2	Irith Pomeranz, Zvi Kohavi	Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing Module Insertion.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	polynomial complexity algorithms, testing-module insertion, test set merging, fanout free circuits, computational complexity, logic testing, partitioning, combinational circuits, logic CAD, testability, digital circuits, combinatorial circuits, single stuck-at faults, test generation algorithm, placement algorithm
2	Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun	Analysis and Design of Latch-Controlled Synchronous Digital Circuits.	DAC	1990	DBLP DOI BibTeX RDF
2	Randal E. Bryant, Carl-Johan H. Seger	Formal Verification of Digital Circuits Using Symbolic Ternary System Models.	CAV	1990	DBLP DOI BibTeX RDF
2	Kewal K. Saluja, Rajiv Sharma, Charles R. Kime	A concurrent testing technique for digital circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1988	DBLP DOI BibTeX RDF
2	Carlos Delgado Kloos	STREAM: A Scheme Language for Formally Describing Digital Circuits.	PARLE	1987	DBLP DOI BibTeX RDF
2	William H. Kao, Nader Fathi, Chia-Hao Lee	Algorithms for automatic transistor sizing in CMOS digital circuits.	DAC	1985	DBLP DOI BibTeX RDF
2	David M. Lewis	A hardware engine for analogue mode simulation of MOS digital circuits.	DAC	1985	DBLP DOI BibTeX RDF	SPICE
1	Nandish Ashutosh Mehta, Bharadwaj Amrutur	Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo	An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits.	IEEE Trans. on Circuits and Systems	2012	DBLP DOI BibTeX RDF