Search results for "digital integrated circuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Katharina Weinberger, Slava Bulach, Robert Bosch	Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits.	DATE	2008	DBLP DOI BibTeX RDF
2	Srinath R. Naidu	Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah	Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah	Statistical timing for parametric yield prediction of digital integrated circuits.	DAC	2003	DBLP DOI BibTeX RDF	statistical timing, yield prediction
2	Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick	A Genetic Testing Framework for Digital Integrated Circuits. (PDF / PS)	ICTAI	2002	DBLP DOI BibTeX RDF
2	Ireneusz Brzozowski, Andrzej Kos	Minimization of Power Consumption in Digital Integrated Circuits by Reduction of Switching Activity.	EUROMICRO	1999	DBLP DOI BibTeX RDF
2	Kenneth L. Shepard	Design Methodologies for Noise in Digital Integrated Circuits.	DAC	1998	DBLP DOI BibTeX RDF	high-level synthesis, telecommunication
1	Guihai Yan, Xiaowei Li	Online timing variation tolerance for digital integrated circuits.	ITC	2011	DBLP DOI BibTeX RDF
1	C. Hartmann, M. Wieberneit	Investigation on BIST assisted failure analysis on digital integrated circuits.	Microelectronics Reliability	2010	DBLP DOI BibTeX RDF
1	Junxia Ma, Jeremy Lee, Mohammad Tehranipoor, Nisar Ahmed, Patrick Girard	Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	pattern grading, crosstalk, signal integrity, power supply noise, path delay test
1	David Bol, Denis Flandre, Jean-Didier Legat	Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive circuits, subthreshold logic, variability, CMOS digital integrated circuits, ultra-low power
1	David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat	Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic.	ISLPED	2009	DBLP DOI BibTeX RDF	short-channel effects, subthreshold logic, variability, cmos digital integrated circuits, ultra-low power, gate leakage
1	Ho Fai Ko, Nicola Nicolici	Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Ali Alaeldine, Nicolas Lacrampe, Alexandre Boyer, Richard Perdriau, Fabrice Caignet, Mohammed Ramdani, Etienne Sicard, M'hamed Drissi	Comparison among emission and susceptibility reduction techniques for electromagnetic interference in digital integrated circuits.	Microelectronics Journal	2008	DBLP DOI BibTeX RDF
1	Lukas Fujcik, Radimir Vrba, Roman Prokop, Jaromir Hubalek, Pavel Steffan, Hana Hornochova	A Microconductometer Utilizing Bipolar Pulse Method for Electro-Chemical Sensors.	ICONS	2008	DBLP DOI BibTeX RDF	mixed analog-digital integrated circuits
1	Bradley N. Bond, Luca Daniel	Guaranteed stable projection-based model reduction for indefinite and unstable linear systems.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Yatin Hoskote, Sriram R. Vangal, Arvind Singh, Nitin Borkar, Shekhar Borkar	A 5-GHz Mesh Interconnect for a Teraflops Processor.	IEEE Micro	2007	DBLP DOI BibTeX RDF	interconnection fabric, network on chip, mesh, router, CMOS digital integrated circuits, crossbar
1	Ilya Wagner, Valeria Bertacco	Engineering trust with semantic guardians.	DATE	2007	DBLP DOI BibTeX RDF
1	Nicola Nicolici, Xiaoqing Wen	Embedded Tutorial on Low Power Test.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	Parameterized Non-Gaussian Variational Gate Timing Analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Hirotsugu Okuno, Tetsuya Yagi	A Robot Vision System for Collision Avoidance Using a Bio-inspired Algorithm.	ICONIP	2007	DBLP DOI BibTeX RDF
1	Anu Gupta, Bipin Kulkarni	Automation of clock distribution network design for digital integrated circuits using divide and conquer technique.	Integration	2006	DBLP DOI BibTeX RDF
1	Shweta Shah, Nazanin Mansouri, Adrián Núñez-Aldana	Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits.	CONIELECOMP	2006	DBLP DOI BibTeX RDF
1	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	Parameterized block-based non-gaussian statistical gate timing analysis.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky Ramachandran	Solving hard instances of floorplacement.	ISPD	2006	DBLP DOI BibTeX RDF	floorplacement, benchmarks, placement, floorplanning, RTL, circuit layout
1	Luís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira	Variation-Aware, Library Compatible Delay Modeling Strategy.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, J. Piaget, N. Venkateswaran, Jeffrey G. Hemmett	First-Order Incremental Block-Based Statistical Timing Analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Tsu-Jae King	FinFETs for nanoscale CMOS digital integrated circuits.	ICCAD	2005	DBLP BibTeX RDF
1	Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey	A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 Segmented Current Steering CMOS DAC.	VLSI Design	2005	DBLP DOI BibTeX RDF	MOS Analog Circuits, Digital to Analog Conversion, Mixed Analog -Digital Integrated Circuits, Low Power
1	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	moment calculation, sources of variation, sensitivity, statistical timing analysis, elmore delay
1	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	VGTA: Variation Aware Gate Timing Analysis.	ICCD	2005	DBLP DOI BibTeX RDF
1	Rao Desineni, R. D. (Shawn) Blanton	Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction.	VTS	2005	DBLP DOI BibTeX RDF	test generation, Diagnosis, defects, failure analysis, yield enhancement
1	Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti	A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Li Ding 0002, Pinaki Mazumder	A novel technique to improve noise immunity of CMOS dynamic logic circuits.	DAC	2004	DBLP DOI BibTeX RDF	domino logic style, negative differential resistance, noise-tolerant design, digital integrated circuits, dynamic circuits
1	A. Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz	Leakage current reduction by new technique in standby mode.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	subthreshold current, low power, leakage current, digital integrated circuits, static power
1	Rajat Gupta	Digital Design: The components of a new paradigm.	VLSI Design	2004	DBLP DOI BibTeX RDF	design for testability, logic design, Design methodology, microprocessors, digital integrated circuits
1	Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan	First-order incremental block-based statistical timing analysis.	DAC	2004	DBLP DOI BibTeX RDF	variability, incremental, statistical timing
1	Mauro Olivieri, Mirko Scarana, Giuseppe Scotti, Alessandro Trifiletti	Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Yu Zheng, Kenneth L. Shepard	On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Miguel Angel Aguirre Echánove, Jonathan Noel Tombs, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo	UNSHADES-1: An Advanced Tool for In-System Run-Time Hardware Debugging.	FPL	2003	DBLP DOI BibTeX RDF
1	Andrea Acquaviva, Alessandro Bogliolo	A Bottom-Up Approach to On-Chip Signal Integrity.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Steven C. Chan, Kenneth L. Shepard, Dae-Jin Kim	Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick	Functional Test Generation For Digital Integrated Circuits Using A Genetic Algorithm.	GECCO	2002	DBLP BibTeX RDF
1	Rafael Escovar, Roberto Suaya	Transmission line design of clock trees.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Kurt Keutzer, Michael Orshansky	From blind certainty to informed uncertainty.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
1	Dale E. Martin, Philip A. Wilsey, Robert J. Hoekstra, Eric R. Keiter, Scott A. Hutchinson, Thomas V. Russo, Lon J. Waters	Integrating Multiple Parallel Simulation Engines for Mix-Technogy Parallel Simulatio.	Annual Simulation Symposium	2002	DBLP DOI BibTeX RDF
1	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Scan Architecture for Shift and Capture Cycle Power Reduction. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
1	Edith Kussener, Hervé Barthélemy, A. Malherbe, A. Kaiser	Versatile macromodel for the power supply of submicronic CMOS microprocessors based on voltage down DC-DC converter.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Adam Kristof	Improved Digital I/O Ports Enhance Testability of Interconnections.	ITC	2002	DBLP DOI BibTeX RDF
1	Steven C. Chan, Kenneth L. Shepard	Practical Considerations in RLCK Crosstalk Analysis for Digital Integrated Circuits.	ICCAD	2001	DBLP BibTeX RDF
1	S. K. Tewksbury	Challenges Facing Practical DFT for MEMS. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	Microelectromechanical systems, microsystems technologies, fault tolerance, defect tolerance
1	Kenneth L. Shepard	CAD Issues for CMOS VLSI Design in SOI.	ISQED	2001	DBLP DOI BibTeX RDF
1	Luca P. Carloni, Kenneth L. McMillan, Alberto L. Sangiovanni-Vincentelli	Theory of latency-insensitive design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Kenneth L. Shepard, Dae-Jin Kim	Body-voltage estimation in digital PD-SOI circuits and itsapplication to static timing analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Kenneth L. Shepard, Dae-Jin Kim	Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology.	DAC	2000	DBLP DOI BibTeX RDF
1	Antonio G. M. Strollo, Ettore Napoli, Davide De Caro	New clock-gating techniques for low-power flip-flops.	ISLPED	2000	DBLP DOI BibTeX RDF	flip-fops, CMOS digital integrated circuits, transition probability, low-power circuits
1	Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita	A high-speed IDDQ sensor implementation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit feedback, high-speed IDDQ sensor implementation, submicron CMOS process, feedback scheme, floppy-disk controller IDDQ test, current sensor, built-in sensor, 0.35 micron, 50 MHz, integrated circuit testing, CMOS digital integrated circuits, BICS, electric current measurement, electric sensing devices
1	Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José L. Huertas	Testing mixed-signal cores: practical oscillation-based test in an analog macrocell.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	analog macrocell, mixed signal integrated circuit, OBT, mixed-signal macrocell, integrated circuit testing, mixed analogue-digital integrated circuits, oscillation-based test
1	Arabi Keshk, Yukiya Miura, Kozo Kinoshita	Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit oscillations, transistor level networks, feedback oscillation, Byzantine General's problems, logic threshold, logic testing, logic testing, integrated circuit testing, fault coverage, fault location, bridging fault, CMOS circuits, CMOS digital integrated circuits, test vector
1	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
1	Wei-Lun Wang, Kuen-Jong Lee	Accelerated test pattern generators for mixed-mode BIST environments.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
1	Shiyi Xu, Wei Cen	Forecasting the efficiency of test generation algorithms for digital circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
1	Kenneth L. Shepard, Vinod Narayanan, Ron Rose	Harmony: static noise analysis of deep submicron digital integrated circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Christian Dufaza	Multiple Paths Sensitization of Digital Oscillation Built-In Self Test.	ICCD	1999	DBLP DOI BibTeX RDF	DOBIST, Test, Built-In Self Test
1	N. S. Nagaraj, Kenneth L. Shepard, Takahide Inone	Taming Noise in Deep Submicron Digital Integrated Circuits (Panel).	DAC	1998	DBLP DOI BibTeX RDF
1	Karim Arabi, Hassan Ihs, Christian Dufaza, Bozena Kaminska	Digital oscillation-test method for delay and stuck-at fault testing of digital circuits.	ITC	1998	DBLP DOI BibTeX RDF
1	Naim Ben Hamida, Khaled Saab, David Marche, Bozena Kaminska	A perturbation based fault modeling and simulation for mixed-signal circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	analog circuit fault simulation, perturbation fault model, fault abstraction, structural fault modeling, perturbation estimation, fault observation, hierarchical analog fault simulator, complexity, test generation, CMOS, mixed-signal circuits, mixed analogue-digital integrated circuits, functional fault modeling, physical defects
1	Chauchin Su, Yi-Ren Cheng, Yue-Tsang Chen, Shing Tenchen	Analog signal metrology for mixed signal ICs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Analog signal metrology, multiple period low-rate sampled waveform, high-rate sampled waveform, DSP based testing, on-chip ADC, 20 MHz, mixed analogue-digital integrated circuits, Signal reconstruction, mixed signal IC
1	Michael Weeks, M. B. Maaz, H. Krishnamurthy, Paul Shipley, Magdy A. Bayoumi	A prototype chipset for a large scaleable ATM switching node.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	prototype chipset, large scaleable ATM switching node, static logic, packet headers storage, dynamic logic, register file, CMOS digital integrated circuits, banyan network, CMOS IC, 1 micron
1	Gordon W. Roberts	Metrics, techniques and recent developments in mixed-signal testing.	ICCAD	1996	DBLP DOI BibTeX RDF	manufacturing environment, measurement setups, quality, mixed-signal testing, mixed analogue-digital integrated circuits, manufacturing defects, product cost
1	Julien Dunoyer, Nizar Abdallah, Pirouz Bazargan-Sabet	A symbolic simulation approach in resolving signals' correlation.	Annual Simulation Symposium	1996	DBLP DOI BibTeX RDF	signal resolution, signal correlation resolution, symbolic simulation approach, evaluation package, signal transition density, specification levels, first order clue, independent inputs, binary decision diagram concept, algorithms, VLSI, probability, logic CAD, digital simulation, design process, decision theory, circuit analysis computing, integrated circuit design, circuit CAD, digital circuits, subroutines, symbol manipulation, power dissipation, correlation methods, digital integrated circuits, signal probability, probabilistic approach, synthesis tools
1	Shriram Kulkarni, Pinaki Mazumder, George I. Haddad	A high-speed 32-bit parallel correlator for spread spectrum communication.	VLSI Design	1996	DBLP DOI BibTeX RDF	pseudonoise codes, radio equipment, high speed pipelined digital parallel correlator, lattice field programmable gate array, 87 MHz, 11.5 ns, field programmable gate arrays, parallel processing, data stream, correlators, CDMA, pipeline processing, CMOS integrated circuit, CMOS digital integrated circuits, transceiver, spread spectrum communication, spread spectrum communication, digital radio, 32 bit, PN sequence
1	Rajesh Ramadoss, Michael L. Bushnell	Test generation for mixed-signal devices using signal flow graphs.	VLSI Design	1996	DBLP DOI BibTeX RDF	mixed-signal devices, reverse simulation approach, component tolerances, analog input sinusoids, test generation results, analog backtrace method, high-order analog circuits, fault diagnosis, test generation, integrated circuit testing, automatic testing, circuit analysis computing, mixed analogue-digital integrated circuits, signal flow graphs, signal flow graphs, nonlinear circuits
1	Chuan-Yu Wang, Kaushik Roy	Maximum power estimation for CMOS circuits using deterministic and statistic approaches.	VLSI Design	1996	DBLP DOI BibTeX RDF	maximum power estimation, deterministic approach, instantaneous power consumption, ATG technique, Monte Carlo based technique, computational complexity, VLSI, lower bound, statistical analysis, automatic testing, circuit analysis computing, Monte Carlo methods, automatic test generation, VLSI circuits, CMOS circuits, CMOS digital integrated circuits, statistic approach
1	Karim Arabi, Bozena Kaminska	Oscillation-test strategy for analog and mixed-signal integrated circuits.	VTS	1996	DBLP DOI BibTeX RDF	circuit oscillations, oscillation test strategy, analog ICs, low-cost test method, oscillation frequency deviation, wafer-probe testing, final production testing, ASIC testing, integrated circuit testing, operational amplifiers, analogue integrated circuits, mixed analogue-digital integrated circuits, production testing, analogue-digital conversion, mixed-signal ICs
1	S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	A new test pattern generation method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits
1	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.	VTS	1996	DBLP DOI BibTeX RDF	GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm
1	Chen-Yang Pan, Kwang-Ting Cheng	Implicit functional testing for analog circuits.	VTS	1996	DBLP DOI BibTeX RDF	implicit functional testing, linear time-invariant circuits, impulse response samples, pseudo-random technique, production testing time, yield coverages, VLSI, integrated circuit testing, fault coverage, analog circuits, analogue integrated circuits, mixed analogue-digital integrated circuits, transient response
1	John W. Sheppard, William R. Simpson	Improving the accuracy of diagnostics provided by fault dictionaries.	VTS	1996	DBLP DOI BibTeX RDF	diagnostics accuracy improvement, digital circuit diagnosis, information flow model, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, circuit analysis computing, digital integrated circuits, fault dictionaries, nearest neighbor classification
1	Andrzej Materka, Michal Strzelecki	Parametric testing of mixed-signal circuits by ANN processing of transient responses.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	mixed analog-digital integrated circuits, transient power, supply current, neural networks, integrated circuit testing
1	Mahadevamurty Nemani, Farid N. Najm	Towards a high-level power estimation capability [digital ICs].	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
1	Sachin S. Sapatnekar, Weitong Chuang	Power vs. delay in gate sizing: conflicting objectives?	ICCAD	1995	DBLP DOI BibTeX RDF	power-delay tradeoffs, short-circuit power, logic design, logic CAD, integrated circuit design, circuit CAD, optimization problem, circuit optimisation, gate sizing, convex programming, CMOS digital integrated circuits, dynamic power
1	Kei-Yong Khoo, Alan N. Willson Jr.	Single-transistor transparent-latch clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits
1	Louis Monier, Ramsey W. Haddad, Jeremy Dion	Recursive layout generation.	ARVLSI	1995	DBLP DOI BibTeX RDF	BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, hand-drawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration
1	Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III	A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.	ARVLSI	1995	DBLP DOI BibTeX RDF	high-speed fine-resolution pattern generation, data signals, edge placement, matched delays, MOSIS CMOS technology, 100 ps, 833 Mbit/s, architecture, delays, test pattern generators, network interfaces, CMOS digital integrated circuits, 1.2 micron
1	Michel Renovell, Florence Azaïs, Yves Bertrand	A design-for-test technique for multistage analog circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	design-for-test technique, multistage analog circuits, DFT approach, op-amp-based modules, testability resources, transparent paths, external I/O, local I/O, test mode, on-chip digital resources, analog response penalty, controllability, controllability, integrated circuit testing, design for testability, observability, observability, mixed-signal circuits, mixed analogue-digital integrated circuits, test management, production testing
1	Janusz Rzeszut, Bozena Kaminska, Yvon Savaria	A new method for testing mixed analog and digital circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	charge-coupled device circuits, mixed analog and digital circuits, analog test points, simultaneous observation, analog multiplexer, signal path, analog shift register, input voltage, integrated circuit testing, shift registers, mixed analogue-digital integrated circuits, charge coupled device, analogue processing circuits
1	Yeong-Ruey Shieh, Cheng-Wen Wu	DC control and observation structures for analog circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	level-sensitive scan-design, test points, DC voltage levels, diagnosis capability, calibration process, read-out voltage levels, VLSI, VLSI, fault diagnosis, controllability, controllability, integrated circuit testing, calibration, observability, observability, analog circuits, mixed signal circuits, mixed analogue-digital integrated circuits
1	A. Agrawal, A. Raju, S. Varadarajan, Magdy A. Bayoumi	A scalable shared buffer ATM switch architecture.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	electronic switching systems, field effect transistor switches, scalable shared buffer ATM switch architecture, memory bandwidth requirement, maximum crosspoint switch size, buffer memory size, access time reduction, multiple buffer memories, 8/spl times/8 switch, 1 mum, 622 Mbit/s, asynchronous transfer mode, asynchronous transfer mode, shared memory systems, buffer storage, CMOS technology, CMOS digital integrated circuits, B-ISDN, B-ISDN, switching circuits, parallel access
1	Wilbert H. F. J. Körver	A universal formalization of the effects of threshold voltages for discrete switch-level circuit models.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	field effect transistor switches, threshold voltage effects, discrete switch-level circuit models, universal formalization, switch imperfection, CMOS design, demolition degree, CMOS digital integrated circuits, state transitions, integrated circuit modelling, switching circuits
1	N. Ranganathan, K. B. Doreswamy	A systolic algorithm and architecture for image thinning.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	image thinning, 4-distance transform, single VLSI chip, 2.59 ms, 0.327 ms, parallel algorithms, image processing, VLSI, parallelism, skeleton, systolic arrays, CMOS, pipeline processing, VLSI architecture, digital signal processing chips, processing elements, CMOS digital integrated circuits, linear time, systolic architecture, systolic algorithm, multiple objects
1	John Bunda, Donald S. Fussell, William C. Athas	Energy-efficient instruction set architecture for CMOS microprocessors.	HICSS	1995	DBLP DOI BibTeX RDF	energy-efficient instruction set architecture, CMOS microprocessors, portable battery-based applications, performance-driven designs, processor architecture tradeoffs, program encoding size, instruction set richness, energy cost, speculative instruction fetching, execution resources, instruction-level parallel machines, multiple-path instruction fetching, high execution bandwidth, power management, microprocessor chips, instruction sets, power dissipation, CMOS digital integrated circuits, reduced instruction set computing, cooling, design constraint, instruction delivery, code density
1	Thomas D. Burd, Robert W. Brodersen	Energy efficient CMOS microprocessor design.	HICSS	1995	DBLP DOI BibTeX RDF	energy efficient CMOS microprocessor design, portable electronics, battery weight, battery size, heat dissipation, computation modes, power analysis methodology, energy efficiency quantification, computer architecture, computer architectures, throughput, parallel machines, energy consumption, energy conservation, microprocessor chips, design principles, power dissipation, CMOS digital integrated circuits, integrated circuit modelling, cooling, figures of merit, desktop computers
1	Mark R. Greenstreet	Implementing a STARI chip. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	STARI chip, high-speed signaling technique, MOSIS 2/spl mu/ CMOS process, self-timed FIFO, robust compensation, clock skew, digital signal processing chips, CMOS digital integrated circuits, self-timed circuits, synchronous circuits, 2 micron, timing circuits
1	Bret Stott, Dave Johnson, Venkatesh Akella	Asynchronous 2-D discrete cosine transform core processor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron
1	S. Muller	A new programmable VLSI architecture for histogram and statistics computation in different windows. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	programmable VLSI architecture, histogram computation, grey-scale histogram, image preprocessing methods, inhomogeneous illumination elimination, simple increment operations, histogrammer, window handling, arithmetic unit configuration, memory configuration, equalisation, simulation, image segmentation, VLSI, segmentation, data compression, data compression, statistics, image enhancement, image enhancement, texture analysis, image texture, digital signal processing chips, CMOS technology, binary images, CMOS digital integrated circuits, co-occurrence-matrix, statistics computation
1	Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak	An improved output compaction technique for built-in self-test in VLSI circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	output compaction technique, space compression technique, compaction tree generation, detectable error probability, Boolean difference method, syndrome counter, VLSI, logic testing, probability, built-in self test, built-in self-test, Boolean functions, integrated circuit testing, design for testability, BIST, combinational circuits, combinational circuits, automatic testing, DFT, fault coverage, integrated logic circuits, digital circuits, VLSI circuits, digital integrated circuits
1	Anirudh Devgan, Ronald A. Rohrer	Efficient simulation of interconnect and mixed analog-digital circuits in ACES.	VLSI Design	1995	DBLP DOI BibTeX RDF	adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation
1	Debabrata Ghosh, Soumitra Kumar Nandy	Wave pipelined architecture folding: a method to achieve low power and low area.	VLSI Design	1995	DBLP DOI BibTeX RDF	wave pipelined architecture folding, clock-free wave pipelining scheme, chip area reduction, VLSI, low power design, logic design, pipeline processing, integrated circuit design, digital integrated circuits
1	Jason P. Hurst, Adit D. Singh	A differential built-in current sensor design for high speed IDDQ testing.	VLSI Design	1995	DBLP DOI BibTeX RDF	built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices