Search results for "digital signal processing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Chin-Fu Kuo, Tei-Wei Kuo, Cheng Chang	Real-Time Digital Signal Processing of Phased Array Radars.	IEEE Trans. Parallel Distrib. Syst.	2003	DBLP DOI BibTeX RDF	component-oriented signal processor, system capacity estimation, digital signal processing, real-time scheduling, Phased array radar
3	Anantha Chandrakasan	Ultra low power digital signal processing.	VLSI Design	1996	DBLP DOI BibTeX RDF	ultra low power digital signal processing, portable wireless device, capacitance minimization, spatial signal correlations, temporal signal correlations, re-synchronization, operation reduction, 1 V, logic design, DSP, power consumption, switching, integrated circuit design, voltage scaling, digital signal processing chips, circuit optimisation, circuit design, data representation, circuit optimization, glitching, architecture optimization
3	Vojin Zivojnovic, Stefan Pees, C. Schälger, Markus Willems, R. Schoenen, Heinrich Meyr	DSP Processor/Compiler Co-Design: A Quantitative Approach. (PDF / PS)	ISSS	1996	DBLP DOI BibTeX RDF	processor/compiler codesign, benchmarking methodology, DSPstone, fast processor simulation, SuperSim, compiled processor simulation, performance evaluation, embedded systems, digital signal processing, digital signal processing chips, LISA, top-down approach, machine description
3	Claude Thibeault	Detection and location of faults and defects using digital signal processing.	VTS	1995	DBLP DOI BibTeX RDF	sampled current, sampled voltage, quiescent current, parasitic resistive contacts, DSP technique, fault diagnosis, logic testing, integrated circuit testing, fault detection, signal processing, diagnosis, digital signal processing, fault location, fault location, defects, digital integrated circuits, test method
2	Krishna V. Palem, Lakshmi N. Chakrapani, Zvi M. Kedem, Lingamneni Avinash, Kirthi Krishna Muntimadugu	Sustaining moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects.	CASES	2009	DBLP DOI BibTeX RDF	approximate arithmetic, approximate design, probabilistic CMOS, probabilistic arithmetic, probabilistic design, digital signal processing
2	Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala	Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing.	PATMOS	2008	DBLP DOI BibTeX RDF	coarse-grain array, DSP, Reconfigurable systems
2	Xiaojuan Chen, Yaru Han	Design and Implementation of Digital Signal Processing Soft Laboratory.	CSSE	2008	DBLP DOI BibTeX RDF
2	Aníbal Rodríguez Fuentes, Juan V. Lorenzo-Ginori, Ricardo Grau Ábalo	Coding Region Prediction in Genomic Sequences Using a Combination of Digital Signal Processing Approaches.	CIARP	2007	DBLP DOI BibTeX RDF	Coding region prediction, Computational load reduction, Bioinformatics, Digital Signal Processing, Fourier Transform
2	Yang Liu, Tong Zhang	On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing.	ISLPED	2007	DBLP DOI BibTeX RDF	voltage overscaling, low power, signal processing
2	Jan Vlach, Pavel Rajmic, Jiri Prinosil, Josef Vyoral, Ivan Mica	Optimized discrete wavelet transform to real-time digital signal processing.	PWC	2007	DBLP DOI BibTeX RDF
2	Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin	A design methodology for space-time adapter.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	communication and interface synthesis, digital signal processing and multimedia applications, RTL design
2	Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung	AsAP: A Fine-Grained Many-Core Platform for DSP Applications.	IEEE Micro	2007	DBLP DOI BibTeX RDF	MIMD processors, GALS networking, embedded systems, multiprocessors, digital signal processing, microarchitecture, special-purpose and application-based systems
2	Zhan-Li Sun, Deshuang Huang, Yiu-ming Cheung	Erratum to "Extracting nonlinear features for multispectral images by FCMC and KPCA" [Digital Signal Processing 15 (2005) 331-346].	Digital Signal Processing	2006	DBLP DOI BibTeX RDF
2	Nacer-Eddine Zergainoh, Ludovic Tambour, Ahmed Amine Jerraya	Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Byonghyo Shim, Naresh R. Shanbhag	Energy-efficient soft error-tolerant digital signal processing.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Sylvain Huet, Emmanuel Casseau, Olivier Pasquier	A Computation Core for Communication Refinement of Digital Signal Processing Algorithms.	DSD	2006	DBLP DOI BibTeX RDF
2	Zohar Dvir	Web-Based Remote Digital Signal Processing (DSP) Laboratory Using The Integrated Learning Methodology (ILM).	ITRE	2006	DBLP DOI BibTeX RDF
2	Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin	A formal method for hardware IP design and integration under I/O and timing constraints.	ACM Trans. Embedded Comput. Syst.	2006	DBLP DOI BibTeX RDF	IP design and integration, communication interface unit, constrained synthesis, digital signal processing and multimedia applications, SoC
2	Andrzej Czyzewski	Applications of Knowledge Technologies to Sound and Vision Engineering.	RSKT	2006	DBLP DOI BibTeX RDF	Sound & Vision Engineering, Knowledge Technologies, Digital Signal Processing
2	Yih-Chyun Jenq	Digital Signal Processing with Interleaved ADC Systems.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	interleaved ADC, DSP algorithm, aliasing, filter banks, A/D converter
2	Alireza Shoa, Shahram Shirani	Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	FPGA, DSP, Run-Time Reconfiguration (RTR)
2	Jianxin Wang, Lijuan Liu, Weijia Jia	The Design and Implementation of Digital Signal Processing Virtual Lab Based on Components.	ICWL	2005	DBLP DOI BibTeX RDF	components, DSP, Virtual Laboratory, Java Beans
2	Jaehyun Baek, Ju Hyung Hong, Myung Hoon Sunwoo	Novel digital signal processing unit for Ethernet receiver.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Hung Yang Ko, Yi-Chiuan Wang, An-Yeu Wu	Digital signal processing engine design for polar transmitter in wireless communication systems.	ISCAS	2005	DBLP DOI BibTeX RDF
2	William R. Dieter, Srabosti Datta, Wong Key Kai	Power reduction by varying sampling rate.	ISLPED	2005	DBLP DOI BibTeX RDF	real-time audio, digital signal processing, voltage scaling, power-aware, frequency scaling
2	Juan A. Rico-Gallego, Juan Carlos Díaz Martín, Jesús M. Álvarez Llorente	An MPI Implementation for Distributed Signal Processing.	PVM/MPI	2005	DBLP DOI BibTeX RDF	DSP multicomputers, communication middleware, MPI, Digital signal processing, digital signal processors
2	Mladen Berekovic, Sören Moch, Peter Pirsch	A scalable, clustered SMT processor for digital signal processing.	SIGARCH Computer Architecture News	2004	DBLP DOI BibTeX RDF
2	Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon	Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability.	SAMOS	2004	DBLP DOI BibTeX RDF
2	Debasis Mitra, Michael Smith	Digital Signal Processing in Predicting Secondary Structures of Proteins.	IEA/AIE	2004	DBLP DOI BibTeX RDF
2	L.-P. Lafrance, Yvon Savaria	A Framework for Implementing Reusable Digital Signal Processing Modules.	IWSOC	2004	DBLP DOI BibTeX RDF
2	Beibei Ren, Anru Wang, Joyopriya Bakshi, Kai Liu, Wei Li, Wayne Wei-Ming Dai	A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications.	DATE	2004	DBLP DOI BibTeX RDF
2	Changchun Shi, Robert W. Brodersen	Automated fixed-point data-type optimization tool for signal processing and communication systems.	DAC	2004	DBLP DOI BibTeX RDF	optimization, FPGA, digital signal processing, ASIC, communication systems, fixed-point arithmetic
2	Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum, Eduardo Luis Rhod	Merging a DSP-Oriented Signal Integrity Technique and SW-Based Fault Handling Mechanisms to Ensure Reliable DSP Systems.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	digital signal processing (DSP) systems, electromagnetic interference (EMI), speech recognition system (SRS), on-line testing, noise immunity
2	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk	Wordlength optimization for linear digital signal processing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
2	Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum	Briefing a New Approach to Improve the EMI Immunity of DSP Systems.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	Digital Signal Processing (DSP) Systems, Electromagnetic Interference (EMI), On-Line Testing, Noise Immunity
2	Javier Ramírez, Antonio García, Uwe Meyer-Bäse, Fred J. Taylor, Antonio Lloris-Ruíz	Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	field-programmable logic, digital signal processing, discrete wavelet transform, residue number system, distributed arithmetic
2	Franz Franchetti, Markus Püschel	A SIMD Vectorizing Compiler for Digital Signal Processing Algorithms. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF	code generation, FFT, discrete cosine transform, discrete Fourier transform, SIMD, SPIRAL, SSE, vector code
2	Naresh R. Shanbhag	Reliable and energy-efficient digital signal processing.	DAC	2002	DBLP DOI BibTeX RDF	reliability, communications, low-power, energy-efficiency, noise, broadband, noise-tolerance, deep submicron
2	Paijlo R. De Aguiar, Edliardo Carlos Bianchi, Paulo José Amaral Serni, Patrik N. Lanconi	Control of thermal damage in grinding by digital signal processing of raw acoustic emission.	ICARCV	2002	DBLP DOI BibTeX RDF
2	Daniel Menard, Daniel Chillet, François Charot, Olivier Sentieys	Automatic floating-point to fixed-point conversion for DSP code generation.	CASES	2002	DBLP DOI BibTeX RDF	digital signal processing systems, floating-point to fixed-point conversion, quantization noise, code generation, DSP, fixed-point
2	Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.	Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	Speech-Recognition Systems (SRS), Recovery Blocks Scheme, Digital Signal Processing (DSP), On-Line Testing, Performance Degradation, Noise Immunity
2	Rajamohana Hegde, Naresh R. Shanbhag	Soft digital signal processing.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
2	Russell Tessier, Wayne Burleson	Reconfigurable Computing for Digital Signal Processing: A Survey.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	FPGA, survey, signal processing, reconfigurable computing
2	Olaf Lüthje, Martin Coors, Holger Keding	A novel approach to code analysis of digital signal processing systems.	CASES	2001	DBLP DOI BibTeX RDF
2	Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.	A New Approach to Design Reliable Real-Time Speech Recognition Systems.	IOLTW	2001	DBLP DOI BibTeX RDF	HW-SW Codesign, Digital Signal Processing - DSP, Speech-Recognition Systems, Fault-Tolerance Techniques, Transparent BIST, Performance Degradation, Area overhead
2	Uwe Meyer-Bäse, Antonio García, Fred J. Taylor	Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer
2	Jean-Michel Raczinski, Stéphane Sladek	The Modular Architecture of SYNTHUP, FPFA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing.	FPL	2000	DBLP DOI BibTeX RDF
2	Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya	Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	digital signal processing, rapid prototyping, dataflow, software synthesis, configurable computing
2	S. Ramanathan, S. K. Nandy, V. Visvanathan	Reconfigurable Filter Coprocessor Architecture for DSP Applications.	VLSI Signal Processing	2000	DBLP DOI BibTeX RDF	reconfigurable coprocessors, filter coprocessor architecture, systolic architectures and digital signal processing, pipelined architectures, low-power architectures
2	B. Bosi, Guy Bois, Yvon Savaria	Reconfigurable pipelined 2-D convolvers for fast digital signal processing.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
2	Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki	A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing.	ASP-DAC	1999	DBLP DOI BibTeX RDF
2	Tyler J. Moeller, David R. Martinez	Field Programmable Gate Array Based Radar Front-End Digital Signal Processing.	FCCM	1999	DBLP DOI BibTeX RDF
2	David W. Trainor, Roger F. Woods, John V. McCanny	Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS".	VLSI Signal Processing	1997	DBLP DOI BibTeX RDF
2	Gerhard Fettweis	Design methodology for digital signal processing.	ASAP	1997	DBLP DOI BibTeX RDF	semiconductor integration density, architecture heterogeneity, hardwired digital circuits, software programmed signal processors, flexibly mapping, system simulation tools, system design, signal processing, digital signal processing, design methodology, data transfer, data manipulation
2	Vassil S. Dimitrov, Graham A. Jullien, William C. Miller	Theory and applications for a double-base number system.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	basic arithmetic operations, index calculus, logarithmic-like arithmetic, hardware reductions, lookup table size, inner product computation, modular exponentiation computation, cryptography, digital signal processing, number theory, sparse representation, double-base number system, geometric interpretation
2	Paul F. Stelling, Vojin G. Oklobdzija	Implementing Multiply-Accumulate Operation in Multiplication Time.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	multiply-accumulate operation, multiplication time, optimal delays, instruction time, optimal multiply-accumulate circuit, RISC CPU, partial product reduction tree, final adder, digital signal processing, power savings, multiplying circuits, circuit design, VLSI circuits, parallel multiplier, processor performance, video applications, graphics applications, clock speed
2	Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee	Optimized software synthesis for synchronous dataflow.	ASAP	1997	DBLP DOI BibTeX RDF	optimized software synthesis, programmable digital signal processors, off-chip memory, real-time systems, digital signal processing, synchronous dataflow, graphical programs
2	Jens Horstmannshoff, Thorsten Grötker, Heinrich Meyr	Mapping multirate dataflow to complex RT level hardware models.	ASAP	1997	DBLP DOI BibTeX RDF	multirate dataflow mapping, complex RT level hardware models, digital signal processing systems, algorithm development phase, data flow specification, RTL target architecture, HDL code generation, cycle based timing model, ASIC design complexity, multirate dataflow graphs, signal processing, hardware architecture
2	Adel Baganne, Jean Luc Philippe, Eric Martin	Hardware interface design for real time embedded systems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	real time digital signal processing, hardware interface design, codesign approach, storage components, hardware-software components, I/O data modeling style, hardware I/O transfer sequences, high level synthesis tool, GAUT, I/O transfer order, cosynthesis tool, real-time systems, ASICs, timing constraints, generic model, data communication, real time embedded systems, formal technique, interface specification, FFT algorithms, allocation problem
2	Cheng Chang, Chien-Chung Chen, Yao-Liang Chen, Fu-Shin Huang	Real-time scheduling in a programmable radar signal processor.	RTCSA	1997	DBLP DOI BibTeX RDF	programmable radar signal processor, parallel multi-processor architecture, real-time scheduling algorithm, digital signal processing, real-time scheduling, processing speed, radar signal processing
2	Matt Kaufmann, J. Strother Moore	An Industrial Strength Theorem Prover for a Logic Based on Common Lisp.	IEEE Trans. Software Eng.	1997	DBLP DOI BibTeX RDF	total functions, microcode verification, floating point division, Formal verification, digital signal processing, type checking, computational logic, automatic theorem proving, partial functions
2	Liangkung Lin, G. Robert Redinbo	Efficient fault protection of block gradient-based adaptive filters. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	fault protection, block gradient-based adaptive filters, block processing techniques, sequential implementations, finite word length, fault-tolerant techniques, block adaptive filtering algorithms, fine-grained approach, computational complexity, complexity, fault tolerant computing, signal processing, encoding, adaptive filters, FIR filters, FIR filters, computational power, checksums, encoding scheme, digital signal processing applications
2	P. Wauters, Marc Engels, Rudy Lauwereins, J. A. Peperstraete	Cyclo-Dynamic Dataflow.	PDP	1996	DBLP DOI BibTeX RDF	cyclo dynamic data flow, CDDF, data flow model, real time digital signal processing, cyclo static dataflow, data dependent control flow, data flow languages, Boolean data flow model, scheduling, real-time systems, semantics, signal processing, parallel languages, data flow computing, automatic tools
2	Sati Banerjee, Paul M. Chau, Ronald D. Fellman	Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems.	VLSI Signal Processing	1995	DBLP DOI BibTeX RDF
2	Rainer Leupers, Peter Marwedel	Time-constrained code compaction for DSPs.	ISSS	1995	DBLP DOI BibTeX RDF	code generation techniques, digital signal processing algorithms, encoding restrictions, exact timing behavior, hard real-time constraints, integer programming model, local code compaction, programmable DSP, rigid heuristics, time-constrained code compaction, real-time systems, timing, integer programming, instruction-level parallelism, source coding, automatic programming, digital signal processing chips, side-effects
2	Kala Srivatsan, Chaitali Chakrabarti, Lori Lucke	Low power data format converter design using semi-static register allocation. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	code convertors, low power data format converter design, semi-static register allocation, processing modules, VLSI, linear programming, integer programming, signal processing, digital signal processing, power consumption, integer linear programming, heuristic programming, heuristic programming, VLSI implementations
2	David M. Goblirsch	An introduction to Haskell with applications to digital signal processing.	SAC	1994	DBLP DOI BibTeX RDF	functional programming, digital signal-processing, Haskell, Haskell
2	W. Kenneth Jenkins, Bernard A. Schnaufer, A. J. Mansen	Combined system-level redundancy and modular arithmetic for fault tolerant digital signal processing.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
2	Tobias G. Noll	Carry-save architectures for high-speed digital signal processing.	VLSI Signal Processing	1991	DBLP DOI BibTeX RDF
2	Ivan P. Radivojevic, Jayantha A. Herath	Executing DSP Applications in a Fine-Grained Dataflow Environment.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	fine-grained dataflow architecture, numerically intensive digital signal processing, pipelined data-parallel algorithms, high-level language programming blocks, logical fine-grained decomposition, serial fraction, fine-grained general-purpose dataflow computing, parallel algorithms, parallel architectures, pipeline processing, precedence relations, computerised signal processing, DSP applications
2	Chien-Chun Su, Hao-Yung Lo	An Algorithm for Scaling and Single Residue Error Correction in Residue Number Systems.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	single residue digit error correction, mixed radix conversion, redundant digits, scaling error, error-correction circuit with scaling, fault tolerant computing, digital signal processing, digital arithmetic, error correction, residue number systems, RNS, fault-tolerant systems, digital signal processing chips, number theory, lookup table
2	Graham A. Jullien, P. D. Bird, J. T. Carr, M. Taheri, William C. Miller	An efficient bit-level systolic cell design for finite ring digital signal processing applications.	VLSI Signal Processing	1989	DBLP DOI BibTeX RDF
2	Brian C. McKinney, Fayez El Guibaly	A Multiple-Access Pipeline Architecture for Digital Signal Processing.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	multiple-access pipeline architecture, CMOS processor, processing concurrency, microprogram control, floating-point data, parallel architectures, digital signal processing, digital arithmetic, computerised signal processing, arithmetic logic unit
1	Gabriel Caffarena, Olivier Sentieys, Daniel Menard, Juan A. López, David Novo	Quantization of VLSI digital signal processing systems.	EURASIP J. Adv. Sig. Proc.	2012	DBLP DOI BibTeX RDF
1	Etsushi Yamazaki, Masahito Tomizawa, Yutaka Miyamoto	100-Gb/s optical transport network and beyond employing digital signal processing.	IEEE Communications Magazine	2012	DBLP DOI BibTeX RDF
1	Ron Schneiderman	Digital Signal Processing Gets Big Play in Music [Special Reports].	IEEE Signal Process. Mag.	2012	DBLP DOI BibTeX RDF
1	Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel	Computer Generation of Hardware for Linear Digital Signal Processing Transforms.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
1	Davide Anastasia, Yiannis Andreopoulos	Throughput-Distortion Computation of Generic Matrix Multiplication: Toward a Computation Channel for Digital Signal Processing Systems.	IEEE Transactions on Signal Processing	2012	DBLP DOI BibTeX RDF
1	Reinhard Enne, Miodrag Nikolic, Horst Zimmermann	A maximum power-point tracker without digital signal processing in 0.35μm CMOS for automotive applications.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Suresh N. Mali, Pradeep M. Patil, Rajesh M. Jalnekar	Robust and secured image-adaptive data hiding.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	F. Javier López-Martínez, Eduardo del Castillo-Sánchez, Eduardo Martos-Naya, José Tomás Entrambasaguas	Performance evaluation of preamble detectors for 3GPP-LTE physical random access channel.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Jie Lin, Guangming Shi, Xuyang Chen, Fei Qi, Li Zhang, Xuemei Xie	High-resolution ranging method based on low-rate parallel random sampling.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Mehmet Burak Guldogan, Orhan Arikan	Cross-ambiguity function domain multipath channel parameter estimation.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Alan P. Pinheiro, David E. Stewart, Carlos D. Maciel, José C. Pereira, Suely Oliveira	Analysis of nonlinear dynamics of vocal folds using high-speed video observation and biomechanical modeling.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Tamás Kovács	A novel optimization based method for separation of periodic signals.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Yener Ülker, Bilge Günsel	Multiple model target tracking with variable rate particle filters.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Ercan E. Kuruoglu	Editorial.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Xinmin Liu, Zongli Lin, Scott T. Acton	A grid-based Bayesian approach to robust visual tracking.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Anil Kumar, S. M. Rafi, G. K. Singh	A hybrid method for designing linear-phase quadrature mirror filter bank.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Alan J. Terry, Munir Zaman, John Illingworth	Sensor fusion by a novel algorithm for time delay estimation.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Omar Nibouche, J. Jiang, P. Trundle	Analysis of performance of palmprint matching with enforced sparsity.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	S. Jothilakshmi, Vennila Ramalingam, S. Palanivel	A hierarchical language identification system for Indian languages.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Tarik Yardibi, Jian Li, Peter Stoica, Louis N. Cattafesta	Sparse representations and sphere decoding for array signal processing.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Ying Wen, Lianghua He, Pengfei Shi	Face recognition using difference vector plus KPCA.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Ali Cafer Gurbuz, James H. McClellan, Waymond R. Scott Jr.	Compressive sensing of underground structures using GPR.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Qingyue Zhang, Ling Wang, Wenchang Sun	Signal denoising with average sampling.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Jianhua Luo, Yuemin Zhu	Denoising of medical images using a reconstruction-average mechanism.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Quan Quan, Kai-Yuan Cai	Time-domain analysis of the Savitzky-Golay filters.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Esra Saatci, Aydin Akan	Posterior Cramer-Rao Lower Bounds for dual Kalman estimation.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	A. Mejías, S. Romero, F. Moreno	A new algorithm to extract the lines and edges through orthogonal projections.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF