Search results for "digital signal processing chips"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Ameet Bagwe, Rubin A. Parekhji	Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fault coverage enhancement, embedded core based systems, test constraints, Texas Instruments TMS320C27xx, memory wrapper logic, fault diagnosis, logic testing, integrated circuit testing, application specific integrated circuits, functional testing, digital signal processing chips, fault analysis
1	Ismet Bayraktaroglu, Alex Orailoglu	Accumulation-based concurrent fault detection for linear digital state variable systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	concurrent fault detection, linear digital state variable systems, algorithmic fault detection scheme, accumulation-based approach, fault diagnosis, logic testing, error detection, error detection, linear systems, digital filters, digital signal processing chips, digital systems, area overhead
1	Nuno Roma, Leonel Sousa	In the Development and Evaluation of Specialized Processors for Computing High-Order 2-D Image Moments in Real-Time.	CAMP	2000	DBLP DOI BibTeX RDF	specialized processors, high-order 2-D image moments, computational intensive task, systolic processing, programmable digital processors, configurable hardware logic, real-time system, image analysis, object modelling, floating-point arithmetic, digital signal processing chips, object matching
1	Hercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr.	Realization of a nonlinear digital filter on a DSP array processor.	ASAP	1997	DBLP DOI BibTeX RDF	nonlinear digital filter, third-order Volterra digital filtering algorithm, AT&T DSP-3 parallel processor, nonlinear communication channel equalization, 64-QAM signal constellation, performance evaluation, digital signal processing chips, time-skewing
1	Chouki Aktouf, Ghassan Al Hayek, Chantal Robach	Concurrent testing of VLSI digital signal processors using mutation based testing. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	VLSI digital signal processor, software technique, hardware device, fault latency, computation, DSP, fault coverage, Mutation testing, digital signal processing chips, concurrent testing
1	Marco Mattavelli, Sylvain Brunetton, Daniel Mlynek	A Parallel Multimedia Processor for Macroblock Based Compression Standards. (PDF / PS)	ICIP	1997	DBLP DOI BibTeX RDF	parallel multimedia processor, macroblock based compression standards, block-based video processing algorithms, DGP, digital generic processor, generic system architecture, pixel processors, RISC controller, video processing algorithms, video effects, window clipping, H.261, 1.7 GIPS, 54 MHz, 0.5 micron, code, video compression, digital filtering, MPEG-2, digital signal processing chips, H.263, SIMD architecture, MPEG-1
1	Wei Zhao, Christos A. Papachristou	Synthesis of reusable DSP cores based on multiple behaviors.	ICCAD	1996	DBLP DOI BibTeX RDF	RTL components, RTL structure, design process complexity, design time, multiple behaviors, reusable DSP cores synthesis, digital signal processing chips
1	Chris H. L. Moller, Gerald G. Pechanek	Architectural simulation system for M.f.a.s.t.	Annual Simulation Symposium	1996	DBLP DOI BibTeX RDF	pulse transformers, architectural simulation system, architecture verification, Mwave folded array signal transform processor, single chip scalable very long instruction word processor array, independent processes, socket mechanism, execution-unit operations, execution emulation, M.f.a.s.t. processor, parallel architectures, virtual machines, reconfigurable architectures, digital signal processing chips, instruction sets, functional models, array signal processing, simulator performance
1	Mohan Vishwanath, Robert Michael Owens	A Common Architecture For The DWT and IDWT.	ASAP	1996	DBLP DOI BibTeX RDF	inverse discrete wavelet transform, j'th octave, wavelet transforms, discrete wavelet transform, digital signal processing chips, filter bank, single chip
1	Vojin Zivojnovic, Stefan Pees, C. Schälger, Markus Willems, R. Schoenen, Heinrich Meyr	DSP Processor/Compiler Co-Design: A Quantitative Approach. (PDF / PS)	ISSS	1996	DBLP DOI BibTeX RDF	processor/compiler codesign, benchmarking methodology, DSPstone, fast processor simulation, SuperSim, compiled processor simulation, performance evaluation, embedded systems, digital signal processing, digital signal processing chips, LISA, top-down approach, machine description
1	Anantha Chandrakasan	Ultra low power digital signal processing.	VLSI Design	1996	DBLP DOI BibTeX RDF	ultra low power digital signal processing, portable wireless device, capacitance minimization, spatial signal correlations, temporal signal correlations, re-synchronization, operation reduction, 1 V, logic design, DSP, power consumption, switching, integrated circuit design, voltage scaling, digital signal processing chips, circuit optimisation, circuit design, data representation, circuit optimization, glitching, architecture optimization
1	Vamsi Krishna, Abdel Ejnioui, N. Ranganathan	A tree matching chip.	VLSI Design	1996	DBLP DOI BibTeX RDF	tree matching chip, online interpreter systems, linear systolic array algorithms, fixed size linear array, Cadence design tools, parallel algorithms, VLSI, compilers, object recognition, image recognition, systolic arrays, digital signal processing chips, code optimization, 3D object recognition, vision systems, systolic architecture
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Low power realization of FIR filters using multirate architectures.	VLSI Design	1996	DBLP DOI BibTeX RDF	low power realization, multirate architectures, computationally efficient implementations, power dissipation reduction, dedicated ASIC implementation, TMS320C2x/C5x programmable DSP, computational complexity, computational complexity, application specific integrated circuits, power analysis, digital filters, FIR filters, FIR filters, digital signal processing chips
1	D. V. Poornaiah, P. V. Ananda Mohan	A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent dual multiplier-dual adder architecture, video coding applications, high-throughput image coding, carry-save 4:2 compressors, computational complexity, VLSI, VLSI, data compression, video coding, adders, computation time, multiplying circuits, digital signal processing chips
1	S. Ramanathan, V. Visvanathan	A systolic architecture for LMS adaptive filtering with minimal adaptation delay.	VLSI Design	1996	DBLP DOI BibTeX RDF	LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm
1	Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita	Power analysis and low-power scheduling techniques for embedded DSP software.	ISSS	1995	DBLP DOI BibTeX RDF	circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor
1	Rainer Leupers, Peter Marwedel	Time-constrained code compaction for DSPs.	ISSS	1995	DBLP DOI BibTeX RDF	code generation techniques, digital signal processing algorithms, encoding restrictions, exact timing behavior, hard real-time constraints, integer programming model, local code compaction, programmable DSP, rigid heuristics, time-constrained code compaction, real-time systems, timing, integer programming, instruction-level parallelism, source coding, automatic programming, digital signal processing chips, side-effects
1	Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man	Synthesis of pipelined DSP accelerators with dynamic scheduling.	ISSS	1995	DBLP DOI BibTeX RDF	DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules
1	Stan Y. Liao, Srinivas Devadas, Kurt Keutzer	Code density optimization for embedded DSP processors using data compression techniques.	ARVLSI	1995	DBLP DOI BibTeX RDF	code density optimization, embedded DSP processors, code size minimization, text compression algorithms, TMS320C25 code generator, VLSI, data compression, data compression, skeleton, minimisation, dictionary, digital signal processing chips, VLSI systems, production cost
1	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews	High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.	ARVLSI	1995	DBLP DOI BibTeX RDF	counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
1	Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barros, Raúl Jiménez, José L. Huertas	New CMOS VLSI linear self-timed architectures.	ASYNC	1995	DBLP DOI BibTeX RDF	semiconductor storage, CMOS VLSI linear self-timed architectures, digital signal processor circuits, self-timed techniques, synchronous VLSI circuits, FIFO memories, VLSI, asynchronous circuits, asynchronous circuits, digital signal processing chips, CMOS memory circuits, hardware resources
1	Chuck Monahan, Forrest Brewer	Symbolic execution of data paths.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	combinational switching, data-path model, path constraints, bus hazards, register constraints, control encoding limitations, path-constrained model, DSP microprocessor, switching logic, connection constraints, operand constraints, scheduling, Boolean functions, Boolean functions, logic design, combinational circuits, data flow analysis, processor scheduling, symbolic execution, data flow graphs, digital signal processing chips, constraint handling, combinational logic, dataflow graphs, hazards and race conditions, memory elements
1	N. Ranganathan, K. B. Doreswamy	A systolic algorithm and architecture for image thinning.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	image thinning, 4-distance transform, single VLSI chip, 2.59 ms, 0.327 ms, parallel algorithms, image processing, VLSI, parallelism, skeleton, systolic arrays, CMOS, pipeline processing, VLSI architecture, digital signal processing chips, processing elements, CMOS digital integrated circuits, linear time, systolic architecture, systolic algorithm, multiple objects
1	Eddy de Greef, Francky Catthoor, Hugo De Man	Memory organization for video algorithms on programmable signal processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	video algorithms, programmable signal processors, memory-intensive algorithms, compile-time data caching, motion estimation type algorithms, performance, image processing, video, mapping, DSP, imaging, storage management, memory architecture, cache storage, digital signal processing chips, buffer sizes
1	Mark R. Greenstreet	Implementing a STARI chip. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	STARI chip, high-speed signaling technique, MOSIS 2/spl mu/ CMOS process, self-timed FIFO, robust compensation, clock skew, digital signal processing chips, CMOS digital integrated circuits, self-timed circuits, synchronous circuits, 2 micron, timing circuits
1	Bret Stott, Dave Johnson, Venkatesh Akella	Asynchronous 2-D discrete cosine transform core processor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron
1	S. Muller	A new programmable VLSI architecture for histogram and statistics computation in different windows. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	programmable VLSI architecture, histogram computation, grey-scale histogram, image preprocessing methods, inhomogeneous illumination elimination, simple increment operations, histogrammer, window handling, arithmetic unit configuration, memory configuration, equalisation, simulation, image segmentation, VLSI, segmentation, data compression, data compression, statistics, image enhancement, image enhancement, texture analysis, image texture, digital signal processing chips, CMOS technology, binary images, CMOS digital integrated circuits, co-occurrence-matrix, statistics computation
1	Bjørn Olstad, E. Steen, Arne Halaas	Image filtering techniques and VLSI architectures for efficient data extraction in shell rendering. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	image filtering techniques, shell rendering, interactive data reduction, real-time data reduction, PCI based search engine, full custom VLSI chip, opacity assignment, multi-spectral voxel data, interactive inspection procedures, 3D imagery, 3D ultrasonics, 3D MRI studies, classification, VLSI, feature extraction, volume rendering, image classification, application specific integrated circuits, medical image processing, search problems, VLSI architectures, filtering theory, data reduction, digital signal processing chips, data extraction, rendering (computer graphics), biomedical NMR, image preprocessing, biomedical ultrasonics
1	Gerald G. Pechanek, M. Stojancic, Stamatis Vassiliadis, C. John Glossner	MFAST: a single chip highly parallel image processing architecture. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	MFAST, single chip highly parallel image processing architecture, IBM Mwave, graphics processing, scalable array of processing elements, folded array, transpose operations, Mwave Folded Array Signal Transform processor, scalable DSP, algorithm execution, 2D DCT program, functional simulator models, 16 bit/s, 50 MHz, real-time systems, parallel architectures, VHDL, discrete cosine transforms, discrete cosine transform, hardware description languages, video signal processing, digital signal processing chips, matrix operations, real-time video processing
1	Miodrag Potkonjak	Discrete-relaxation-based heuristic techniques for video algorithm/architecture matching and system level transformations. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	discrete-relaxation-based heuristic techniques, video algorithm, system level transformations, computational transformations, throughput performance, iterative heuristic approach, behavioral transformations, rephasing, architecture matching, computational complexity, image processing, VLSI, pipelining, iterative methods, pipeline processing, retiming, integrated circuit design, system level design, video processing, video signal processing, heuristic programming, digital signal processing chips, circuit optimisation, throughput optimization
1	Miodrag Potkonjak, Anantha Chandrakasan	Synthesis and selection of DCT algorithms using behavioral synthesis-based algorithm space exploration. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	DCT algorithms, behavioral synthesis-based algorithm space exploration, high level synthesis tools, behavioral design space, IC implementation, image processing, image processing, high level synthesis, discrete cosine transforms, discrete cosine transform, application specific integrated circuits, circuit layout CAD, video processing, fast algorithms, video signal processing, digital signal processing chips, design space
1	An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-Chieh Liu	Parallel programmable video co-processor design. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	quadrature mirror filters, parallel programmable video co-processor design, computationally intensive data processing, very high data rate, subband filtering, discrete orthogonal transforms, computational speed, multirate FIR/IIR/DT operations, low-power implementation, QMF, parallel architectures, transforms, high-performance, adaptive filters, adaptive filtering, FIR filters, FIR filtering, video signal processing, digital signal processing chips, low-cost, IIR filters, IIR filtering, hardware overhead, video applications, processing speed
1	Varsha Kamat, Subramaniam Ganesan	An efficient implementation of the Hough transform for detecting vehicle license plates using DSP'S. (PDF / PS)	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	vehicle license plate detection, road scenes, image processing technique, license plate shape, real vehicle, algorithm, tracking, edge detection, Hough transforms, Hough transform, orientations, digital signal processing chips, digital signal processors, vehicle tracking, line detection, road vehicles, CCD camera
1	Mario Kovac, N. Ranganathan	JAGUAR: a high speed VLSI chip for JPEG image compression standard.	VLSI Design	1995	DBLP DOI BibTeX RDF	JAGUAR, high speed VLSI chip, JPEG image compression standard, pipelined single chip VLSI architecture, entropy encoder, clock rate, input rate, CMOS VLSI chip, Huffman entropy coding, 1024 pixel, 1048576 pixel, VLSI, parallel architectures, data compression, image coding, discrete cosine transforms, discrete cosine transform, pipeline processing, color images, image colour analysis, digital signal processing chips, Huffman codes, high throughput, CMOS digital integrated circuits, entropy codes, 100 MHz
1	S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta	A single chip, pipelined, cascadable, multichannel, signal processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	delay lines, single chip signal processor, cascadable processor, multichannel signal processor, programmable delay line, memory mapped peripheral, online diagnostics, shadow accumulators, double metal CMOS process, 144 pin CPGA, VLSI, timing, pipeline processing, digital signal processing chips, pipelined processor, CMOS digital integrated circuits, array multipliers, DSP architecture, 2 micron
1	Hossein Sahabi, Anup Basu, Mark Fiala	VLSI implementation of variable resolution image compression.	VLSI Design	1995	DBLP DOI BibTeX RDF	variable resolution image compression, bandwith requirements, telepresence system, teleconferencing systems, encoding/decoding subsystem, SBus interface, VLSI codec chip, real time compression, real time decompression, video rates, output image quality, 1024 pixel, 1048576 pixel, real-time systems, VLSI, data compression, image coding, teleconferencing, image resolution, video signal processing, digital signal processing chips, VLSI implementation, codecs, video codecs
1	Richard I. Hartley, Kenneth Welles II, Michael Hartman, Abhijit Chatterjee, Paul Delano, Barbara Molnar, Colin Rafferty	A Rapid-Prototyping Environment for Digital-Signal Processors.	IEEE Design & Test of Computers	1991	DBLP DOI BibTeX RDF
1	Robert Michael Owens, Mary Jane Irwin	Being Stingy with Multipliers.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	VLSI signal processor, signal processing architectures, signal processing equipment, VLSI, interconnect, adders, multipliers, digital signal processing chips
1	A. L. Narasimha Reddy, Prithviraj Banerjee	Algorithms-Based Fault Detection for Signal Processing Applications.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	algorithm based fault detection, FFT factorization, correctness checking, signal processing applications, special-purpose array processors, functional-level concurrent error-detection, VLSI signal processing architectures, finite-precision arithmetic, error coverage, VLSI, fault tolerant computing, integrated circuit testing, error detection, digital signal processing chips, QR factorization, roundoff errors, truncation errors
1	Chien-Chun Su, Hao-Yung Lo	An Algorithm for Scaling and Single Residue Error Correction in Residue Number Systems.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	single residue digit error correction, mixed radix conversion, redundant digits, scaling error, error-correction circuit with scaling, fault tolerant computing, digital signal processing, digital arithmetic, error correction, residue number systems, RNS, fault-tolerant systems, digital signal processing chips, number theory, lookup table
1	Allan L. Fisher, Peter T. Highnam	Computing the Hough Transform on a Scan Line Array Processor (Image Processing).	IEEE Trans. Pattern Anal. Mach. Intell.	1989	DBLP DOI BibTeX RDF	scan line array processor, parallel algorithm, parallel algorithms, image processing, transforms, computerised picture processing, computerised picture processing, SIMD, Hough transform, digital signal processing chips, linear arrays, vector processing
1	Frank Yeong-Chyang Shih, Owen Robert Mitchell	Threshold Decomposition of Gray-Scale Morphology into Binary Morphology.	IEEE Trans. Pattern Anal. Mach. Intell.	1989	DBLP DOI BibTeX RDF	gray-scale morphology, binary morphology, multiple binary signals, threshold decomposition architecture, parallel processing, VLSI, VLSI, parallel architectures, computerised picture processing, computerised picture processing, stacking, digital signal processing chips, logic gates