Search results for "divider"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Stephan Henzler, Siegmar Koeppe	High-speed low-power frequency divider with intrinsic phase rotator.	ISLPED	2006	DBLP DOI BibTeX RDF	phase-rotator, pre-scaler, low-power, divider
3	Jean-Olivier Plouchart, Jonghae Kim, Hector Recoules, Noah Zamdmer, Yue Tan, Melanie Sherony, Asit Ray, Lawrence F. Wagner	A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology.	ISLPED	2003	DBLP DOI BibTeX RDF	RF circuit, SOI CMOS, frequency divider, low power, CML
3	Suchitav Khadanga	Synchronous programmable divider design for PLL Using 0.18 um cmos technology.	IWSOC	2003	DBLP DOI BibTeX RDF	programmable divider, CMOS integrated circuits, phase locked loop, PLL, Prescaler, frequency synthesizers
3	Chanyutt Arjhan, Raghvendra G. Deshmukh	A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	parallel divider, parallel-array divider, pf-model, summand-generator, summand-counter, multiple faults functional testing, design for testability, boundary scan, array multiplier, Parallel multiplier
2	Zhaofeng He, Junshuang Ma, Ming Yang	Design of Automatic Multiple Musical Performance Circuit System Based on Numerical Control Frequency Divider.	MVHI	2010	DBLP DOI BibTeX RDF	frequency divider, VHDL, musical performance
2	Hongli Tian, Shuo Shi, Jun Zhang, Hongdong Zhao	Controllable Arbitrary Integer Frequency Divider Based on VHDL.	JCAI	2009	DBLP DOI BibTeX RDF	50% duty cycle, frequency divider, FPGA, VHDL, CPLD
2	Alireza Saberkari, Shahriar B. Shokouhi, Azadeh Kiani, Fereshteh Poorahangaryan	A novel low power static frequency divider based on the GDI technique.	CCECE	2009	DBLP DOI BibTeX RDF
2	Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li	A novel VLSI iterative divider architecture for fast quotient generation.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Melina Apostolidou, Peter G. M. Baltus, Cicero S. Vaucher	Phase noise in frequency divider circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt	High speed digital CMOS divide-by-N fequency divider.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Vítor Silva, Rui Duarte, Mário P. Véstias, Horácio C. Neto	Multiplier-based double precision floating point divider according to the IEEE-754 standard.	ARC	2008	DBLP DOI BibTeX RDF
2	K. Scott Hemmert, Keith D. Underwood	Floating-Point Divider Design for FPGAs.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Liang-Kai Wang, Michael J. Schulte	A Decimal Floating-Point Divider Using Newton-Raphson Iteration.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	Newton-Raphson iteration, initial approximation, computer arithmetic, floating-point, division, hardware design, decimal
2	Liang Wang, Suge Yue, Yuanfu Zhao, Long Fan	An SEU-Tolerant Programmable Frequency Divider.	ISQED	2007	DBLP DOI BibTeX RDF
2	Jian-Hong Fang, Norman M. Filiol, Tom A. D. Riley, Miles A. Copeland	A Second Order Delta-Sigma Frequency Discriminator with Fractional-N Divider and Multi-Bit Quantizer.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Kuo-Hsing Cheng, Cheng-Liang Hung, Chia-Wei Su	A Sub-1V Low-Power High-Speed Static Frequency Divider.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Muhammad Usama, Tad A. Kwasniewski	A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	A radix-10 SRT divider based on alternative BCD codings.	ICCD	2007	DBLP DOI BibTeX RDF
2	Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo	A New Phase Noise Model for TSPC based divider.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
2	Sandeep B. Singh, Jayanta Biswas, S. K. Nandy	A Cost Effective Pipelined Divider for Double Precision Floating Point Number.	ASAP	2006	DBLP DOI BibTeX RDF
2	Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski	A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider.	CCECE	2006	DBLP DOI BibTeX RDF
2	Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel	A New Self-Checking and Code-Disjoint Non-Restoring Array Divider.	IOLTS	2006	DBLP DOI BibTeX RDF
2	X. P. Yu, Manh Anh Do, Lin Jia, Jianguo Ma, Kiat Seng Yeo	Design of a low power wide-band high resolution programmable frequency divider.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Xinyu Guo, Carl Sechen	High Speed Redundant Adder and Divider in Output Prediction Logic.	ISVLSI	2005	DBLP DOI BibTeX RDF
2	Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije	A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer.	SBCCI	2005	DBLP DOI BibTeX RDF	high speed digital circuit, low power, prescaler, frequency synthesizer
2	Maria J. Avedillo, José M. Quintana, José L. Huertas	Robust frequency divider based on resonant tunneling devices.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Mika Nyström, Elaine Ou, Alain J. Martin	An Eight-Bit Divider Implemented in Asynchronous Pulse Logic.	ASYNC	2004	DBLP DOI BibTeX RDF
2	Woo-Chan Park, Tack-Don Han, Sung-Bong Yang	A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
2	Amin Q. Safarian, Payam Heydari	Design and analysis of a distributed regenerative frequency divider using distributed mixer.	ISCAS	2004	DBLP DOI BibTeX RDF
2	Gang Li, Brent Maundy	A novel four quadrant CMOS analog multiplier/divider.	ISCAS	2004	DBLP DOI BibTeX RDF
2	Jen-Shiun Chiang, Min-Shiou Tsai	A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	floating-point division, new Svoboda-Tung division, radix-4, Svoboda-Tung division, computer arithmetic, prescaling, signed digit number system
2	U. Yodprasit, Christian C. Enz	Nonlinear analysis of a Colpitts injection-locked frequency divider.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Khanittha Kaewdang, Chalermpan Fongsamut, Wanlop Surakampontorn	A wide-band current-mode OTA-based analog multiplier-divider.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Junhyung Um, Sangwoo Lee, Youngsoo Park, Sungik Jun, Thewhan KimU	An efficient inverse multiplier/divider architecture for cryptography systems.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Sanya Amnartpluk, Chuwong Phongcharoenpanich, Sompol Kosulvit, Monai Krairiksh	A power divider using linear electric probes coupling inside conducting cylindrical cavity.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Zhenhua Wang	A virtually jitter-free fractional-N divider for a Bluetooth radio.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Anders Berkeman, Viktor Öwall	A configurable divider using digit recurrence.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Guenter Gerwig, Holger Wetter, Eric M. Schwarz, Juergen Haess	High Performance Floating-Point Unit with 116 Bit Wide Divider.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
2	G. Ritzberger, J. Böck, H. Knapp, L. Treitinger, Arpad L. Scholtz	38 GHz low-power static frequency divider in SiGe bipolar technology.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Jing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun	A Totally Self-Checking Dynamic Asynchronous Datapath.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	Totally self-checking asynchronous datapath, differential cascade voltage switch logic, divider
2	S. M. Aziz, S. J. Carr	On C-Testability of Carry Free Dividers.	DELTA	2002	DBLP DOI BibTeX RDF	Carry-free, C-Testability, Divider, Radix-2
2	Roope Kaivola, Mark Aagaard	Divider Circuit Verification with Model Checking and Theorem Proving.	TPHOLs	2000	DBLP DOI BibTeX RDF
2	Alberto Nannarelli, Tomás Lang	Low-Power Divider.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Floating-point division, low-power, digit-recurrence division
2	Antonio J. López-Martín, Alfonso Carlosena	Geometric-mean based current-mode CMOS multiplier/divider.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Spiridon Vlassis, Stilianos Siskos	Analog CMOS four-quadrant multiplier and divider.	ISCAS	1999	DBLP DOI BibTeX RDF
2	C.-C. Wang, C. J. Huang, G.-C. Lin	A chip design of radix-4/2 64b/32b signed and unsigned integer divider using Compass cell library.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Y. Sumi, S. Obote, N. Kitai, R. Furuhashi, Y. Matsuda, Yutaka Fukui	PLL frequency synthesizer with an auxiliary programmable divider.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Naofumi Takagi, Takashi Horiyama	A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	on-the-fly conversion, adder, Arithmetic circuit, divider
2	Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet	Verifying a Self-Timed Divider.	ASYNC	1998	DBLP DOI BibTeX RDF	model checking, refinement, asynchronous, hardware verification, timing verification, self-timed, speed-independence
2	Jean-Paul Theis, Harald Schlimper	Ultrafast compact CMOS dividers. (PDF / PS)	ICPADS	1997	DBLP DOI BibTeX RDF	CMOS dividers, ultrafast, restoring division, floating-point division, 0.3 mum, parallelization, timing, layout, compact, dividing circuits, divider circuits
2	KiJong Lee, Kiyoung Choi	Self-timed divider based on RSD number system.	IEEE Trans. VLSI Syst.	1996	DBLP DOI BibTeX RDF
2	Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi	A C-testable carry-free divider.	IEEE Trans. VLSI Syst.	1994	DBLP DOI BibTeX RDF
2	D. Eisig, J. Rotstain, I. Koren	The design of a 64-bit integer multiplier/divider unit.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
1	Yong-Hwan Lee, Young-Sung Cho, Sangook Moon	Design of a high precision logarithmic converter in a binary floating point divider.	Concurrency and Computation: Practice and Experience	2012	DBLP DOI BibTeX RDF
1	Lo'ai Ali Tawalbeh, Yaser Jararweh, Abidalrahman Mohammad	An integrated radix-4 modular divider/multiplier hardware architecture for cryptographic applications.	Int. Arab J. Inf. Technol.	2012	DBLP BibTeX RDF
1	Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo	A Low-Power Single-Phase Clock Multiband Flexible Divider.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Jing Jin, Xiaoming Liu, Tingting Mo, Jianjun Zhou	Quantization Noise Suppression in Fractional-$N$ PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider.	IEEE Trans. on Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Kailash Chandrashekar, Stefano Pellerano, Paolo Madoglio, Ashoke Ravi, Yorgos Palaskas	A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Robab Kazemi, Aly E. Fathy, R. Ali Sadeghzadeh	Ultra-wide band vivaldi antenna array using low loss SIW power divider and GCPW wide band transition.	RWS	2012	DBLP DOI BibTeX RDF
1	Haiyan Jin, Xianzhi Du, Fulin Xiao, Guangjun Wen	A Novel Wideband Spatial Power Combining Amplifier Based on Turnstile-Junction Waveguide Divider/Combiner.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda	A 60-GHz Injection-Locked Frequency Divider Using Multi-Order LC Oscillator Topology for Wide Locking Range.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Young-Pyo Hong, Jong-Gwan Yook	Varactor-Tuned Radial Power Divider with SIW Technology.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Jian Gu, Yong Fan, Haiyan Jin	A Novel 3D Power Divider Based on Half-Mode Substrate Integrated Circular Cavity.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Xin Liu, Cuiping Yu, Yuanan Liu, Shulan Li, Fan Wu, Yongle Wu	A Novel Dual-Band Bagley Polygon Power Divider with 2-D Configuration.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Sheng-Lyang Jang, Li-Te Chou, Jhin-Fang Huang, Chia-Wei Chang	A Dual-Band Dual-Resonance Quadrature Injection-Locked Frequency Divider.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Sheng-Lyang Jang, Chia-Wei Chang, Yu-Sheng Chen, Jhin-Fang Huang, Jau-Wei Hsieh, Chong-Wei Huang	A 0.18 µm CMOS Wide-Band Injection-Locked Frequency Divider Using Push-Push Oscillator.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Ugo Decanis, Andrea Ghilioni, Enrico Monaco, Andrea Mazzanti, Francesco Svelto	A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita	A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Jae Kap Jung, Eddy So, Sang-Hwa Lee, David Bennett	Comparison of Systems Between KRISS and NRC to Evaluate the Performance Characteristics of A 400-kV Capacitive Voltage Divider.	IEEE T. Instrumentation and Measurement	2011	DBLP DOI BibTeX RDF
1	Yi Liu, Fuchang Lin, Guan Hu, Miao Zhang	Design and Performance of a Resistive-Divider System for Measuring Fast HV Impulse.	IEEE T. Instrumentation and Measurement	2011	DBLP DOI BibTeX RDF
1	Joonhee Lee, Sunghyun Park, SeongHwan Cho	A 470-µW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	F. Javier López-Martínez, Eduardo del Castillo-Sánchez, José T. Entrambasaguas, Eduardo Martos-Naya	Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput.	Signal Processing Systems	2011	DBLP DOI BibTeX RDF
1	Chi-Sheng Lin, Ting-Hsu Chien, Chin-Long Wey	A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Saeid Daneshgar, Oscar De Feo, Michael Peter Kennedy	Observations Concerning the Locking Range in a Complementary Differential LC Injection-Locked Frequency Divider - Part II: Design Methodology.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Yuen-Haw Chang	Variable-Conversion-Ratio Switched-Capacitor-Voltage-Multiplier/Divider DC-DC Converter.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Davide Tasca, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita	Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Michael Peter Kennedy, Xi Dong, Hongjia Mo	Phenomenological study of an injection-locked CMOS LC frequency divider with direct injection.	ECCTD	2011	DBLP DOI BibTeX RDF
1	Andreas Axholt, Henrik Sjöland	A 2.25mW inductor-less 24 GHz CML frequency divider in 90nm CMOS.	ECCTD	2011	DBLP DOI BibTeX RDF
1	Zbynek Fedra, Jaromir Kolouch	VHDL procedure for combinational divider.	TSP	2011	DBLP DOI BibTeX RDF
1	Andrea Ghilioni, Ugo Decanis, Enrico Monaco, Andrea Mazzanti, Francesco Svelto	A 6.5mW inductorless CMOS frequency divider-by-4 operating up to 70GHz.	ISSCC	2011	DBLP DOI BibTeX RDF
1	Karthik Mahesh Varadarajan	Efficient Serial Floating-point Constant Divider Structure of the Form 2P±1.	PECCS	2011	DBLP BibTeX RDF
1	D. Hammou, Emilia Moldovan, Serioja Ovidiu Tatu	Novel MHMIC millimeter wave power divider/combiner.	CCECE	2011	DBLP DOI BibTeX RDF
1	Bong-Ki Jang, Young-soon Lee	A Study on the Power Divider of the Microstrip Antenna for Identification Friend or Foe Radar.	FGIT	2011	DBLP DOI BibTeX RDF
1	Xiaoming Liu, Jing Jin, Xi Li, Jianjun Zhou	Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Carlo Samori, Marco Zanuso, Salvatore Levantino, Andrea L. Lacaita	Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Hongrui Wang, Dajie Zeng, Dongxu Yang, Li Zhang, Lei Zhang, Yan Wang, He Qian, Zhiping Yu	Understanding dynamic behavior of mm-wave CML divider with injection-locking concept.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Haipeng Fu, Deyun Cai, Junyan Ren, Wei Li	A harmonic-suppressed regenerative divide-by-5 frequency divider for UWB applications.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Tomislav Markovic, Raul Blecic, Adrijan Baric	Quadrature coupler and power divider circuit-EM co-simulation.	MIPRO	2011	DBLP BibTeX RDF
1	Somaye Asadian, Mohammad Jafar Hemmati, Sasan Naseh	A low power 9GHz divide-by-3 injection locked frequency divider in 0.18μm CMOS with 15% locking range.	ICECS	2011	DBLP DOI BibTeX RDF
1	Masoud Rezaei, Hassan Sepehrian, Sasan Naseh	A new scheme of coupling VCOs for the purpose of injection locking frequency divider.	ICECS	2011	DBLP DOI BibTeX RDF
1	Kazuhisa Yamauchi, Akira Inoue, Moriyasu Miyazaki	High Directivity Coupler Suppressing Leak Coupling with Cancellation Circuit of Wilkinson Divider.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Yihong Zhou, Jiayin Li, Haiyan Jin, Haiyang Wang	Compact Four-Way Ka-Band Power Divider/Combiner Based on Finline.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Seungwoo Seo, Jae-Sung Rieh	A Low Power V-Band Injection-Locked Frequency Divider in 0.13-µm Si RFCMOS Technology.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Yihong Zhou, Jiayin Li, Haiyang Wang, Haiyan Jin	A Novel Traveling Wave Power Divider/Combiner Based on Finline.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Shoichi Hara, Kenichi Okada, Akira Matsuzawa	A Wide-Tunable LC-Based Voltage-Controlled Oscillator Using a Divide-by-N Injection-Locked Frequency Divider.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Sheng-Lyang Jang, Cheng-Chen Liu, Jhin-Fang Huang	Divide-by-3 Injection-Locked Frequency Divider Using Two Linear Mixers.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Morihiko Nanjo, Kunio Sakakibara, Nobuyoshi Kikuma, Hiroshi Hirayama	Control of Power Dividing Ratio in Four-Way Power Divider for Feeding Microstrip Comb-Line Antenna.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Yihong Zhou, Jiayin Li, Haiyan Jin, Haiyang Wang	Compact Eight-Way Ka-Band Power Divider/Combiner Based on Double-Layer Finline.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Matt D'Amore, Cedric Monier, Steven Taiyu Lin, Bert Oyama, Dennis W. Scott, Eric N. Kaneshiro, Ping-Chih Chang, Kenneth F. Sato, Alex Niemi, Linh Dang, Abdullah Cavus, Augusto Gutierrez-Aitken, Aaron K. Oki	A 0.25 μ m InP DHBT 200 GHz+ Static Frequency Divider.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Jun Deguchi, Daisuke Miyashita, Yosuke Ogasawara, Gaku Takemura, Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi, Nobuyuki Itoh, Mototsugu Hamada	A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF