Search results for "dual VDD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Yu Hu, King Ho Tam, Tong Jing, Lei He	Fast dual-vdd buffering based on interconnect prediction and sampling.	SLIP	2007	DBLP DOI BibTeX RDF	routing, low power, interconnect, buffer insertion, dual-Vdd
3	Harmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka	A dual-VDD boosted pulsed bus technique for low power and low leakage operation.	ISLPED	2006	DBLP DOI BibTeX RDF	pulsed bus, leakage, repeaters, Dual-VDD
3	Himanshu Kaul, Dennis Sylvester	A novel buffer circuit for energy efficient signaling in dual-VDD systems.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	on-chip signaling, low-power, repeaters, dual-VDD
3	Fei Li, Yan Lin, Lei He	FPGA power reduction using configurable dual-Vdd.	DAC	2004	DBLP DOI BibTeX RDF	FPGA, low power, configurable, power efficient, dual-Vdd
3	Fei Li, Yan Lin, Lei He, Jason Cong	Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, low power, power efficient, dual-Vdd, dual-Vt
2	Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini	Automatic synthesis of near-threshold circuits with fine-grained performance tunability.	ISLPED	2010	DBLP DOI BibTeX RDF	near threshold, sub-threshold performance, variability compensation, low power, ultra low power, dual VDD, sub-threshold
2	Stephen Bijansky, Sae Kyu Lee, Adnan Aziz	TuneLogic: Post-silicon tuning of dual-Vdd designs.	ISQED	2009	DBLP DOI BibTeX RDF
2	Xiaoming Chen, Yu Wang 0002, Yu Cao, Yuchun Ma, Huazhong Yang	Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd
2	Yu Hu, Yan Lin, Lei He, Tim Tuan	Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	FPGA, Low power, retiming
2	Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal	A high-level clustering algorithm targeting dual Vdd FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	clustering, field programmable gate arrays, partitioning, placement, voltage scaling, Dynamic power
2	Saihua Lin, Huazhong Yang, Rong Luo	A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Bruce Tseng, Hung-Ming Chen	Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations.	ISPD	2008	DBLP DOI BibTeX RDF	voltage island architecture, low power, buffer insertion
2	Stephen Bijansky, Adnan Aziz	TuneFPGA: post-silicon tuning of dual-Vdd FPGAs.	DAC	2008	DBLP DOI BibTeX RDF	FPGA, delay, process variation, yield, tuning
2	Yan Lin, Lei He	Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction.	DATE	2007	DBLP DOI BibTeX RDF
2	Sherif A. Tawfik, Volkan Kursun	Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution.	ISLPED	2007	DBLP DOI BibTeX RDF	dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD
2	Yan Lin, Lei He	Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Yu Hu, Yan Lin, Lei He, Tim Tuan	Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.	DAC	2006	DBLP DOI BibTeX RDF	FPGA, low power, retiming
2	Bin Liu 0007, Yici Cai, Qiang Zhou, Xianlong Hong	Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Sarvesh H. Kulkarni, Dennis Sylvester	Power distribution techniques for dual VDD circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Aswath Oruganti, Nagarajan Ranganathan	Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation.	VLSI Design	2006	DBLP DOI BibTeX RDF
2	Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu	Design of STR level converters for SoCs using the multi-island dual-VDD design technique.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Mihir R. Choudhury, Quming Zhou, Kartik Mohanram	Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques.	ICCAD	2006	DBLP DOI BibTeX RDF
2	King Ho Tam, Lei He	Power optimal dual-Vdd buffered tree considering buffer stations and blockages.	DAC	2005	DBLP DOI BibTeX RDF	low power, buffer insertion, detail routing
2	Yan Lin, Lei He	Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction.	DAC	2005	DBLP DOI BibTeX RDF	programmable-Vdd, time slack, FPGA, low power
2	Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan	A Dual-VDD Low Power FPGA Architecture.	FPL	2004	DBLP DOI BibTeX RDF
2	Sarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester	A new algorithm for improved VDD assignment in low power dual VDD systems.	ISLPED	2004	DBLP DOI BibTeX RDF	ECVS, dual VDD design, low power design algorithms, CVS, level converters
2	Ashish Srivastava, Dennis Sylvester, David Blaauw	Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment.	DAC	2004	DBLP DOI BibTeX RDF	optimization, power dissipation, multiple voltages
1	Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin	HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan	A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
1	Qing Gao, Orly Yadid-Pecht	Dual VDD block based CMOS image sensor - preliminary evaluation.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Kazuei Hironaka, Hideharu Amano	Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Joseph F. Ryan, Benton H. Calhoun	A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS.	CICC	2010	DBLP DOI BibTeX RDF
1	Prasanth Mangalagiri, Vijaykrishnan Narayanan	Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs.	ISVLSI	2009	DBLP DOI BibTeX RDF
1	Thomas Schweizer, Julio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel	Low Energy Voltage Dithering in Dual VDD Circuits.	PATMOS	2009	DBLP DOI BibTeX RDF
1	Insup Shin, Seungwhun Paik, Youngsoo Shin	Register allocation for high-level synthesis using dual supply voltages.	DAC	2009	DBLP DOI BibTeX RDF	low power, high-level synthesis, register allocation, dual supply voltage
1	Kiyoo Itoh	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
1	Prateek Mishra, Anish Muttreja, Niraj K. Jha	Low-power FinFET circuit synthesis using multiple supply and threshold voltages.	JETC	2009	DBLP DOI BibTeX RDF	Low-power, linear programming, synthesis, TCMS
1	King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang	Dual-Vdd Buffer Insertion for Power Reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Behnam Ghavami, Mehrshad Khosraviani, Hossein Pedram	Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing.	DSD	2008	DBLP DOI BibTeX RDF
1	Anish Muttreja, Prateek Mishra, Niraj K. Jha	Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto	Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Yici Cai, Bin Liu 0007, Qiang Zhou, Xianlong Hong	Voltage Island Generation in Cell Based Dual-Vdd Design.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong	Logic and Layout Aware Voltage Island Generation for Low Power Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Sherif A. Tawfik, Volkan Kursun	Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Sherif A. Tawfik, Volkan Kursun	Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew.	ISQED	2007	DBLP DOI BibTeX RDF
1	Fei Li, Yan Lin, Lei He	Field Programmability of Supply Voltages for FPGA Power Reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Sarvesh H. Kulkarni, Dennis Sylvester	Power Distribution Techniques for Dual VDD Circuits.	J. Low Power Electronics	2006	DBLP DOI BibTeX RDF
1	Yan Lin, Yu Hu, Lei He, Vijay Raghunat	An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction.	ISLPED	2006	DBLP DOI BibTeX RDF	time slack, FPGA, low power
1	Somsubhra Mondal, Seda Ogrenci Memik	Power Optimization Techniques for SRAM-Based FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
1	Rajarshi Mukherjee, Seda Ogrenci Memik	Evaluation of dual VDD fabrics for low power FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Yan Lin, Fei Li, Lei He	Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA power model, Vdd programmability, low power, FPGA architecture, dual-Vdd
1	Deming Chen, Jason Cong, Junjuan Xu	Optimal module and voltage assignment for low-power.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Yu Ching Chang, King Ho Tam, Lei He	Power-optimal repeater insertion considering Vdd and Vth as design freedoms.	ISLPED	2005	DBLP DOI BibTeX RDF	low power, buffer insertion
1	Sarvesh H. Kulkarni, Dennis Sylvester	High performance level conversion for dual VDD design.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Low-power dual Vth pseudo dual Vdd domino circuits.	SBCCI	2004	DBLP DOI BibTeX RDF	NMOS pull-up, low power, domino logic, dual supply voltages, dual threshold voltages
1	Deming Chen, Jason Cong, Fei Li, Lei He	Low-power technology mapping for FPGA architectures with dual supply voltages.	FPGA	2004	DBLP DOI BibTeX RDF	low-power FPGA, technology mapping, dual supply voltage
1	Deming Chen, Jason Cong	Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.	ISLPED	2004	DBLP DOI BibTeX RDF	circuit clustering, low-power FPGA, dual supply voltage