Search results for "dual supply voltage"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada	A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.	PATMOS	2004	DBLP DOI BibTeX RDF
2	Nestoras Tzartzanis, William W. Walker	A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File.	ICCD	2003	DBLP DOI BibTeX RDF
2	Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic	Level conversion for dual-supply systems.	ISLPED	2003	DBLP DOI BibTeX RDF	level conversion, flip-flop, dual-supply voltage
2	David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer	Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization.	ISLPED	2003	DBLP DOI BibTeX RDF	dual threshold, sizing, dual supply voltage, simultaneous
2	Torsten Mahnke, Walter Stechele, Wolfgang Hoeld	Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment.	PATMOS	2002	DBLP DOI BibTeX RDF
2	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Low-swing clock domino logic incorporating dual supply and dual threshold voltages.	DAC	2002	DBLP DOI BibTeX RDF	low swing clock, low power, domino logic, dual supply voltage, dual threshold voltage
1	Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai	24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits.	ISQED	2012	DBLP DOI BibTeX RDF
1	Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai	12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Insup Shin, Seungwhun Paik, Youngsoo Shin	Register allocation for high-level synthesis using dual supply voltages.	DAC	2009	DBLP DOI BibTeX RDF	low power, high-level synthesis, register allocation, dual supply voltage
1	Sherif A. Tawfik, Volkan Kursun	Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Sherif A. Tawfik, Volkan Kursun	Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew.	ISQED	2007	DBLP DOI BibTeX RDF
1	Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh	Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling.	HiPEAC	2007	DBLP DOI BibTeX RDF
1	Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama	Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	K. Sadeghi, M. Emadi, F. Farbiz	Using Level Restoring Method for Dual Supply Voltage.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Pseudo Dual Supply Voltage Domino Logic Design.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
1	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Kun-Lin Tsai, Szu-Wei Chaung, Feipei Lai, Shanq-Jang Ruan	A low power scheduling method using dual V/sub dd/ and dual V/sub th/.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Deming Chen, Jason Cong, Fei Li, Lei He	Low-power technology mapping for FPGA architectures with dual supply voltages.	FPGA	2004	DBLP DOI BibTeX RDF	low-power FPGA, technology mapping, dual supply voltage
1	Deming Chen, Jason Cong	Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.	ISLPED	2004	DBLP DOI BibTeX RDF	circuit clustering, low-power FPGA, dual supply voltage
1	Weisheng Chong, Masanori Hariyama, Michitaka Kameyama	Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits.	ISVLSI	2004	DBLP DOI BibTeX RDF
1	Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman	Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Tim Schoenauer, Jörg Berthold, Christoph Heer	Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Thomas Olsson, Pontus Åström, Peter Nilsson	Dual supply-voltage scaling for reconfigurable SoC's.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Chien-Cheng Yu, Wei-Ping Wang, Bin-Da Liu	A new level converter for low-power applications.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Jun-Fu Shen, Liang-Gee Chen, Hao-Chieh Chang, Tu-Chih Wang	Low power full-search block-matching motion estimation chip for H.263+.	ISCAS	1999	DBLP DOI BibTeX RDF