Search results for "dynamic frequency clocking"

Found 12 publication records. Showing 12 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar	A VLSI array architecture with dynamic frequency clocking. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	VLSI array architecture, dynamic frequency clocking, linear VLSI array processor, DFLAP, power requirements, image processing, VLSI, throughput
2	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	ILP models for simultaneous energy and transient power minimization during behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	average power, cycle difference power, datapath scheduling, dynamic frequency clocking, multicycling, multiple supply voltages, peak power differential, Peak power
2	Saraju P. Mohanty, N. Ranganathan	Energy-efficient datapath scheduling using multiple voltages and dynamic clocking.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	dynamic frequency clocking, low-power datapath synthesis, multiple voltage scheduling, time-constrained scheduling, High-level synthesis, resource-constrained scheduling
2	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Simultaneous peak and average power minimization during datapath scheduling for DSP processors.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	average power, datapath scheduling, dynamic frequency clocking, high-level synthesis, peak power, multiple voltages
2	Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna	Datapath Scheduling using Dynamic Frequency Clocking.	ISVLSI	2002	DBLP DOI BibTeX RDF
2	Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan	Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi	ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Nagarajan Ranganathan	A framework for energy and transient power reduction during behavioral synthesis.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling.	ICCD	2003	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	An ILP-based scheduling scheme for energy efficient high performance datapath synthesis.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Peak Power Minimization Through Datapath Scheduling.	ISVLSI	2003	DBLP DOI BibTeX RDF
1	Nagarajan Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar	A linear array processor with dynamic frequency clocking for image processing applications.	IEEE Trans. Circuits Syst. Video Techn.	1998	DBLP DOI BibTeX RDF