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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 15 occurrences of 14 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 3 | Thomas William Ainsworth, Timothy Mark Pinkston |
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus.  |
NOCS  |
2007 |
DBLP DOI BibTeX RDF |
Element Interconnect Bus, heterogeneous multicore, network characterization, interconnection networks, network-on-chip, Cell Broadband Engine, on-chip network, performance bottleneck |
| 2 | Daniel Jiménez-González, Xavier Martorell, Alex Ramírez |
Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications.  |
ISPASS  |
2007 |
DBLP DOI BibTeX RDF |
arithmetic performance analysis, memory bandwidth application, synergistic processor element, DMA controller, direct memory access, element interconnect bus, bandwidth performance peak, processor component, message passing interface, data stream, single instruction multiple data, cell broadband engine, streaming programming model, processor speed |
| 1 | C. Devi Sudheer, T. Nagaraju, Pallav K. Baruah, Ashok Srinivasan |
Optimizing assignment of threads to SPEs on the cell BE processor.  |
IPDPS  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Pieter Bellens, Josep M. Pérez, Rosa M. Badia, Jesús Labarta |
Exploiting Locality on the Cell/B.E. through Bypassing.  |
SAMOS  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | William Lundgren |
Gedae's automated management of hierarchical memories on multicore processors Commercial Tutorial.  |
IPDPS  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Meilian Xu, Parimala Thulasiraman |
Finite-difference time-domain on the cell/B.E. processor.  |
IPDPS  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Thomas William Ainsworth, Timothy Mark Pinkston |
Characterizing the Cell EIB On-Chip Network.  |
IEEE Micro  |
2007 |
DBLP DOI BibTeX RDF |
multiple data stream architectures, multiprocessors, multicore architectures, interconnection architectures, on-chip interconnection networks |
Displaying result #1 - #7 of 7 (100 per page; Change: )
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