Search results for "exhaustive simulation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Radu Mateescu, Sylvain Rampacek	Formal Modeling and Discrete-Time Analysis of BPEL Web Services.	CIAO! / EOMAS	2008	DBLP DOI BibTeX RDF	exhaustive simulation, Web services, model checking, formal specification, process algebra
2	Mostefa Belarbi, Jean-Philippe Babau, Jean-Jacques Schwarz	Temporal Verification of Real-Time Multitasking Application Properties Based on Communicating Timed Automata.	DS-RT	2004	DBLP DOI BibTeX RDF	Exhaustive Simulation, Temporal Verification, Observer Automata, Communicating, Timed Automata, RTOS
2	Sujit Dey, Surendra Bommu	Performance analysis of a system of communicating processes.	ICCAD	1997	DBLP DOI BibTeX RDF	PERC, accurate worst case performance analysis technique, concurrent communicating processes, exhaustive simulation, multiple communicating processes, single process descriptions, system design space, system of communicating processes, worst case performance analysis, worst case performance estimate, performance analysis, system performance, performance estimation, communicating sequential processes, system implementation, synchronization overhead, inter process communication
2	Karen Panetta Lentz, Elias S. Manolakos, Edward C. Czeck	A multiple domain environment for efficient simulation.	Annual Simulation Symposium	1997	DBLP DOI BibTeX RDF	multiple domain environment, efficient simulation, concurrent simulation methodology, digital logic experimentation, multiple experiment environment, independent experiments, parallel hardware, digital logic simulators, signature paths, multiple experiment algorithms, function list, dynamic interactions, exhaustive simulation problem, Multiple Stuck-at Fault simulations, logic CAD, coverage analysis, digital logic
2	Daniel Brand	Exhaustive simulation need not require an exponential number of tests.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Patrice Bonhomme	Towards a new exhaustive simulation technique for P-time Petri nets.	ETFA	2010	DBLP DOI BibTeX RDF
1	Halder Subir, Amrita Ghosal, Sur Sanjib, Dan Avishek, DasBit Sipra	A Lifetime Enhancing Node Deployment Strategy in WSN.	FGIT	2009	DBLP DOI BibTeX RDF	node deployment, connectivity, coverage, network lifetime
1	Jonathan Billington, Smit Saboo	An investigation of credit-based flow control protocols.	SimuTools	2008	DBLP DOI BibTeX RDF	exhaustive simulation, flow control, coloured petri nets
1	Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij	Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip.	NOCS	2008	DBLP DOI BibTeX RDF	Cyclo-Static Dataflow, System on Chip, Network on Chip, Real-Time Performance
1	Nazanin Rahnavard, Badri N. Vellambi, Faramarz Fekri	Distributed Protocols for Finding Low-Cost Broadcast and Multicast Trees in Wireless Networks.	SECON	2008	DBLP DOI BibTeX RDF
1	Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu	Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Panagiotis D. Vouzis, Sylvain Collange, Mark G. Arnold	Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction.	DSD	2007	DBLP DOI BibTeX RDF
1	Wang-Dauh Tseng, Lung-Jen Lee	Reduction of Power Dissipation during Scan Testing by Test Vector Ordering.	MTV	2007	DBLP DOI BibTeX RDF
1	Praveen Tiwari, Raj S. Mitra, Manu Chopra, Alok Jain	Tutorial T4B: Formal Assertion-Based Verification in Industrial Setting.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Mohamed H. Zaki, Ghiath Al Sammane, Sofiène Tahar	Formal Verification of Analog and Mixed Signal Designs in Mathematica.	International Conference on Computational Science	2007	DBLP DOI BibTeX RDF	AMS Designs, Formal Verification, Mathematica
1	Noam Kogan, Yuval Shavitt, Avishai Wool	A practical revocation scheme for broadcast encryption using smartcards.	ACM Trans. Inf. Syst. Secur.	2006	DBLP DOI BibTeX RDF	smart cards, Broadcast encryption
1	Rüdiger Martin, Michael Menth, Michael Hemmkeppler	Accuracy and Dynamics of Hash-Based Load Balancing Algorithms for Multipath Internet Routing.	BROADNETS	2006	DBLP DOI BibTeX RDF
1	Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu	Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Stylianos Basagiannis, Panagiotis Katsaros, Andrew Pombortsis	Interlocking Control by Distributed Signal Boxes: Design and Verification with the SPIN Model Checker.	ISPA	2006	DBLP DOI BibTeX RDF	interlocking control, model checking, safety, distributed control
1	Charalabos Skianis, Lambros Sarakis	An Information Theoretic Approach for Systems with Parallel Distributions: Case Studying Internet Traffic.	Networking	2006	DBLP DOI BibTeX RDF
1	San-Yuan Wang, Jia-Yu Liu, Chun-Chien Huang, Mao-Yuan Kao, Yi-Ho Li	Signal Strength-Based Routing Protocol for Mobile Ad Hoc Networks.	AINA	2005	DBLP DOI BibTeX RDF
1	Scott K. Ralph, John M. Irvine, Magnús Snorrason, Mark R. Stevens, David Vanstone	An Image Metric-Based ATR Performance Prediction Testbed.	AIPR	2005	DBLP DOI BibTeX RDF
1	Colin D. Walter, David Samyde	Data Dependent Power Use in Multipliers.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF	EMA, smart card, Differential power analysis, DPA, multiplication, multiplier, RSA cryptosystem
1	E. George Walters III, Michael J. Schulte	Efficient Function Approximation Using Truncated Multipliers and Squarers.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
1	Jan Staschulat, Rolf Ernst, Andreas Schulze, Fabian Wolf	Context Sensitive Performance Analysis of Automotive Applications.	DATE	2005	DBLP DOI BibTeX RDF
1	Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija	A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Mohammad Riaz Moghal, Mohammad Saleem Mian	QoS-Aware Adaptive Resource Management in Distributed Multimedia System Using Server Clusters.	CLUSTER	2003	DBLP DOI BibTeX RDF
1	Noam Kogan, Yuval Shavitt, Avishai Wool	A Practical Revocation Scheme for Broadcast Encryption Using Smart Cards.	IEEE Symposium on Security and Privacy	2003	DBLP DOI BibTeX RDF
1	Chung-Min Chen, Randeep Bhatia, Rakesh K. Sinha	Multidimensional Declustering Schemes Using Golden Ratio and Kronecker Sequences.	IEEE Trans. Knowl. Data Eng.	2003	DBLP DOI BibTeX RDF	disk allocation, parallel databases, Declustering
1	T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua	Compiler-directed customization of ASIP cores.	CODES	2002	DBLP DOI BibTeX RDF	soft cores, embedded, customization, ASIP
1	Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali	Least-square estimation of average power in digital CMOS circuits.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen	Grouped input power sensitive transition an input sequence compaction technique for power estimation.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali	Average Power in Digital CMOS Circuits using Least Square Estimation.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj	Power Bus Maximum Voltage Drop in Digital VLSI Circuits.	ISQED	2000	DBLP DOI BibTeX RDF
1	Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj	Monte-Carlo approach for power estimation in sequential circuits.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Karen Panetta Lentz, Elias S. Manolakos, Edward C. Czeck, Jamie A. Heller	Multiple Experiment Environments for Testing.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	concurrent fault simulation, multiple stuck-at, interactive experimentation, scenario
1	Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang	Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	maximum switching activity, uncertainty waveforms, circuit reliability
1	Mark H. Linderman, Miriam Leeser	Simulation of digital circuits in the presence of uncertainty.	ICCAD	1994	DBLP DOI BibTeX RDF
1	Prabhat Jain, Ganesh Gopalakrishnan	Efficient symbolic simulation-based verification using the parametric form of Boolean expressions.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
1	Daniel Brand	Exhaustive simulation need not require an exponential number of tests.	ICCAD	1992	DBLP DOI BibTeX RDF
1	Antti Valmari	Eliminating Redundant Interleavings During Concurrent Program Verification.	PARLE	1989	DBLP DOI BibTeX RDF
1	Mandalagiri S. Chandrasekhar, J. P. Privitera, K. W. Conradt	Application of Term Rewriting Techniques to Hardware Design Verification.	DAC	1987	DBLP DOI BibTeX RDF