Search results for "fault collapsing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Audhild Vaaje	Theorems for Fault Collapsing in Combinational Circuits.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	Boolean function, combinational circuit, monotonic function, fault collapsing
2	Irith Pomeranz, Sudhakar M. Reddy	Safe Fault Collapsing Based on Dominance Relations.	European Test Symposium	2008	DBLP DOI BibTeX RDF	test generation, bridging faults, fault collapsing, dominance relations
2	Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal	Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults.	VTS	2008	DBLP DOI BibTeX RDF	Diagnosis, ATPG, Fault Model, Fault Collapsing, Implication Graph
2	Shiyi Xu	A New Approach to Improving the Test Effectiveness in Software Testing Using Fault Collapsing.	PRDC	2006	DBLP DOI BibTeX RDF	Software Testing, Mutation Testing, Testing Effectiveness, Fault Equivalence, Fault Dominance
2	Irith Pomeranz, Sudhakar M. Reddy	Fault Collapsing for Transition Faults Using Extended Transition Faults.	European Test Symposium	2006	DBLP DOI BibTeX RDF
2	Vishnu C. Vimjam, Michael S. Hsiao	Efficient Fault Collapsing via Generalized Dominance Relations.	VTS	2006	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Level of Similarity: A Metric for Fault Collapsing.	DATE	2004	DBLP DOI BibTeX RDF
2	Vishwani D. Agrawal, A. V. S. S. Prasad, Madhusudan V. Atre	Fault Collapsing via Functional Dominance.	ITC	2003	DBLP DOI BibTeX RDF
2	A. V. S. S. Prasad, Vishwani D. Agrawal, Madhusudan V. Atre	A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets.	ITC	2002	DBLP DOI BibTeX RDF
2	Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken	DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits.	ASYNC	2000	DBLP DOI BibTeX RDF	DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing
2	Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen	Fanout fault analysis for digital logic circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	fanout fault analysis, digital logic circuits, combinational benchmark circuits, sequential benchmark circuits, target faults, fault diagnosis, logic testing, test generation, sequential circuits, combinational circuits, fault simulation, fault collapsing
2	Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita	Transistor leakage fault location with ZDDQ measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	field effect transistor circuits, transistor leakage fault location, I/sub DDQ/ measurement, equivalence fault collapsing, diagnosed faults, gate-array circuit, fault diagnosis, logic testing, random tests, fault location, CMOS logic circuits, leakage currents, logic arrays, CMOS circuit, deterministic tests, electric current measurement, diagnostic resolution
2	Antonio Lloy	Advanced Fault Collapsing (Logic Circuits Testing).	IEEE Design & Test of Computers	1992	DBLP DOI BibTeX RDF
2	Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen	Single-fault fault-collapsing analysis in sequential logic circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF
1	Maheshwar Chandrasekar, Michael S. Hsiao	Fault Collapsing Using a Novel Extensibility Relation.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman	Structural fault collapsing by superposition of BDDs for test generation in digital circuits.	ISQED	2010	DBLP DOI BibTeX RDF
1	Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman	Fault collapsing with linear complexity in digital circuits.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Diagnostic fault simulation, diagnostic test generation, fault diagnosis, fault collapsing, fault equivalence, fault dominance
1	Pallav Gupta, Rui Zhang, Niraj K. Jha	Automatic Test Generation for Combinational Threshold Logic Networks.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Mohammad Gh. Mohammad, Laila Terkawi	Techniques for Disturb Fault Collapsing.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	algorithm, test, flash memory, faults, disturb
1	Hussain Al-Asaad	Efficient Global Fault Collapsing for Combinational Library Modules.	CDES	2007	DBLP BibTeX RDF
1	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael	Accelerating Diagnosis via Dominance Relations between Sets of Faults.	VTS	2007	DBLP DOI BibTeX RDF
1	Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael	Sub-faults identification for collapsing in diagnosis.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael	Evaluation of Collapsing Methods for Fault Diagnosis.	ISQED	2006	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Using Dummy Bridging Faults to Define Reduced Sets of Target Faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Raja K. K. R. Sandireddy, Vishwani D. Agrawal	Diagnostic and Detection Fault Collapsing for Multiple Output Circuits.	DATE	2005	DBLP DOI BibTeX RDF
1	Hussain Al-Asaad	EGFC: An exact global fault collapsing tool for combinational circuits.	Circuits, Signals, and Systems	2005	DBLP BibTeX RDF
1	Vishwani D. Agrawal, Alok S. Doshi	Concurrent Test Generation.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Pallav Gupta, Rui Zhang, Niraj K. Jha	An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks.	ICCD	2004	DBLP DOI BibTeX RDF
1	Abilio Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa	Fault Simulation Using Partially Reconfigurable Hardware.	FPL	2003	DBLP DOI BibTeX RDF
1	Matthew Worsman, Mike W. T. Wong, Y. S. Lee	A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality.	ISQED	2000	DBLP DOI BibTeX RDF	Equivalent faults, One-port circuits, Fault diagnosis, Design for testability, Fault collapsing
1	Zheng Rong Yang, Mark Zwolinski	Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog Circuits.	DATE	1999	DBLP DOI BibTeX RDF
1	Vamsi Boppana, W. Kent Fuchs	Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits.	ICCAD	1998	DBLP DOI BibTeX RDF
1	Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda, Pierluigi Civera	An Integrated HW and SW Fault Injection Environment for Real-Time Systems. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	Hybrid Fault Injection, Real-Time Systems, Dependability, Fault Injection
1	Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Raimund Ubar	A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Ralf Hahn, Rolf Krieger, Bernd Becker	A Hierarchical Approach to Fault Collapsing.	EDAC-ETC-EUROASIC	1994	DBLP BibTeX RDF
1	Younès Karkouri, El Mostapha Aboulhamid, Eduard Cerny, Alain Verreault	Use of Fault Dropping for Multiple Fault Analysis.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	fault dropping, multiple fault analysis, frontier faults, fault-free circuit, logic testing, stuck at faults, logic circuits, logic circuits, combinatorial circuits, benchmark circuits, gate level, fault collapsing, multiple stuck at faults
1	Yunzhan Gong, Daozheng Wei	Deductive fault simulation algorithm based on fault collapsing.	J. Comput. Sci. Technol.	1993	DBLP DOI BibTeX RDF
1	Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch	Fault modeling and fault equivalence in CMOS technology.	J. Electronic Testing	1991	DBLP DOI BibTeX RDF	test generation, Fault modeling, fault collapsing, fault equivalence
1	Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen	Single-fault fault collapsing analysis in sequential logic circuits.	ITC	1990	DBLP DOI BibTeX RDF
1	Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch	Fault modelling and fault equivalence in CMOS technology.	EURO-DAC	1990	DBLP DOI BibTeX RDF	Fault modelling, Test pattern generation, Fault collapsing