Search results for "fault coverage"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Hailong Cui, Sharad C. Seth, Shashank K. Mehta	Modeling Fault Coverage of Random Test Patterns.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	fault-coverage prediction, cost-benefit analysis of fault simulation, variance of fault coverage, BIST, probabilistic model
4	Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell	Statistical methods for delay fault coverage analysis.	VLSI Design	1995	DBLP DOI BibTeX RDF	delay fault coverage analysis, true value simulation, multi-value logic system, implicit random path sampling procedure, linear-time estimate, fault coverage estimates, longest path theorem, fanout branches, fault diagnosis, logic testing, delays, probability, statistical analysis, observabilities, multivalued logic, propagation delay, detection probabilities, statistical techniques, transition probabilities
3	Yung-Ruei Chang, Suprasad V. Amari, Sy-Yen Kuo	OBDD-Based Evaluation of Reliability and Importance Measures for Multistate Systems Subject to Imperfect Fault Coverage.	IEEE Trans. Dependable Sec. Comput.	2005	DBLP DOI BibTeX RDF	multistate system, importance measure, Reliability, fault-coverage, OBDD
3	Mitrajit Chatterjee, Dhiraj K. Pradhan	A BIST Pattern Generator Design for Near-Perfect Fault Coverage.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	core logic, built-in self-test, synthesis, fault coverage, Linear feedback shift registers, test pattern generation, scan, SOC
3	Marie-Lise Flottes, Christian Landrault, A. Petitqueux	Design for sequential testability: an internal state reseeding approach for 100 % fault coverage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset
3	Ameet Bagwe, Rubin A. Parekhji	Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fault coverage enhancement, embedded core based systems, test constraints, Texas Instruments TMS320C27xx, memory wrapper logic, fault diagnosis, logic testing, integrated circuit testing, application specific integrated circuits, functional testing, digital signal processing chips, fault analysis
3	Janusz Sosnowski	Improving Fault Coverage in System Tests.	IOLTW	2000	DBLP DOI BibTeX RDF	In system testing, test controllability and observability, fault coverage analysis, on-line monitoring
3	Michael S. Hsiao	On Non-Statistical Techniques for Fast Fault Coverage Estimation.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	fault coverage estimation, hyperactivity reduction, test generation, fault simulation, tolerance
3	Abdeslam En-Nouaary, Ferhat Khendek, Rachida Dssouli	Fault Coverage in Testing Real-Time Systems.	RTCSA	1999	DBLP DOI BibTeX RDF	Real-Time Systems, Testing, Specification, Implementation, Timed Automata, Fault Coverage
3	Xiao Sun, Carmie Hull	Functional Verification Coverage vs. Physical Stuck-at Fault Coverage. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	functional property, stuck-at fault coverage, verification coverage, UIO, verification, validation, ATPG, FSM, signature analysis, test application time
3	Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das	Delay Fault Coverage Enhancement Using Variable Observation Times.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	statistical delay fault coverage, delay test observation times, delay fault testing
3	Karim Arabi, Bozena Kaminska	Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology.	VTS	1997	DBLP DOI BibTeX RDF	Oscillation-Test Method, Parametric Fault Coverage, Analog Testing, Mixed-Signal Circuits
3	V. Prepin, R. David	Fault coverage of a long random test sequence estimated from a short simulation.	VTS	1997	DBLP DOI BibTeX RDF	long random test sequence, short simulation, fault coverage estimation, two-parameter model, fault diagnosis
3	Michel Renovell, P. Huc, Yves Bertrand	Bridging fault coverage improvement by power supply control.	VTS	1996	DBLP DOI BibTeX RDF	bridging fault coverage, power supply control, resistance interval, faulty value, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, logic circuits, parametric model, benchmark circuits
3	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Improving accuracy in path delay fault coverage estimation.	VLSI Design	1996	DBLP DOI BibTeX RDF	fault coverage estimation, simulated vector pair, exact fault simulation, fixed-length path-segments, fan-in branches, fan-out branches, flagged path-segments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time
3	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical path delay fault coverage estimation for synchronous sequential circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation
3	Mitrajit Chatterjee, Dhiraj K. Pradhan	A novel pattern generator for near-perfect fault-coverage.	VTS	1995	DBLP DOI BibTeX RDF	near-perfect fault-coverage, onchip BIST, GLFSR, logic mapping technique, weighted pattern technique, logic testing, built-in self test, integrated circuit testing, design methodology, combinational circuits, automatic testing, integrated logic circuits, shift registers, combinational logic, digital integrated circuits, pattern generator, single stuck-at fault
3	Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams	On the decline of testing efficiency as fault coverage approaches 100%.	VTS	1995	DBLP DOI BibTeX RDF	single stuck-at fault model, ISCAS benchmark circuits, nontarget defects, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault coverage, test pattern generation, manufacturing process, test quality, production testing, testing efficiency, circuit sizes
3	Marc Riedel, Janusz Rajski	Fault coverage analysis of RAM test algorithms.	VTS	1995	DBLP DOI BibTeX RDF	RAM test algorithms, flexible software analysis program, arbitrary test sequences, coverage statistics, functional cell-array faults, fault state transition conditions, representative fault classes, fault diagnosis, integrated circuit testing, fault coverage, random-access storage, integrated memory circuits, semiconductor memories, test algorithms
3	Eun Sei Park, M. Ray Mercer, Thomas W. Williams	The Total Delay Fault Model and Statistical Delay Fault Coverage.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	delay fault model, delay fault coverage, statistical delay fault coverage, defect level model, logic testing, delay testing, delay faults
3	Peter C. Maxwell, Robert C. Aitken	IDDQ testing as a component of a test suite: The need for several fault coverage metrics.	J. Electronic Testing	1992	DBLP DOI BibTeX RDF	quality, fault coverage, scan, functional testing, Current testing, physical defects
3	Deepinder P. Sidhu, Ting-Kau Leung	Formal Methods for Protocol Testing: A Detailed Study.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	NBS Class 4 Transport Protocol, protocol-test-sequence generation techniques, real-world communication protocols, protocols, fault detection, fault coverage, fault coverage, conformance testing, Monte Carlo methods, Monte Carlo simulation, failure analysis, test sequences, protocol implementation, protocol testing
2	Khaled El-Fakih, Nina Yevtushenko, Hacène Fouchal	Testing Timed Finite State Machines with Guaranteed Fault Coverage.	TestCom/FATES	2009	DBLP DOI BibTeX RDF
2	Zhen Chen, Boxue Yin, Dong Xiang	Conflict driven scan chain configuration for high transition fault coverage and low test power.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Albert F. Myers, Antoine Rauzy	Efficient Reliability Assessment of Redundant Systems Subject to Imperfect Fault Coverage Using Binary Decision Diagrams.	IEEE Transactions on Reliability	2008	DBLP DOI BibTeX RDF
2	Albert F. Myers	Achievable Limits on the Reliability of k-out-of-n: G Systems Subject to Imperfect Fault Coverage.	IEEE Transactions on Reliability	2008	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Parallel fault backtracing for calculation of fault coverage.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.	DFT	2008	DBLP DOI BibTeX RDF
2	Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee	A hybrid software-based self-testing methodology for embedded processor.	SAC	2008	DBLP DOI BibTeX RDF	embedded processor testing, fault coverage, functional testing, software-based self-test
2	Liudong Xing	Reliability Evaluation of Phased-Mission Systems With Imperfect Fault Coverage and Common-Cause Failures.	IEEE Transactions on Reliability	2007	DBLP DOI BibTeX RDF
2	Albert F. Myers	k-out-of-n: G System Reliability With Imperfect Fault Coverage.	IEEE Transactions on Reliability	2007	DBLP DOI BibTeX RDF
2	Sanghyeon Baeg	Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Seongmoon Wang	A BIST TPG for Low Power Dissipation and High Fault Coverage.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Jason G. Brown, R. D. (Shawn) Blanton	A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	fault diagnostic accuracy, nanofabrication, regular architectures, nanoFabric, fault diagnosis, logic testing, reconfigurability, integrated circuit testing, fault coverage, nanoelectronics, high defect densities
2	Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi	Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Seongmoon Wang, Srimat T. Chakradhar	A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Margrit R. Krug, Marcelo Lubaszewski, Marcelo de Souza Moraes	Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
2	Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi	Enhancing Delay Fault Coverage through Low Power Segmented Scan.	European Test Symposium	2006	DBLP DOI BibTeX RDF
2	Wen-Li Dong, Hang Yu	Web Service Testing Method Based on Fault-coverage.	EDOC Workshops	2006	DBLP DOI BibTeX RDF
2	Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram	Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring.	VTS	2006	DBLP DOI BibTeX RDF
2	Sezer Gören, F. Joel Ferguson	Test sequence generation for controller verification and test with high coverage.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	finite state machine, Fault coverage, black box testing, X-machine
2	Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-aware scan chain synthesis for improved path delay fault coverage.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	V. R. Devanathan	Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
2	Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz	Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
2	Peter Filter, Hana Kubatova	Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST.	DSD	2005	DBLP DOI BibTeX RDF
2	Wei Li 0023, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy	Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Nisar Ahmed, Mohammad Tehranipoor	Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique.	DFT	2005	DBLP DOI BibTeX RDF
2	Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz	A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals.	ICCD	2005	DBLP DOI BibTeX RDF
2	Suprasad V. Amari, Hoang Pham, G. Dill	Optimal design of k-out-of-n: G subsystems subjected to imperfect fault-coverage.	IEEE Transactions on Reliability	2004	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada	Practical Fault Coverage of Supply Current Tests for Bipolar ICs.	DELTA	2004	DBLP DOI BibTeX RDF
2	Wangqi Qiu, Xiang Lu, Jing Wang 0006, Zhuo Li, D. M. H. Walker, Weiping Shi	A Statistical Fault Coverage Metric for Realistic Path Delay Faults.	VTS	2004	DBLP DOI BibTeX RDF
2	Seongmoon Wang, Xiao Liu, Srimat T. Chakradhar	Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets.	DATE	2004	DBLP DOI BibTeX RDF
2	Shanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi	Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment.	DFT	2004	DBLP DOI BibTeX RDF
2	Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas	Exact path delay fault coverage with fundamental ZBDD operations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
2	Yi Zhao, Sujit Dey	Fault-coverage analysis techniques of crosstalk in chip interconnects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
2	Arun N. Netravali, Krishan K. Sabnani, Ramesh Viswanathan	Correct Passive Testing Algorithms and Complete Fault Coverage.	FORTE	2003	DBLP DOI BibTeX RDF
2	Seongmoon Wang, Srimat T. Chakradhar	A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs.	ITC	2003	DBLP DOI BibTeX RDF
2	Chen Fu, Richard P. Martin, Kiran Nagaraja, Thu D. Nguyen, Barbara G. Ryder, David Wonnacott	Compiler-Directed Program-Fault Coverage for Highly Available Java Internet Services.	DSN	2003	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit.	VTS	2003	DBLP DOI BibTeX RDF
2	Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage.	ICCAD	2003	DBLP DOI BibTeX RDF
2	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers	March SL: A Test For All Static Linked Memory Faults.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	fault coverage, Memory testing, march tests, functional fault models, linked faults
2	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker	Simulating Resistive Bridging and Stuck-At Faults.	ITC	2003	DBLP DOI BibTeX RDF	Resistive stuck-at faults, probabilistic fault coverage, Resistive bridging faults, bridging fault simulation
2	Takahisa Hiraide, Kwame Osei Boateng, Hideaki Konishi, Koichi Itaya, Michiaki Emori, Hitoshi Yamanaka, Takashi Mochiyama	BIST-Aided Scan Test - A New Method for Test Cost Reduction.	VTS	2003	DBLP DOI BibTeX RDF	ATPG, BIST, fault coverage, ATE, test cost reduction
2	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers	Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	static faults, fault models, fault coverage, memory tests, dynamic faults, fault primitives
2	Seongmoon Wang	Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST.	ITC	2002	DBLP DOI BibTeX RDF
2	Stanislaw J. Piestrak	Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
2	Jien-Chung Lo	Analysis of a BICS-Only Concurrent Error Detection Method.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	unsafe probability, reliability, fault coverage, testability, concurrent error detection, built-in current sensors, operating speed
2	Abdeslam En-Nouaary, Rachida Dssouli, Ferhat Khendek	Timed Wp-Method: Testing Real-Time Systems.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	real-time systems, Testing, specification, implementation, fault coverage, timed automaton
2	Bruce S. Greene, Samiha Mourad	Partial Scan Testing on the Register-Transfer Level.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	RT-level, fault coverage, partial scan, scan design, graph reduction
2	David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre	A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	BIST, datapath, high level test synthesis
2	Jayant Deodhar, Spyros Tragoudas	Color Counting and its Application to Path Delay Fault Coverage.	ISQED	2001	DBLP DOI BibTeX RDF
2	T. W. Williams, Stephen K. Sunter	How Should Fault Coverage Be Defined?	VTS	2000	DBLP DOI BibTeX RDF
2	Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer	On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	DO-RE-ME technique, MPG-D model, defective part level prediction, benchmark circuit simulations, stuck-at fault detection tests, bridging surrogate detection, stuck-at fault coverage, predictor accuracy, industrial circuit, test pattern sequences, integrated circuit testing, automatic test pattern generation, ATPG, fault simulation, logic circuit, circuit simulation, integrated logic circuits, correlation coefficient
2	Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal	Compaction-based test generation using state and fault information.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	compaction-based test generation, newly-traversed state information, newly-detected fault information, vector compaction iterations, vector sequence bias, biased vectors, compacted test set extension, intelligent vector selection, state analysis, fault diagnosis, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, iterative methods, vectors, fault coverage, circuit analysis computing, fault analysis, benchmark circuits, computing resources, vector generation
2	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
2	Said Hamdioui, A. J. van de Goor	An experimental analysis of spot defects in SRAMs: realistic fault models and tests.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	integrated circuit testing, fault models, fault coverage, SRAMs, functional fault models, SRAM chips, spot defects
2	Junichi Hirase, Shinichi Yoshimura	Faster processing for microprocessor functional ATPG.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	microprocessor functional ATPG, fault coverage improvement, short test pattern, processing speed increase, logic testing, integrated circuit testing, automatic test pattern generation, identification, test pattern generation, functional testing, microprocessor chips, instruction sets, instruction sets, microprocessor tests
2	Arabi Keshk, Yukiya Miura, Kozo Kinoshita	Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit oscillations, transistor level networks, feedback oscillation, Byzantine General's problems, logic threshold, logic testing, logic testing, integrated circuit testing, fault coverage, fault location, bridging fault, CMOS circuits, CMOS digital integrated circuits, test vector
2	Bin Liu, Fabrizio Lombardi, Wei-Kang Huang	Testing programmable interconnect systems: an algorithmic approach.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits
2	Eric MacDonald, Nur A. Touba	Testing domino circuits in SOI technology.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	silicon-on-insulator, SOI technology, dynamic circuit styles, fault modeling analysis, overall fault coverage, parasitic bipolar leakage, CMOS logic, logic testing, integrated circuit testing, automatic testing, fault simulation, CMOS logic circuits, leakage currents, domino circuits
2	Yiorgos Makris, Jamison Collins, Alex Orailoglu	Fast hierarchical test path construction for DFT-free controller-datapath circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fast hierarchical test path construction, DFT-free controller-datapath circuits, transparency based scheme, locally generated vectors, global design test, influence tables, valid control state sequences, module testing, fault coverage levels, vector counts, logic testing, test generation, automatic test pattern generation, ATPG, computational cost reduction
2	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
2	Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	TOF: a tool for test pattern generation optimization of an FPGA application oriented test.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG
2	Wei-Lun Wang, Kuen-Jong Lee	Accelerated test pattern generators for mixed-mode BIST environments.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
2	Ruofan Xu, Michael S. Hsiao	Embedded core testing using genetic algorithms.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	gate level implementation, user defined logic, random inputs, high level benchmarks, wrapper size, genetic algorithms, genetic algorithms, fault diagnosis, logic testing, controllability, controllability, high level synthesis, automatic test pattern generation, observability, observability, application specific integrated circuits, fault coverage, SOC, test application time, test patterns, embedded core testing, internal state
2	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	A genetic algorithm-based system for generating test programs for microprocessor IP cores.	ICTAI	2000	DBLP DOI BibTeX RDF	industrial property, genetic algorithm based system, test program generation, microprocessor IP cores, digital systems design trend, design-and-reuse paradigm, intellectual property cores, encrypted gate-level netlist, testability problems, automatic approach, processor cores, fault coverage figures, random approach, genetic algorithms, genetic algorithms, microprocessor chips, automatic test software, test program, electronic engineering computing
2	Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee	Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.	VLSI Design	2000	DBLP DOI BibTeX RDF	Extension field, BIST structure, Cellular Automata (CA), VLSI design and RTL, Finite field, DFT, Fault coverage, LFSR
2	Anna Maria Brosa, Joan Figueras	On Maximizing the Coverage of Catastrophic and Parametric Faults.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	analog & mixed-signal testing, fault coverage, set covering problems
2	Michael S. Hsiao, Srimat T. Chakradhar	Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	static test set compaction, vector-reordering, fault coverage curve, partitioning, ATPG
2	Von-Kyoung Kim, Tom Chen	On comparing functional fault coverage and defect coverage for memory testing.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
2	Junichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki	Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
2	Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu	Defect Level Prediction Using Multi-Model Fault Coverage.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
2	Von-Kyoung Kim, Tom Chen, Mick Tegethoff	Fault Coverage Estimation for Early Stage of VLSI Design.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
2	Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy	Full Scan Fault Coverage With Partial Scan.	DATE	1999	DBLP DOI BibTeX RDF
2	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	statistical fault analysis, fault simulation, delay test, path-delay faults, transition faults
2	Srinivas Devadas, Kurt Keutzer	An algorithmic approach to optimizing fault coverage for BIST logic synthesis.	ITC	1998	DBLP DOI BibTeX RDF
2	Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng	An almost full-scan BIST solution-higher fault coverage and shorter test application time.	ITC	1998	DBLP DOI BibTeX RDF