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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 28 occurrences of 25 keywords
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Results
Found 11 publication records. Showing 11 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 3 | Zhide Zeng, Jihua Chen, Pengxia Liu |
A Fault Partitioning Method in Parallel Test Generation for Large Scale VLSI Circuits.  |
Asian Test Symposium  |
1999 |
DBLP DOI BibTeX RDF |
Parallel Test Generation, Fault Parallelism, Fault Partitioning, Output Fan-in Cones, Input Fan-out Cones, Speed-up Ratio |
| 3 | Robert H. Klenke, James H. Aylor, Joseph M. Wolf |
An analysis of fault partitioning algorithms for fault partitioned ATPG.  |
VTS  |
1996 |
DBLP DOI BibTeX RDF |
fault partitioning algorithm, VLSI device, detected fault broadcasting, preprocessing time, parallel processing, parallel processing, VLSI, fault diagnosis, integrated circuit testing, ATPG, automatic testing, dynamic load balancing, NP complete problem, digital system, test vector generation |
| 2 | Elizabeth M. Rudnick, Janak H. Patel |
Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation.  |
VLSI Design  |
1997 |
DBLP DOI BibTeX RDF |
serial logic simulation bottleneck, parallel fault simulation, sequential circuit fault simulation algorithms, fault-partitioning approach, test set partitioning, parallel architectures, logic CAD, fault coverage, speedup, benchmark circuits |
| 2 | Steven Parkes, Prithviraj Banerjee, Janak H. Patel |
A parallel algorithm for fault simulation based on PROOFS . (PDF / PS)  |
ICCD  |
1995 |
DBLP DOI BibTeX RDF |
fault partitioning, dynamic partitioning schemes, compute intensive task, integrated circuit design process, rapid design turn around, ProperPROOFS, parallel extension, PROOFS fault simulation package, distributed method, fault redistribution, ISCAS-89 benchmark set, high performance serial fault simulation applications, parallel algorithms, parallel algorithm, parallel architectures, parallel architectures, fault diagnosis, logic testing, sequential circuits, sequential circuits, circuit analysis computing, logic partitioning |
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Partitioned n-detection test generation.  |
ACM Great Lakes Symposium on VLSI  |
2009 |
DBLP DOI BibTeX RDF |
fault partitioning, test generation, stuck-at faults, bridging faults, n-detection test sets |
| 1 | Kyunghwan Han, Soo-Young Lee |
A parallel implementation of fault simulation on a cluster of workstations.  |
IPDPS  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Michael S. Hsiao, Srimat T. Chakradhar |
Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits.  |
J. Electronic Testing  |
2000 |
DBLP DOI BibTeX RDF |
static test set compaction, vector-reordering, fault coverage curve, partitioning, ATPG |
| 1 | Joseph M. Wolf, Lori M. Kaufman, Robert H. Klenke, James H. Aylor, Ronald Waxman |
An analysis of fault partitioned parallel test generation.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
1996 |
DBLP DOI BibTeX RDF |
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| 1 | Jer-Min Jou, Shung-Chih Chen |
Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning.  |
ISCAS  |
1995 |
DBLP BibTeX RDF |
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| 1 | E. Calia, Antonio Lioy |
Test generation in a distributed environment.  |
SPDP  |
1991 |
DBLP DOI BibTeX RDF |
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| 1 | Srinivas Patil, Prithviraj Banerjee |
Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment.  |
ITC  |
1989 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #11 of 11 (100 per page; Change: )
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