Search results for "fault simulation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Michael S. Hsiao, Janak H. Patel	A new architectural-level fault simulation using propagation prediction of grouped fault-effects. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	architectural-level fault simulation, propagation prediction, grouped fault-effects, fault effects, intelligent propagation prediction, automated behavioral simulation, ALFSIM, Architectural Level Fault Simulation, gate level fault simulation, VLSI, fault diagnosis, circuit analysis computing, stuck at faults, integrated circuit design, deterministic algorithm, data types, symbolic data, architectural level
4	Irith Pomeranz, Sudhakar M. Reddy	On the feasibility of fault simulation using partial circuit descriptions.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	partial circuit description, gate-level circuits, subcircuits, logic testing, fault simulation, fault simulation, memory requirements
4	Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita	Test sequence compaction for sequential circuits with reset states.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction
4	Takaki Yoshida, Reisuke Shimoda, Takashi Mizokawa, Katsuhiro Hirayama	An effective fault simulation method for core based LSI.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	effective fault simulation, core based LSI, handling time, random sampling method, distributed fault simulation, FPP, faults per pass, hyper faults, mask patterns, random processes, DFS, yield analysis
4	Elizabeth M. Rudnick, Janak H. Patel	Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation.	VLSI Design	1997	DBLP DOI BibTeX RDF	serial logic simulation bottleneck, parallel fault simulation, sequential circuit fault simulation algorithms, fault-partitioning approach, test set partitioning, parallel architectures, logic CAD, fault coverage, speedup, benchmark circuits
4	Michel Renovell, P. Huc, Yves Bertrand	Serial transistor network modeling for bridging fault simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	serial transistor network modeling, voting model, biased voting model, relative transistor strength, SPICE pre-simulation, fault simulation procedure, CMOS logic, fault diagnosis, logic testing, integrated circuit testing, digital simulation, circuit analysis computing, CMOS logic circuits, SPICE, integrated circuit modelling, bridging fault simulation
4	Eiji Harada, Janak H. Patel	Overhead reduction techniques for hierarchical fault simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	overhead reduction techniques, hierarchical fault simulation, simulation overhead, concurrent method, multi-list-traversal method, one-pass fault simulation strategy, characteristic vectors, contiguous concurrent machines, ISCAS benchmark circuits, fault ordering, logic test sequences, fault diagnosis, logic testing, combinational circuits, logic CAD, digital simulation, circuit analysis computing, concurrent engineering, multivalued logic circuits, ULSI, ULSI
4	Minesh B. Amin, Bapiraju Vinnakota	Data parallel fault simulation. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	data parallel fault simulation, compute intensive problem, fault simulation time, fault set partitioning technique, low cost parallel resource, logic gate level, parallel programming, fault diagnosis, logic testing, logic CAD, circuit analysis computing, workstations, logic partitioning, multiple processors
4	Steven Parkes, Prithviraj Banerjee, Janak H. Patel	A parallel algorithm for fault simulation based on PROOFS . (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	fault partitioning, dynamic partitioning schemes, compute intensive task, integrated circuit design process, rapid design turn around, ProperPROOFS, parallel extension, PROOFS fault simulation package, distributed method, fault redistribution, ISCAS-89 benchmark set, high performance serial fault simulation applications, parallel algorithms, parallel algorithm, parallel architectures, parallel architectures, fault diagnosis, logic testing, sequential circuits, sequential circuits, circuit analysis computing, logic partitioning
3	Nicola Bombieri, Franco Fummi, Valerio Guarnieri	Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction.	European Test Symposium	2011	DBLP DOI BibTeX RDF	RTL fault simulation, fault simulation acceleration, RTL-to-TLM abstraction
3	Michael A. Kochte, Marcel Schaal, Hans-Joachim Wunderlich, Christian G. Zoellin	Efficient fault simulation on many-core processors.	DAC	2010	DBLP DOI BibTeX RDF	PPSFP, parallel fault simulation, many-core processors
3	Kanupriya Gulati, Sunil P. Khatri	Towards acceleration of fault simulation using graphics processing units.	DAC	2008	DBLP DOI BibTeX RDF	graphics processing units, fault simulation
3	Michel Morneau, Abdelhakim Khouas	TBSA: Threshold-Based Simulation Accuracy Method for Fast Analog DC Fault Simulation.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	DC fault simulation, analog fault detection, Newton-Raphson algorithm, analog testing
3	Li Shen 0002	VFSim: Concurrent Fault Simulation at Register Transfer Level.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	concurrent fault simulation, fault model, RTL, Verilog, high-level testing, circuit modeling
3	Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi	Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	hierarchical fault simulation, mixed level, delta times, VHDL, register transfer level
3	Li Shen	RTL Concurrent Fault Simulation.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	concurrent fault simulation, fault model, RTL, high-level testing, circuit modeling
3	Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik	Multi-Level Fault Simulation of Digital Systems on Decision Diagrams.	DELTA	2002	DBLP DOI BibTeX RDF	register transfer and gate level descriptions, fault simulation, decision diagrams, Digital systems
3	Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita	Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	Clock-delayed domino circuit, Fault simulation, crosstalk fault
3	Abdelhakim Khouas, Anne Derieux	Fault Simulation for Analog Circuits Under Parameter Variations.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	test optimisation, fault simulation, analog testing
3	Karen Panetta Lentz, Jonathan B. Homer	Handling Behavioral Components in Multi-Level Concurrent Fault Simulation.	Annual Simulation Symposium	2000	DBLP DOI BibTeX RDF	concurrent fault simulation, simulation, behavioral modeling, multilevel
3	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate
3	Matthew Worsman, Mike W. T. Wong, Y. S. Lee	Analog circuit equivalent faults in the D.C. domain.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	analog circuit faults, fault simulation data, equivalent faults, equivalent fault identification, built-in self test, design for testability, data analysis, fault simulation, fault location, fault location, analogue circuits, linear analog circuits
3	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita	Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	sequential circuit, fault simulation, bridging fault, IDDQ testing
3	Jing-Jou Tang	An Accurate Logic Threshold Voltages Determination Model for CMOS Gates to Facilitate Test Generation and Fault Simulation.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Logic Threshold Voltage, test generation, fault modeling, fault simulation
3	Abdelhakim Khouas, Mohamed Dessouky, Anne Derieux	Optimized Statistical Analog Fault Simulation.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Fault Simulation, Analog Testing, Statistical Simulation
3	Irith Pomeranz, Sudhakar M. Reddy	Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits.	ICCD	1999	DBLP DOI BibTeX RDF	test generation, fault simulation, stuck-at faults, bridging faults, circuit partitioning
3	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	cell fault model (CFM), fault simulation, test pattern generation, stuck-at fault model
3	Seiji Kajihara, Kewal K. Saluja	On Test Pattern Compaction Using Random Pattern Fault Simulation.	VLSI Design	1998	DBLP DOI BibTeX RDF	test generation, combinational circuit, fault simulation, stuck-at fault, test compaction
3	Alfred V. Gomes, Ramakrishna Voorakaranam, Abhijit Chatterjee	Modular Fault Simulation of Mixed Signal Circuits with Fault Ranking by Severity. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	Analog test generation, Fault modeling, Fault Simulation
3	Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel	Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation.	Workshop on Parallel and Distributed Simulation	1997	DBLP DOI BibTeX RDF	asynchronous parallel algorithms, dynamic characteristics, redundant work, sequential VLSI circuits, synchronous two stage approach, test set partitioned fault simulation, MPI, Message Passing Interface, shared memory multiprocessor, circuit analysis computing, circuit CAD, software portability
3	Laura Farinetti, Pier Luca Montessoro	The Dynamic Rollback Problem in Concurrent Event-Driven Fault Simulation.	VTS	1997	DBLP DOI BibTeX RDF	Fault Simulation
3	Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee	SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation.	VTS	1997	DBLP DOI BibTeX RDF	SPITFIRE, scalable parallel algorithms, test set partitioned fault simulation, synchronous parallel algorithms, sequential VLSI circuits, VLSI, fault coverage
3	Pascal Caunegre, Claude Abraham	Fault simulation for mixed-signal systems.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	mixed-signal systems, fault simulation, bridging faults
3	Chen-Pin Kung, Chen-Shang Lin	Parallel sequence fault simulation for synchronous sequential circuits.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	parallel sequence simulation, fault simulation, logic simulation
3	Ashok Balivada, Hong Zheng, Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham	A unified approach for fault simulation of linear mixed-signal circuits.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	arithmetic distance, testing, fault simulation, mixed-signal
3	Kuen-Jong Lee, Jing-Jou Tang	Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	efficient modeling techniques, enhanced test generation performance, fault modeling technique, inter-gate faults, threshold determination method, SPICE like accuracy, digital logic gates, logic testing, fault simulation, CMOS logic circuits, bridging faults, IDDQ testing, CMOS circuits
3	Sreejit Chakravarty	A sampling technique for diagnostic fault simulation.	VTS	1996	DBLP DOI BibTeX RDF	diagnostic fault simulation, diagnostic test sets, EC/IC Sampling, indistinguishable classes, approximation algorithm, fault diagnosis, integrated circuit testing, circuit analysis computing, set theory, equivalence classes, equivalence classes, sampling technique
3	Chen-Pin Kung, Chun-Jieh Huang, Chen-Shang Lin	Fast fault simulation for BIST applications.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	signature computation, BIST applications, combinational fault simulation, BISTSIM, demand-driven logic simulation algorithm, fault propagation methods, bit-array computation, parallel-pattern sequential simulation, speedup ratio, VLSI, VLSI, logic testing, built-in self test, integrated circuit testing, combinational circuits, digital simulation, circuit analysis computing, aliasing, test patterns, MISR
3	Winfried Hahn, Andreas Hagerer, R. Kandlbinder	Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computing.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	hardware-accelerated concurrent fault simulation, eventflow computing, highly-parallel Munich Simulation Computer, compiler-driven simulation, selective trace simulation, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, discrete event simulation, MuSiC, automatic testing, automatic testing, circuit analysis computing, logic simulation, concurrent engineering, test vectors, data flow computing, dataflow computing
3	Rolf Drechsler, Rolf Krieger, Bernd Becker	Random Pattern Fault Simulation in Multi-Valued Circuits. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	random pattern fault simulation, multi-valued circuits, multi-valued logic networks, fault diagnosis, logic testing, integrated circuit testing, fault simulator, circuit analysis computing, multivalued logic circuits, random pattern testability
3	Karen Panetta Lentz, Elias S. Manolakos, Edward C. Czeck	On the simulation of Multiple Stuck-at Faults using Multiple Domain Concurrent and Comparative Simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	multiple stuck-at fault simulation, multiple domain simulation, comparative simulation, MDCCS, discrete event concurrent simulation, CPU time efficiency, digital logic fault simulation, fault diagnosis, logic testing, discrete event simulation, circuit analysis computing, fault location, concurrent engineering
3	Kanji Hirabayashi	Delay fault simulation of sequential circuits.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	sequential circuit, fault simulation, robust test, Gate delay fault
3	Byung S. So, Charles R. Kime	A fault simulation method: Parallel pattern critical path tracing.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	parallel pattern simulation, single fault propagation, fault simulation, Critical path tracing
3	Vinod Narayanan, Vijay Pitchumani	Fault simulation on massively parallel SIMD machines algorithms, implementations and results.	J. Electronic Testing	1992	DBLP DOI BibTeX RDF	parallel algorithms, parallel processing, Fault simulation
3	Gabriel M. Silberman, Ilan Y. Spillinger	Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	functional fault simulation, biased-random test pattern generation, implementation-level faults, functional-level description, combinational VLSI design, difference fault model, formal abstraction, nonuniformly random test patterns, backtracing process, VLSI, logic testing, fault simulation, fault location, combinatorial circuits, functional fault model
3	Wilfried Daehn	Fault simulation using small fault samples.	J. Electronic Testing	1991	DBLP DOI BibTeX RDF	confidence level, sampling, fault simulation, Bayesian estimation
3	Michele Favalli, Piero Olivo, Bruno Riccò, Fabio Somenzi	Fault simulation for general FCMOS ICs.	J. Electronic Testing	1991	DBLP DOI BibTeX RDF	fault simulation, bridging faults, CMOS circuits, stuck-open faults, critical path analysis
3	Daniel G. Saab, Robert B. Mueller-Thuns, David Blaauw, Joseph T. Rahmeh, Jacob A. Abraham	Hierarchical multi-level fault simulation of large systems.	J. Electronic Testing	1990	DBLP DOI BibTeX RDF	multilevel simulation, testing, fault simulation, VLSI design
3	Wu-Tung Cheng, Meng-Lin Yu	Differential fault simulation for sequential circuits.	J. Electronic Testing	1990	DBLP DOI BibTeX RDF	test generation, sequential circuits, fault simulation
2	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits.	DELTA	2010	DBLP DOI BibTeX RDF	extended fault classes, parallel exact critical path tracing, fault simulation, digital circuits, fault analysis
2	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda	An efficient fault simulation technique for transition faults in non-scan sequential circuits.	DDECS	2009	DBLP DOI BibTeX RDF
2	Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian	SUPERB: Simulator utilizing parallel evaluation of resistive bridges.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	PPSFP, SPPFP, fault mapping, Resistive bridging faults, bridging fault simulation
2	Michele Favalli, Marcello Dalpasso	How Many Test Vectors We Need to Detect a Bridging Fault?	J. Electronic Testing	2009	DBLP DOI BibTeX RDF	Test generation, Fault simulation, Bridging faults
2	Irith Pomeranz, Sudhakar M. Reddy	Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Mariagrazia Graziano, Massimo Ruo Roch	An Automotive CD-Player Electro-Mechanics Fault Simulation Using VHDL-AMS.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Automotive electro-mechanical test, Fault simulation, VHDL-AMS
2	Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli	Vacuity Analysis by Fault Simulation.	MEMOCODE	2008	DBLP DOI BibTeX RDF
2	Kyunghwan Han, Soo-Young Lee	A parallel implementation of fault simulation on a cluster of workstations.	IPDPS	2008	DBLP DOI BibTeX RDF
2	Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker	Resistive Bridging Fault Simulation of Industrial Circuits.	DATE	2008	DBLP DOI BibTeX RDF
2	Jason G. Brown, R. D. (Shawn) Blanton	Automated Standard Cell Library Analysis for Improved Defect Modeling.	ISQED	2008	DBLP DOI BibTeX RDF	test generation, diagnosis, fault simulation, fault, defect
2	Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman	z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Hossam A. Gabbar, Akinlade Damilola, Hanaa E. Sayed	Trend analysis using real time fault simulation for improved fault diagnosis.	SMC	2007	DBLP DOI BibTeX RDF
2	C.-J. Richard Shi, Michael W. Tian, Guoyong Shi	Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber	A Mixed Language Fault Simulation of VHDL and SystemC.	DSD	2006	DBLP DOI BibTeX RDF
2	Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty	Path Delay Fault Simulation on Large Industrial Designs.	VTS	2006	DBLP DOI BibTeX RDF
2	Bharath Seshadri, Xiaoming Yu, Srikanth Venkataraman	Accelerating Diagnostic Fault Simulation Using Z-diagnosis and Concurrent Equivalence Identification.	VTS	2006	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	A delay fault model for at-speed fault simulation and test generation.	ICCAD	2006	DBLP DOI BibTeX RDF
2	Abhishek Singh, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel	Defect Simulation Methodology for iDDT Testing.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	iDDT, transient current testing, device testing, ATPG, fault simulation, IDDQ, defect simulation, defect-based test
2	Shahrzad Mirkhani, Zainalabedin Navabi	Enhancing Fault Simulation Performance by Dynamic Fault Clustering.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
2	Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman	Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs.	EDCC	2005	DBLP DOI BibTeX RDF
2	D. Barros Júnior, Marcial Jesús Rodríguez-Irago, Marcelino B. Santos, Isabel C. Teixeira, Fabian Vargas, João Paulo Teixeira	Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	intermittent faults modeling and simulation, digital SoC, EMI/EMC standard compliance, delay fault simulation, power supply voltage transients, fault tolerance
2	Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker	Modeling Feedback Bridging Faults with Non-Zero Resistance.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	feedback bridging faults, resistive bridging faults, bridging fault simulation
2	Sandip Kundu	Pitfalls of hierarchical fault simulation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
2	J. V. Deodhar, Spyros Tragoudas	Implicit deductive fault simulation for complex delay fault models.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Vladimir Hahanov, Irina Hahanova, Stanley Hyduke	Topological BDP Fault Simulation Method.	DSD	2004	DBLP DOI BibTeX RDF
2	Feng Shi, Yiorgos Makris	Fault simulation and random test generation for speed-independent circuits.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	random test pattern generation, fault simulation, asynchronous circuits, speed-independent circuits
2	Wilfried Steiner, John M. Rushby, Maria Sorea, Holger Pfeifer	Model Checking a Fault-Tolerant Startup Algorithm: From Design Exploration To Exhaustive Fault Simulation.	DSN	2004	DBLP DOI BibTeX RDF
2	Silvio Misera, Heinrich Theodor Vierhaus	FIT - A Parallel Hierarchical Fault Simulation Environment.	PARELEC	2004	DBLP DOI BibTeX RDF
2	Abhishek Singh, Chintan Patel, Jim Plusquellic	Fault Simulation Model for i{DDT} Testing: An Investigation.	VTS	2004	DBLP DOI BibTeX RDF
2	Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis	Simulating Single Event Transients in VDSM ICs for Ground Level Radiation.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	single fault propagation, fault simulation, soft-errors, single event upsets
2	Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski	Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	analog test generation, fault modeling, fault simulation, catastrophic faults, supply current monitoring
2	Junwei Hou, Abhijit Chatterjee	Concurrent transient fault simulation for analog circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
2	Nur Engin, Hans G. Kerkhoff	Fast Fault Simulation for Nonlinear Analog Circuits.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
2	J. Soares Augusto, Carlos Beltrán Almeida, H. C. Campos Neto	A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits.	FPL	2003	DBLP DOI BibTeX RDF
2	Abilio Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa	Fault Simulation Using Partially Reconfigurable Hardware.	FPL	2003	DBLP DOI BibTeX RDF
2	Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi	The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
2	Vladimir Hahanov, Raimund Ubar, Stanley Hyduke	Back-Traced Deductive-Parallel Fault Simulation for Digital Systems.	DSD	2003	DBLP DOI BibTeX RDF	back traced simulation, re-convergent fan-outs, fault analysis model, ATPG, parallel simulation, deductive
2	Xiaoming Yu, Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz	Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation.	VTS	2003	DBLP DOI BibTeX RDF
2	Nabil M. Abdulrazzaq, Sandeep K. Gupta	Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets.	VTS	2003	DBLP DOI BibTeX RDF
2	Reza Sedaghat	A fast algorithm to reduce 2-dimensional assignment problems to 1-dimensional assignment problems for FPGA-based fault simulation.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Hailong Cui, Sharad C. Seth, Shashank K. Mehta	Modeling Fault Coverage of Random Test Patterns.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	fault-coverage prediction, cost-benefit analysis of fault simulation, variance of fault coverage, BIST, probabilistic model
2	Irith Pomeranz, Sudhakar M. Reddy	n-pass n-detection fault simulation and its applications.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	Shu Chen, Paul Olson, Stephen A. Morrison	A Distributed Graphical Environment for Interactive Fault Simulation and Analysis.	Annual Simulation Symposium	2002	DBLP DOI BibTeX RDF
2	Sule Ozev, Alex Orailoglu	An Integrated Tool for Analog Test Generation and Fault Simulation. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF
2	Dominique Federici, Paul Bisgambiglia, Jean François Santucci	Behavioral Fault Simulation: Implementation and Experiments Results.	DELTA	2002	DBLP DOI BibTeX RDF
2	Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi	Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
2	Marong Phadoongsidhi, Kim T. Le, Kewal K. Saluja	A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
2	Ilia Polian, Piet Engelke, Bernd Becker	Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. (PDF / PS)	ISMVL	2002	DBLP DOI BibTeX RDF	Voting models, Fault simulation, Bridging faults
2	Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu	Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	Test generation, Fault simulation, Power dissipation, CMOS circuit
2	Irith Pomeranz, Sudhakar M. Reddy	Forward-looking fault simulation for improved static compaction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
2	Hans G. Kerkhoff, Hans P. A. Hendriks	Fault Modeling and Fault Simulation in Mixed Micro-Fluidic Microelectronic Systems.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	microsystem testing, analogue fault modeling, analogue fault simulation, fluidic FEM simulation, defect-oriented testing