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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 15 occurrences of 15 keywords
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Results
Found 12 publication records. Showing 12 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 2 | Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke |
Enabling ultra low voltage system operation by tolerating on-chip cache failures.  |
ISLPED  |
2009 |
DBLP DOI BibTeX RDF |
fault-tolerant cache, low voltage operation, dynamic voltage scaling |
| 2 | Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato |
Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs.  |
HiPC  |
2008 |
DBLP DOI BibTeX RDF |
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| 2 | Amit Agarwal, Bipul Chandra Paul, Kaushik Roy |
A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies.  |
IOLTS  |
2004 |
DBLP DOI BibTeX RDF |
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| 2 | Xrysovalantis Kavousianos, Dimitris Nikolos |
Self-exercising self testing k-order comparators.  |
VTS  |
1997 |
DBLP DOI BibTeX RDF |
self testing k-order comparators, self-exercising comparators, equality comparator, fault tolerant cache memory, built-in self test, error correction codes, combinational circuit, error detection codes, broadcast networks |
| 1 | Shuchang Shan, Yu Hu, Xiaowei Li |
Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors.  |
DSN  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Abbas BanaiyanMofrad, Houman Homayoun, Nikil Dutt |
FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation.  |
CASES  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio González |
Low Vccmin fault-tolerant cache with highly predictable performance.  |
MICRO  |
2009 |
DBLP DOI BibTeX RDF |
Vccmin, cache, faults, predictable performance |
| 1 | Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi |
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).  |
CASES  |
2009 |
DBLP DOI BibTeX RDF |
low power memory organization, memory organization., remapping cache, variation aware cache, fault tolerance, low power design, low power cache, vfs |
| 1 | Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li |
The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies.  |
ICCD  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke |
ZerehCache: armoring cache architectures in high defect density technologies.  |
MICRO  |
2009 |
DBLP DOI BibTeX RDF |
fault-tolerant cache, process variation, manufacturing yield |
| 1 | Hamid R. Zarandi, Seyed Ghassem Miremadi |
A fault-tolerant cache architecture based on binary set partitioning.  |
Microelectronics Reliability  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | H. T. Verges, D. Nikolos |
Efficient fault tolerant cache memory design.  |
Microprocessing and Microprogramming  |
1995 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #12 of 12 (100 per page; Change: )
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