Search results for "faults"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Bin Liu, Fabrizio Lombardi, Wei-Kang Huang	Testing programmable interconnect systems: an algorithmic approach.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits
7	Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell	Functional test generation for path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults
6	V. Kim, T. Chen	Assessing SRAM test coverage for sub-micron CMOS technologies.	VTS	1997	DBLP DOI BibTeX RDF	submicron CMOS technologies, SRAM test coverage assessment, memory fault probability model, memory array, data retention faults, memory fault coverages, memory test algorithms, functional fault class coverages, 0.5 to 1 mum, stuck-at faults, transition faults, stuck-open faults, coupling faults, physical defects, CMOS memory circuits
6	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
6	Wei-lun Kao, Ravishankar K. Iyer, Dong Tang	FINE: A Fault Injection and Monitoring Environment for Tracing the UNIX System Behavior under Faults.	IEEE Trans. Software Eng.	1993	DBLP DOI BibTeX RDF	FINE, fault injection and monitoring environment, UNIX system behavior, hardware-induced software errors, fault injector, analysis utilities, SunOS 4.1.2, transient Markov reward analysis, bus faults, CPU faults, pointer faults, software tools, Unix, program testing, system monitoring, software faults, software monitor, workload generator
6	Yashwant K. Malaiya, Stephen Y. H. Su	Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	modeling of faults, Markov model, transient faults, multiple faults, fault-tolerant system, reliability analysis, intermittent faults, permanent faults, Fault-tolerant design, reliability evaluation, reconfiguration scheme, hardware redundancy
5	Jack R. Smith, Tian Xia, Charles E. Stroud	An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	stuck-at faults, bridging faults, delay faults
5	Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour	Diagnosing multiple transition faults in the absence of timing information.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	diagnosis, multiple faults, delay faults, incremental, transition faults
5	Cecilia Metra, Michele Favalli, Bruno Riccò	Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	bus lines, diagnosis, transient faults, On-line testing, delay faults, self-checking, crosstalk faults
5	Yuyun Liao, D. M. H. Walker	Optimal voltage testing for physically-based faults.	VTS	1996	DBLP DOI BibTeX RDF	optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise
5	Mark C. Hansen, John P. Hayes	High-level test generation using physically-induced faults.	VTS	1995	DBLP DOI BibTeX RDF	high-level test generation, physically-induced faults, industry-standard single stuck-line faults, independent functional faults, near-minimal size, fault diagnosis, logic testing, integrated circuit testing, design for testability, automatic testing, functional tests, failure analysis, benchmark circuits, circuit under test
5	Samy Makar, Edward J. McCluskey	Checking experiments to test latches.	VTS	1995	DBLP DOI BibTeX RDF	exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults
5	Irith Pomeranz, Sudhakar M. Reddy	Classification of Faults in Synchronous Sequential Circuits.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	undetectable faults, initial conditions, partially detectable faults, synchronization mode, free mode, logic testing, sequential circuits, synchronisation, fault location, synchronous sequential circuits, combinatorial circuits, test sequence, faults classification, redundant faults
4	Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz	On the Detectability of Scan Chain Internal Faults An Industrial Case Study.	VTS	2008	DBLP DOI BibTeX RDF	Faults in scan cells, stuck-at and stuck-on faults
4	Evangelos Kranakis, Michel Paquette, Andrzej Pelc	Communication in Random Geometric Radio Networks with Positively Correlated Random Faults.	ADHOC-NOW	2008	DBLP DOI BibTeX RDF	dependent faults, crash faults, geometric radio network, Fault-tolerance, broadcast, random
4	Evangelos Kranakis, Michel Paquette, Andrzej Pelc	Communication in Networks with Random Dependent Faults.	MFCS	2007	DBLP DOI BibTeX RDF	dependent faults, crash faults, Fault-tolerance, communication, network connectivity
4	Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen	IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	oscillation ring (OR) test scheme, open faults, crosstalk glitches, IEEE P1500, wrapper cell design, stuck-at faults, delay faults, SOC testing, interconnect test
4	József Sziray	Test Calculation for Logic and Delay Faults in Digital Circuits.	MTV	2006	DBLP DOI BibTeX RDF	Test-pattern calculation, logic faults, CMOS transistor structures, functional testing, delay faults, multi-valued logic
4	Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker	Modeling Feedback Bridging Faults with Non-Zero Resistance.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	feedback bridging faults, resistive bridging faults, bridging fault simulation
4	Joonhwan Yi, John P. Hayes	The Coupling Model for Function and Delay Faults.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	test generation, fault modeling, delay faults, functional faults
4	Petru Cascaval, Stuart Bennett, Corneliu Hutanu	Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	fault simulation, memory testing, march test, coupling faults, functional faults
4	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers	Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	static faults, fault models, fault coverage, memory tests, dynamic faults, fault primitives
4	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker	Simulating Resistive Bridging and Stuck-At Faults.	ITC	2003	DBLP DOI BibTeX RDF	Resistive stuck-at faults, probabilistic fault coverage, Resistive bridging faults, bridging fault simulation
4	Claude Thibeault	On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Delta ${rm I}_{DDQ}$, probabilistic signatures, diagnosis, Integrated circuits, bridging faults, multiple faults
4	Ramesh C. Tekumalla, Premachandran R. Menon	On Redundant Path Delay Faults in Synchronous Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	functional sensitizability, sequential circuits, testability, Path delay faults, redundant faults
4	Toshiyuki Maeda, Kozo Kinoshita	Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
4	Matthew Worsman, Mike W. T. Wong, Y. S. Lee	Analog circuit equivalent faults in the D.C. domain.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	analog circuit faults, fault simulation data, equivalent faults, equivalent fault identification, built-in self test, design for testability, data analysis, fault simulation, fault location, fault location, analogue circuits, linear analog circuits
4	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
4	Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy	Fsimac: a fault simulator for asynchronous sequential circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
4	Irith Pomeranz, Sudhakar M. Reddy	Vector-Based Functional Fault Models for Delay Faults.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	functional tests, delay faults, path delay faults
4	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	function-robust tests, functional delay fault model, delay faults, path delay faults, robust tests
4	Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana	Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using I/sub DDQ/ Testing in BiCMOS and CMOS Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF	input pattern classification, BiCMOS circuits, quiescent power supply current monitoring, enhanced I/sub DDQ/, fault diagnosis, bridging faults, CMOS circuits, I/sub DDQ/ testing, stuck-ON faults
4	Michele Favalli, Cecilia Metra	Low-level error recovery mechanism for self-checking sequential circuits. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	low-level error recovery mechanism, self-checking sequential circuits, reliability requirements, small embedded systems, sequential circuits, design methodology, transient faults, delay faults, fault tolerant capabilities, crosstalk faults
4	H. Goto, S. Nakamura, K. Iwasaki	Experimental fault analysis of 1 Mb SRAM chips.	VTS	1997	DBLP DOI BibTeX RDF	stuck-at cell faults, stuck-at bit-line faults, stuck-at word-line fault, neighborhood-pattern-sensitive faults, load capacity, margin fault detection, 1 Mbit, 70 C, 30 pF, memory testing, fault analysis, SRAM chips, SRAM chips
4	Kuen-Jong Lee, Jing-Jou Tang	Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	efficient modeling techniques, enhanced test generation performance, fault modeling technique, inter-gate faults, threshold determination method, SPICE like accuracy, digital logic gates, logic testing, fault simulation, CMOS logic circuits, bridging faults, IDDQ testing, CMOS circuits
4	Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai	Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	CMOS bridging faults detection, ATPG system, built-in intermediate voltage sensing, BIFEST system, PODEM-like process, PPSFP-based process, logic monitoring, gate threshold ranges, Byzantine General's Command Problem, feedback bridging faults, parallel pattern single fault propagation, fault modelling, fault simulation, fault coverage, greedy algorithm, CMOS logic circuits
4	Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham	A novel test generation approach for parametric faults in linear analog circuits .	VTS	1996	DBLP DOI BibTeX RDF	digital test software, time-domain tests, equivalent digital circuit, digital test vectors, test waveform, VLSI, test generation, integrated circuit testing, fault location, stuck-at faults, analogue integrated circuits, parametric faults, linear analog circuits, time-domain analysis, equivalent circuits, analogue processing circuits
4	A. J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik	March LR: a test for realistic linked faults. (PDF / PS)	VTS	1996	DBLP DOI BibTeX RDF	disturb faults, March LR, March LRD, March LRDD, fault diagnosis, integrated circuit testing, fault models, fault coverage, march tests, integrated memory circuits, semiconductor memories, linked faults
4	Alok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli	Compact and complete test set generation for multiple stuck-faults.	ICCAD	1996	DBLP DOI BibTeX RDF	Multiple stuck faults, complete test set generation, irrepressible faults
4	K. Vijayananda	Distributed fault detection in communication protocols using extended finite state machines. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	distributed fault detection, run-time fault detection, coding defects, memory problems, protocol faults, vocabulary faults, sequencing faults, parallel decomposition method, multiple observers, distributed fault detection mechanism, fault tolerant computing, finite state machines, transport protocols, encoding, communication protocols, fault coverage, extended finite state machines
4	Salvador Manich, Michael Nicolaidis, Joan Figueras	Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring.	VTS	1996	DBLP DOI BibTeX RDF	mathematical operators, parity prediction array arithmetic operators, IDDQ current monitoring, fault diagnosis, logic testing, fault detection, stuck-at faults, bridging faults, multiplying circuits, multiplier circuit, arithmetic circuits, logic arrays, stuck-open faults, topological design, SPICE simulation, fault secureness
4	Theo J. Powell	Consistently dominant fault model for tristate buffer nets.	VTS	1996	DBLP DOI BibTeX RDF	buffer circuits, consistently dominant fault model, tristate buffer nets, floating type faults, contention type faults, MISR signature loss, test pattern compression, VLSI, fault diagnosis, logic testing, integrated circuit testing, fault detection, fault location, integrated logic circuits, multivalued logic circuits, ternary logic, stuck faults
4	Kuo-Chung Tai	Theory of Fault-Based Predicate Testing for Computer Programs.	IEEE Trans. Software Eng.	1996	DBLP DOI BibTeX RDF	predicate testing, boolean operator faults, relational operator faults, off-by-$epsilon$ faults, Software testing, fault-based testing
4	Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal	Test Generation for Path Delay Faults Using Binary Decision Diagrams.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	Boolean algebraic test generation, redundant delay faults, robust delay tests, scan testing of delay faults, binary decision diagrams, delay faults
4	Wen Ching Wu, Chung-Len Lee, Jwu E. Chen	Identification of robust untestable path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification
4	Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara	Compact test generation for bridging faults under I/sub DDQ/ testing.	VTS	1995	DBLP DOI BibTeX RDF	compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing
4	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez	Diagnostic of path and gate delay faults in non-scan sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, self-masking identification, fault diagnosis, fault diagnosis, logic testing, delays, integrated circuit testing, sequential circuits, automatic testing, integrated logic circuits, path delay faults, synchronous sequential circuits, path tracing, gate delay faults
4	Hiroaki Ueda, Kozo Kinoshita	Low power design and its testability.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuck-at faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability
4	Udo Mahlstedt, Jürgen Alt, Matthias Heinitz	CURRENT: a test generation system for I/sub DDQ/ testing.	VTS	1995	DBLP DOI BibTeX RDF	CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
4	Andrej Zemva, Franc Brglez	Detectable perturbations: a paradigm for technology-specific multi-fault test generation.	VTS	1995	DBLP DOI BibTeX RDF	detectable perturbations, technology-specific multi-fault test generation, multiple bridging, open faults, single-output modules, multi-output modules, mutation faults, technology-mapped cells, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, stuck-at faults, cellular arrays, benchmark circuits, generic system
4	Bruce F. Cockburn	Deterministic tests for detecting singleV-coupling faults in RAMs.	J. Electronic Testing	1994	DBLP DOI BibTeX RDF	V-coupling faults, lower bounds, Functional tests, pattern-sensitive faults, RAM testing
4	Yinong Chen, Winfried Bücken, Klaus Echtle	Efficient Algorithms for System Diagnosis with Both Processor and Comparator Faults.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	processor faults, comparison-based self-diagnosis, multiprocessorsystems, comparator faults, O(mod E mod)/sup 2/ algorithm, computational complexity, fault tolerant computing, multiprocessing systems, system diagnosis
4	El Mostapha Aboulhamid, Younès Karkouri, Eduard Cerny	On the generation of test patterns for multiple faults.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	Combinational circuits, stuck-at faults, test pattern generation, multiple faults, fault analysis
4	Bruce F. Cockburn, Janusz A. Brzozowski	Near-optimal tests for classes of write-triggered coupling faults in RAMs.	J. Electronic Testing	1992	DBLP DOI BibTeX RDF	toggling faults, lower bounds, coupling faults, RAM testing, optimal tests
4	Janusz A. Brzozowski, Bruce F. Cockburn	Detection of coupling faults in RAMs.	J. Electronic Testing	1990	DBLP DOI BibTeX RDF	toggling faults, fault modeling, coupling faults, RAM testing, optimal tests
4	René David, Antoine Fuentes, Bernard Courtois	Random Pattern Testing Versus Deterministic Testing of RAM's.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	random pattern testing, double faults, classical fault models, multiple-coupling faults, Markov chains, integrated circuit testing, Markov processes, random-access storage, RAMs, test patterns, parameters, random-access memories, pattern-sensitive faults, deterministic testing, single faults
4	Bhargab B. Bhattacharya, Bidyut Gupta	On the Impossible Class of Faulty Functions in Logic Networks Under Short Circuit Faults.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	fan-out-free functions, N-equivalence classes, P-equivalence classes, short circuit faults, fault detection, stuck-at faults, Bridging faults, combinational logic, unate functions
4	Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara	An Easily Testable Design of Programmable Logic Arrays for Multiple Faults.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	stuck-type faults, Cross-point faults, easily testable design, programmable logic arrays, multiple faults
3	Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson	Energy-efficient redundant execution for chip multiprocessors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	redundant execution, microarchitecture, transient faults, permanent faults
3	Umberto Ferraro Petrillo, Irene Finocchi, Giuseppe F. Italiano	The Price of Resiliency: a Case Study on Sorting with Memory Faults.	Algorithmica	2009	DBLP DOI BibTeX RDF	Memory faults, Computing with unreliable information, Sorting, Fault injection, Memory models, Experimental algorithmics
3	Michael Crocker, Xiaobo Sharon Hu, Michael T. Niemier	Defects and faults in QCA-based PLAs.	JETC	2009	DBLP DOI BibTeX RDF	logic mapping, Nanotechnology, faults, defects, quantum-dot cellular automata
3	Jiangang Yi, Peng Zeng	Analysis of Two Neural Networks in the Intelligent Faults Diagnosis of Metallurgic Fan Machinery.	ISNN	2009	DBLP DOI BibTeX RDF	Metallurgic fan machinery, Intelligent faults diagnosis, ANN
3	Irith Pomeranz, Sudhakar M. Reddy	Partitioned n-detection test generation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	fault partitioning, test generation, stuck-at faults, bridging faults, n-detection test sets
3	Yuanyuan Zhang, Qingwu Gong, Xi Shi	A Novel Adaptive Reclosure Criterion for HV Transmission Lines Based on Wavelet Packet Energy Entropy.	ISNN	2009	DBLP DOI BibTeX RDF	Wavelet packet energy entropy(WPEE), HV transmission line, single-phase adaptive reclosure, Transient faults, Permanent faults
3	Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi	Adapting to intermittent faults in multicore systems.	ASPLOS	2008	DBLP DOI BibTeX RDF	overcommitted system, intermittent faults
3	Stephan Eggersglüß, Rolf Drechsler	On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults.	ISMVL	2008	DBLP DOI BibTeX RDF	Boolean Encodings, ATPG, SAT, Path Delay Faults
3	Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda	A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.	VTS	2008	DBLP DOI BibTeX RDF	SBST, path-delay faults, microprocessor test
3	Irith Pomeranz, Sudhakar M. Reddy	Synthesis for Broadside Testability of Transition Faults.	VTS	2008	DBLP DOI BibTeX RDF	broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
3	Hafizur Rahaman, Dipak K. Kole, Debesh Kumar Das, Bhargab B. Bhattacharya	On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set.	VLSI Design	2008	DBLP DOI BibTeX RDF	Missing-gate faults, quantum computing, reversible logic, testable design, universal test set
3	Bogdan Tomoyuki Nassu, Takashi Nanya	Interaction Faults Caused by Third-Party External Systems - A Case Study and Challenges.	ISAS	2008	DBLP DOI BibTeX RDF	Interaction Faults, Error Detection, Fault Model, Communication Protocols, Case Study
3	Shujian Wu, Qing Wang, Ye Yang	Quantitative analysis of faults and failures with multiple releases of softpm.	ESEM	2008	DBLP DOI BibTeX RDF	software faults and failures, metrics, empirical studies
3	Kyriakos Christou, Maria K. Michael, Spyros Tragoudas	On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Zero-suppressed binary decision diagram, Irredundant sum-of-products, Critical path delay faults, Compact test generation, Delay testing, Path delay faults
3	Martin Omaña, Daniele Rossi, Cecilia Metra	Latch Susceptibility to Transient Faults and New Hardening Approach.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Static Latch, Hardened Latch, Soft Errors, Transient Faults, Robust Design
3	Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Lima Kastensmidt, Luigi Carro	Using majority logic to cope with long duration transient faults.	SBCCI	2007	DBLP DOI BibTeX RDF	long duration transient faults, majority logic
3	Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev	Optimizing Test Length for Soft Faults in DRAM Devices.	VTS	2007	DBLP DOI BibTeX RDF	DRAM testing, test length optimization, circuit design, memory layout, delay time, soft faults
3	Frances Perry, Lester W. Mackey, George A. Reis, Jay Ligatti, David I. August, David Walker	Fault-tolerant typed assembly language.	PLDI	2007	DBLP DOI BibTeX RDF	transient hardware faults, fault tolerance, typed assembly language, soft faults
3	Martin Biely, Josef Widder, Bernadette Charron-Bost, Antoine Gaillard, Martin Hutle, André Schiper	Tolerating corrupted communication.	PODC	2007	DBLP DOI BibTeX RDF	consensus, transient faults, byzantine fault tolerance, dynamic faults
3	Jan Ploski, Matthias Rohr, Peter Schwenkenberg, Wilhelm Hasselbring	Research issues in software fault categorization.	ACM SIGSOFT Software Engineering Notes	2007	DBLP DOI BibTeX RDF	injection of software faults, software fault categorization, software reliability, bugs, software faults
3	Irith Pomeranz, Sudhakar M. Reddy	Forming N-detection test sets without test generation.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	test generation, stuck-at faults, Bridging faults, n-detection test sets
3	Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero	PPM Reduction on Embedded Memories in System on Chip.	European Test Symposium	2007	DBLP DOI BibTeX RDF	static faults, PPM reduction, memory testing, dynamic faults
3	Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji	Modified Stability Checking for On-line Error Detection.	VLSI Design	2007	DBLP DOI BibTeX RDF	crosstalk faults and transient faults, SEU testing, modified stability checking, delay faults, self-checking circuits, Concurrent testing, on-line error detection
3	Joseph Aguilar-Martin, Claudia Isaza, Eduard Diez-Lledo, Marie-Véronique Le Lann, Julio Waissman Vilanova	Process Monitoring Using Residuals and Fuzzy Classification with Learning Capabilities.	IFSA	2007	DBLP DOI BibTeX RDF	Residuals, Fuzzy Classification, Faults Isolation, Faults Identification
3	Yuming Zhou, Hareton Leung	Empirical Analysis of Object-Oriented Design Metrics for Predicting High and Low Severity Faults.	IEEE Trans. Software Eng.	2006	DBLP DOI BibTeX RDF	Object-oriented, metrics, prediction, faults, cross validation, fault-proneness
3	João Durães, Henrique Madeira	Emulation of Software Faults: A Field Data Study and a Practical Approach.	IEEE Trans. Software Eng.	2006	DBLP DOI BibTeX RDF	software reliability, Fault injection, software faults
3	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor	Opens and Delay Faults in CMOS RAM Address Decoders.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	address decoder delay faults, addressing methods, BIST, DFT, Memory testing, open defects
3	Irith Pomeranz, Sudhakar M. Reddy	On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	overtesting, test generation, Design-for-testability, synchronous sequential circuits, redundant faults, full-scan, fault dominance
3	Jong-Hoon Youn, Bella Bose, Seungjin Park	Fault-Tolerant Routing Algorithm in Meshes with Solid Faults.	The Journal of Supercomputing	2006	DBLP DOI BibTeX RDF	solid faults, fault-tolerant, wormhole routing, mesh networks
3	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	BIST, delay faults, look-up table
3	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker	Automatic Test Pattern Generation for Resistive Bridging Faults.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	resistive short defects, ATPG, SAT, bridging faults
3	Kai Chen 0005, Fan Jiang, Chuan-dong Huang	A new method of generating synchronizable test sequences that detect output-shifting faults based on multiple UIO sequences.	SAC	2006	DBLP DOI BibTeX RDF	output-shifting faults, synchronization problems, distributed system, conformance testing, FSM
3	Colin Cooper, Ralf Klasing, Tomasz Radzik	Searching for Black-Hole Faults in a Network Using Multiple Agents.	OPODIS	2006	DBLP DOI BibTeX RDF	black hole faults, mobile agent, Graph exploration
3	Zeng Shuiping, Li Jinhong	Diagnosis System of the Anode Faults for Alumina Reduction Cell.	ISDA	2006	DBLP DOI BibTeX RDF	Aluminum production, diagnosis system, Anode effect, Anode faults, Fuzzy relation
3	Feng Shi, Yiorgos Makris	Testing delay faults in asynchronous handshake circuits.	ICCAD	2006	DBLP DOI BibTeX RDF	test generation, asynchronous circuits, delay faults, handshake circuits
3	David Walker, Lester W. Mackey, Jay Ligatti, George A. Reis, David I. August	Static typing for a faulty lambda calculus.	ICFP	2006	DBLP DOI BibTeX RDF	transient hardware faults, fault tolerance, type systems, lambda calculus, reliable computing, typed intermediate languages, soft faults
3	Muhsen Aljada, Adam Osseiran, Kamal Alameh	Catastrophic and Parametric Fault Modelling for Photonic Systems.	DELTA	2006	DBLP DOI BibTeX RDF	photonic, photonic testing, fault modelling, fault simulation, parametric faults, catastrophic faults
3	Thomas J. Ostrand, Elaine J. Weyuker, Robert M. Bell	Predicting the Location and Number of Faults in Large Software Systems.	IEEE Trans. Software Eng.	2005	DBLP DOI BibTeX RDF	software testing, prediction, empirical study, Software faults, regression model, fault-prone
3	Simone Borri, Magali Bastian Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel	Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	address decoders, core-cells, memory testing, dynamic faults
3	Carlos Arthur Lang Lisbôa, Erik Schüler, Luigi Carro	Going beyond TMR for protection against multiple faults.	SBCCI	2005	DBLP DOI BibTeX RDF	future technologies, simultaneous transient faults, fault tolerance, design techniques
3	Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas	Low power test generation for path delay faults using stability functions.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, ATPG, path delay faults
3	Okuthe P. Kogeda, Johnson I. Agbinya, Christian W. Omlin	Impacts and Cost of Faults on Services in Cellular Networks.	ICMB	2005	DBLP DOI BibTeX RDF	ERDs, level of Service Agreement (SLA), QoS, models, UML, databases, services, costs, faults, OSS, ESPs