Search results for "field programmable gate arrays"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Bradly K. Fawcett, J. Watson	Reconfigurable Processing With Field Programmable Gate Arrays.	ASAP	1996	DBLP DOI BibTeX RDF	reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays
4	Wei-Kang Huang, Fabrizio Lombardi	An approach for testing programmable/configurable field programmable gate arrays.	VTS	1996	DBLP DOI BibTeX RDF	behavioral characterization, single fault detection, disjoint one-dimensional arrays, unilateral horizontal connections, common vertical input lines, array testing, logic blocks, field programmable gate arrays, field programmable gate arrays, VLSI, logic testing, integrated circuit testing, stuck-at fault, FPGA testing, functional fault, hybrid fault model
3	Yee Jern Chong, Sri Parameswaran	Flexible multi-mode embedded floating-point unit for field programmable gate arrays.	FPGA	2009	DBLP DOI BibTeX RDF	dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture
3	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
3	Arifur Rahman, Vijay Polavarapuv	Evaluation of low-leakage design techniques for field programmable gate arrays.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, leakage power, multiplexer
3	Amit Chowdhary, John P. Hayes	General technology mapping for field-programmable gate arrays based on lookup tables.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	lookup tables (LUTs), multiple-LUT blocks, nonrooted trees, field-programmable gate arrays, mapping, synthesis, circuit partitioning, rooted trees, Basis
3	Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi	CODA-R: a reconfigurable testbed for real-time parallel computation.	RTCSA	1997	DBLP DOI BibTeX RDF	CODA-R, reconfigurable testbed, real-time parallel computation, reconfigurable field programmable gate arrays, total execution time, prototype reconfigurable real-time parallel system, real-time parallel architecture, field programmable gate arrays, real-time system, processing elements, computing engine
3	Joseph L. Ganley, James P. Cohoon	Thumbnail rectilinear Steiner trees.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	full-set decomposition algorithm, minimum-length set, thumbnail rectilinear Steiner tree problem, VLSI placement algorithms, geometric partitioning, field programmable gate arrays, field-programmable gate arrays, VLSI, dynamic programming, network topology, logic CAD, trees (mathematics), network routing, circuit layout CAD, global routing, line segments
3	Jae-Tack Yoo, Erik Brunvand, Kent F. Smith	Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
3	John Schewel, Michael Thornburg, Steve Casselman	Transformable computers & hardware object technology. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	transformable computers, hardware object technology, reconfigurable aspects, computationally intensive software algorithms, on-the-fly use, field programmable gate arrays, field programmable gate arrays, programming, reconfigurable architectures, programmable logic arrays, hardware design, performance gain
2	Abdullah Nazma Nowroz, Sherief Reda	Thermal and power characterization of field-programmable gate arrays.	FPGA	2011	DBLP DOI BibTeX RDF
2	Kristian Stevens, Henry Chen, Terry Filiba, Peter McMahon, Yun S. Song	Application of a reconfigurable computing cluster to ultra high throughput genome resequencing (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	genome resequencing, fpga, acceleration, reconfigurable logic
2	David L. Foster, Darrin M. Hanna	Maximizing area-constrained partial fault tolerance in reconfigurable logic.	FPGA	2010	DBLP DOI BibTeX RDF	area-constrained, FPGA
2	Chen Chen, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Efficient FPGAs using nanoelectromechanical relays.	FPGA	2010	DBLP DOI BibTeX RDF	CMOS-NEM FPGA, nanoelectromechanical relay
2	Hoang Le, Yi-Hua E. Yang, Viktor K. Prasanna	Memory efficient string matching: a modular approach on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	deep packet classification, fpga, packet filtering
2	Kuen Hung Tsoi, Wayne Luk	Axel: a heterogeneous cluster with FPGAs and GPUs.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, heterogeneous cluster
2	Jason Helge Anderson, Chirag Ravishankar	FPGA power reduction by guarded evaluation.	FPGA	2010	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
2	Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris	Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	spin-torque devices, fpga, spintronics
2	Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain	Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, dynamic programming, systolic array, throughput optimization, recurrences
2	Philippa Conmy, Iain Bate	Semi-Automated Safety Analysis for Field Programmable Gate Arrays.	ECBS	2009	DBLP DOI BibTeX RDF
2	David Sheldon, Frank Vahid	Making good points: application-specific pareto-point generation for design space exploration using statistical methods.	FPGA	2009	DBLP DOI BibTeX RDF	configurable platform, fpga, low-power, exploration, speedup, pruning, pareto-optimal, design of experiments
2	Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang	A comparison of via-programmable gate array logic cell circuits.	FPGA	2009	DBLP DOI BibTeX RDF	logic cell, via-programmable gate arrays
2	Roto Le, Sherief Reda, R. Iris Bahar	High-performance, cost-effective heterogeneous 3D FPGA architectures.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, heterogeneous, 3d ic, switch box, through silicon via
2	Antonino Tumeo, Christian Pilato, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	HW/SW methodologies for synchronization in FPGA multiprocessors.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, synchronization, multiprocessors
2	Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck, Wendy McDougald, Don Dewitt	FPGA-based front-end electronics for positron emission tomography.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, localization, timing, positron emission tomography
2	Shinya Kubota, Minoru Watanabe	A nine-context programmable optically reconfigurable gate array with semiconductor lasers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	holographic memory, optically reconfigurable gate arrays, field programmable gate arrays
2	Theepan Moorthy, Andy Ye	A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays.	FPL	2008	DBLP DOI BibTeX RDF
2	James W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. Bennington	Creating unique identifiers on field programmable gate arrays using natural processing variations.	FPL	2008	DBLP DOI BibTeX RDF
2	Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal	Architecture-specific packing for virtex-5 FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, performance, FPGAs, field-programmable gate arrays, power, placement, packing
2	Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck	Fpga-based data acquisition system for a positron emission tomography (PET) scanner.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, positron emission tomography
2	Ian Kuon, Jonathan Rose	Area and delay trade-offs in the circuit and architecture design of FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, FPGA, architecture
2	Tarek A. El-Ghazawi, Esam El-Araby, Miaoqing Huang, Kris Gaj, Volodymyr V. Kindratenko, Duncan A. Buell	The Promise of High-Performance Reconfigurable Computing.	IEEE Computer	2008	DBLP DOI BibTeX RDF	HPRC systems, field-programmable gate arrays, high-performance computing, reconfigurable computing
2	Jin Hwan Park, H. K. Dai	Reconfigurable hardware solution to parallel prefix computation.	The Journal of Supercomputing	2008	DBLP DOI BibTeX RDF	Parallel prefix computation, Field-programmable gate arrays, Pipeline, Dataflow, Reconfigurable hardware
2	Scott Miller, Mihai Sima, Michael McGuire	Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays.	DSD	2007	DBLP DOI BibTeX RDF
2	Nathan Woods	Integrating FPGAs in high-performance computing: the architecture and implementation perspective.	FPGA	2007	DBLP DOI BibTeX RDF	compute acceleration, high-performance computinghigh-performance computing, reconfigurable computing, co-processor
2	Kevin Oo Tinmaung, David Howland, Russell Tessier	Power-aware FPGA logic synthesis using binary decision diagrams.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, binary decision diagram, dynamic power
2	N. Pete Sedcole, Peter Y. K. Cheung	Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis.	FPGA	2007	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modelling, FPGA, delay, reconfiguration, process variation, yield
2	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton	GlitchLess: an active glitch minimization technique for FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	field-programmable gate arrays, power minimization
2	Adam Handzlik, Andrzej Jablonski	"Chameleon" Software Defined Control Platform.	EUROCAST	2007	DBLP DOI BibTeX RDF	Signal processing architectures, control platform development, innovative reprogrammable technology, virtual Programmable Logic Controller, Field Programmable Gate Arrays, IP Core
2	Julien Lamoureux, Steven J. E. Wilton	Activity Estimation for Field-Programmable Gate Arrays.	FPL	2006	DBLP DOI BibTeX RDF
2	Tim Tuan, Sean Kao, Ahmad Arif Rahman, Satyaki Das, Steven Trimberger	A 90nm low-power FPGA for battery-powered applications.	FPGA	2006	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, programmable logic
2	Ronald Scrofano, Viktor K. Prasanna	A Performance model for accelerating scientific applications on reconfigurable computers.	FPGA	2006	DBLP DOI BibTeX RDF
2	Young H. Cho, James Moscola, John W. Lockwood	Context-free-grammar based token tagger in reconfigurable devices.	FPGA	2006	DBLP DOI BibTeX RDF
2	Julien Lamoureux, Steven J. E. Wilton	FPGA clock network architecture: flexibility vs. area and power.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, architecture, low-power, clock network
2	Rajagopal Subramaniyan, Ian A. Troxel, Alan D. George, Melissa C. Smith	Simulative analysis of dynamic scheduling heuristics for reconfigurable computing of parallel applications.	FPGA	2006	DBLP DOI BibTeX RDF
2	Nathaniel Couture, Kenneth B. Kent	Periodic licensing of FPGA based intellectual property.	FPGA	2006	DBLP DOI BibTeX RDF
2	Ahmad Darabiha, W. James MacLean, Jonathan Rose	Reconfigurable hardware implementation of a phase-correlation stereoalgorithm.	Mach. Vis. Appl.	2006	DBLP DOI BibTeX RDF	Stereo disparity estimation, Frame rate implementation, Reconfigurable hardware implementation, Field Programmable Gate Arrays (FPGAs), Phase correlation
2	Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong	Power modeling and characteristics of field programmable gate arrays.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Amit Chowdhary, John P. Hayes	Area-optimal technology mapping for field-programmable gate arrays based on lookup tables.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Stéphane Simard, Rachid Beguenane, Éric Larouche, Luc Morin	A 2005 review of FPGA arithmetic (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
2	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	Exploration of heterogeneous reconfigurable architectures (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
2	Andy Gean Ye, Jonathan Rose	Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits.	FPGA	2005	DBLP DOI BibTeX RDF	datapath regularity, reconfigurable fabric, FPGA architecture, routing architecture, area efficiency
2	Sai Gopalan, Gayathri Venkataraman, Sabu Emmanuel	FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF	cluster maintenance algorithm, VHDL (Very High Speed Integrated Circuit Hardware Description Language), FPGA (Field Programmable Gate Arrays), Mobile ad-hoc networks
2	Geoffrey Wall, Faizal Iqbal, Jason C. Isaacs, Xiuwen Liu, Simon Y. Foo	Real Time Texture Classification using Field Programmable Gate Arrays.	AIPR	2004	DBLP DOI BibTeX RDF
2	Ganesh K. Venayagamoorthy, Venu G. Gudise	Swarm Intelligence for Digital Circuits Implementation on Field Programmable Gate Arrays Platforms.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
2	Jason Helge Anderson, Farid N. Najm, Tim Tuan	Active leakage power optimization for FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF	optimization, FPGAs, field-programmable gate arrays, low-power design, power, leakage
2	A. Manoj Kumar, B. Jayaram, V. Kamakoti	SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis.	FPGA	2004	DBLP DOI BibTeX RDF
2	Sashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-Ghazawi	Implementation of elliptic curve cryptosystems over GF(2n) in optimal normal basis on a reconfigurable computer.	FPGA	2004	DBLP DOI BibTeX RDF
2	Paul Kohlbrenner, Kris Gaj	An embedded true random number generator for FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF	TRNG, FPGA, random numbers, RNG, cryptographic
2	Abderrahim Doumar, Hideo Ito	Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
2	Arifur Rahman, Shamik Das, Anantha P. Chandrakasan, Rafael Reif	Wiring requirement and three-dimensional integration technology for field programmable gate arrays.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
2	L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti	Testable Clock Routing Architecture for Field Programmable Gate Arrays.	FPL	2003	DBLP DOI BibTeX RDF
2	Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti	A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays.	IPDPS	2003	DBLP DOI BibTeX RDF
2	Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou	A physical retiming algorithm for field programmable gate arrays.	FPGA	2003	DBLP DOI BibTeX RDF
2	Pak K. Chan, Martine D. F. Schlag	Parallel placement for field-programmable gate arrays.	FPGA	2003	DBLP DOI BibTeX RDF	parallel placement, FPGAs, timing-driven placement, analytical placement
2	Zhibin Dai, Dilip K. Banerji	Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy.	VLSI Design	2003	DBLP DOI BibTeX RDF
2	Miron Abramovici, Charles E. Stroud	BIST-Based Delay-Fault Testing in FPGAs.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	Field Programmable Gate Arrays, Built-In Self-Test, delay faults
2	Deshanand P. Singh, Stephen Dean Brown	Integrated retiming and placement for field programmable gate arrays.	FPGA	2002	DBLP DOI BibTeX RDF
2	Monica Alderighi, Fabio Casini, Sergio D'Angelo, Davide Salvi, Giacomo R. Sechi	A Fault-Tolerant FPGA-based Multi-Stage Interconnection Network for Space Applications.	DELTA	2002	DBLP DOI BibTeX RDF	Fault Tolerance, Field programmable Gate Arrays, Multistage Interconnection Network, Space Applications
2	Tom Kean	Secure Configuration of Field Programmable Gate Arrays.	FPL	2001	DBLP DOI BibTeX RDF
2	Arifur Rahman, Shamik Das, Anantha Chandrakasan, Rafael Reif	Wiring requirement and three-dimensional integration of field-programmable gate arrays.	SLIP	2001	DBLP DOI BibTeX RDF	3-D integrated circuits, FPGA, system-level modeling, wire-length
2	Kris Gaj, Pawel Chodowiec	Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays.	CT-RSA	2001	DBLP DOI BibTeX RDF
2	Andreas Jakoby, Christian Schindelhauer	Efficient Addition on Field Programmable Gate Arrays.	FSTTCS	2001	DBLP DOI BibTeX RDF
2	Jason Cong, Hui Huang 0001	Depth optimal incremental mapping for field programmable gate arrays.	DAC	2000	DBLP DOI BibTeX RDF
2	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF
2	N. R. Shnidman, William H. Mangione-Smith, Miodrag Potkonjak	On-line fault detection for bus-based field programmable gate arrays.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
2	Peichen Pan, C. L. Liu	Optimal clock period FPGA technology mapping for sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, retiming, technology mapping, look-up tables, logic replication, clock period, sequential synthesis
2	Cecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi	Novel Technique for Testing FPGAs.	DATE	1998	DBLP DOI BibTeX RDF	Field Programmable Gate Arrays, testing, reuse, diagnosis
2	Yen-Tai Lai, Ping-Tsung Wang	Hierarchical interconnection structures for field programmable gate arrays.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
2	Donald L. Hung, Antonio Arsgao, Jorge L. Silva, Eduardo Marques, Karl Hillesland	UB1 - a recurrent neural network based parallel machine for solving simultaneous linear equations.	SBRN	1997	DBLP DOI BibTeX RDF	UB1 recurrent neural network, simultaneous linear equation solving, synchronous execution, field programmable gate arrays, real-time systems, parallel machine, systolic array, neural chips, ring topology, neural net architecture
2	Patrick Lysaght, Jon Stockwood	A simulation tool for dynamically reconfigurable field programmable gate arrays.	IEEE Trans. VLSI Syst.	1996	DBLP DOI BibTeX RDF
2	Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto	Universal test complexity of field-programmable gate arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	universal test complexity, arbitrary logic circuits, sequential loading, random access loading, programming schemes, block-sliced loading, configuration memory cells, field programmable gate arrays, field-programmable gate array, computational complexity, fault diagnosis, logic testing, design for testability, fault model, logic CAD, table lookup, look-up tables, automatic test software, C-testable
2	Tong Liu, Wei-Kang Huang, Fabrizio Lombardi	Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays.	FPGA	1995	DBLP DOI BibTeX RDF	constant testability, FPGA, testing, manufacturing
2	Amit Chowdhary, John P. Hayes	Technology mapping for field-programmable gate arrays using integer programming.	ICCAD	1995	DBLP DOI BibTeX RDF	Field-programmable gate arrays (FPGAs), technology mapping, mixed integer linear programming (MILP), lookup tables, circuit partitioning
2	Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois	The Design of RPM: An FPGA-based Multiprocessor Emulator.	FPGA	1995	DBLP DOI BibTeX RDF	field-programmable gate arrays, VHDL, rapid prototyping, shared-memory multiprocessors, logic emulation, message-passing multicomputers
2	Stephen D. Scott, Ashok Samal, Sharad C. Seth	HGA: A Hardware-Based Genetic Algorithm.	FPGA	1995	DBLP DOI BibTeX RDF	performance acceleration, performance evaluation, field programmable gate arrays, function optimization, parallel genetic algorithms
2	Hardy J. Pottinger, Chien-Yuh Lin	Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
2	Yao-Wen Chang, D. F. Wong, C. K. Wong	Design and analysis of FPGA/FPIC switch modules. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	FPGA/FPIC switch modules, routing resources, FPIC, network-flow techniques, field programmable interconnect chip, field programmable gate arrays, FPGA, field programmable gate arrays, logic design, heuristic algorithm, programmable logic arrays, routability
2	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture
2	TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang	Logic synthesis for field-programmable gate arrays.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
2	Barry S. Fagin, C. Renard	Field programmable gate arrays and floating point arithmetic.	IEEE Trans. VLSI Syst.	1994	DBLP DOI BibTeX RDF
2	Neil J. Howard, Andrew M. Tyrrell, Nigel M. Allinson	The yield enhancement of field-programmable gate arrays.	IEEE Trans. VLSI Syst.	1994	DBLP DOI BibTeX RDF
2	Marianne E. Louie, Milos D. Ercegovac	Implementing division with field programmable gate arrays.	VLSI Signal Processing	1994	DBLP DOI BibTeX RDF
2	Marianne E. Louie, Milos D. Ercegovac	On digit-recurrence division implementations for field programmable gate arrays.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
2	Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic	A detailed router for field-programmable gate arrays.	IEEE Trans. on CAD of Integrated Circuits and Systems	1992	DBLP DOI BibTeX RDF
2	Hartmut Surmann, Ansgar Ungering, Karl Goser	Optimized Fuzzy Controller Architecture for Field Programmable Gate Arrays.	FPL	1992	DBLP DOI BibTeX RDF
2	Jouni Isoaho, Arto Nummela, Hannu Tenhunen	Technologies and Utilization fo Field Programmable Gate Arrays.	FPL	1992	DBLP DOI BibTeX RDF
2	Alberto L. Sangiovanni-Vincentelli	Some Considerations on Field-Programmable Gate Arrays and Their Impact on System Design.	FPL	1992	DBLP DOI BibTeX RDF
2	Robert J. Francis, Jonathan Rose, Kevin Chung	Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays.	DAC	1990	DBLP DOI BibTeX RDF
1	Jae Young Hur, Todor Stefanov, Stephan Wong, Kees Goossens	Customisation of on-chip network interconnects and experiments in field-programmable gate arrays.	IET Computers & Digital Techniques	2012	DBLP DOI BibTeX RDF