Search results for "fixed-point arithmetic"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Behzad Akbarpour, Sofiène Tahar, Abdelkader Dekdouk	Formalization of Fixed-Point Arithmetic in HOL.	Formal Methods in System Design	2005	DBLP DOI BibTeX RDF	theorem-proving, floating-point arithmetic, fixed-point arithmetic, HOL
3	T. Y. Tang, Y. S. Moon, K. C. Chan	Efficient implementation of fingerprint verification for mobile embedded systems using fixed-point arithmetic.	SAC	2004	DBLP DOI BibTeX RDF	embedded systems, fingerprint, fixed-point arithmetic
2	Katja Ihsberner	Roundoff error analysis of fast DCT algorithms in fixed point arithmetic.	Numerical Algorithms	2007	DBLP DOI BibTeX RDF	Mathematics Subject Classifications (2000) 65T50, 65G50
2	Javier Díaz, Eduardo Ros, Sonia Mota, Richard R. Carrillo	Image Processing Architecture for Local Features Computation.	ARC	2007	DBLP DOI BibTeX RDF	quadrature filters, local image phase, orientation and energy, Real-time image processing, fixed point arithmetic
2	C. K. Wong, Philip Heng Wai Leong	An FPGA-Based Electronic Cochlea with Dual Fixed-Point Arithmetic.	FPL	2006	DBLP DOI BibTeX RDF
2	Christoph H. Lampert, Oliver Wirjadi	Anisotropic Gaussian Filtering using Fixed Point Arithmetic.	ICIP	2006	DBLP DOI BibTeX RDF
2	Miguel A. Ferrer, Jesús B. Alonso, Carlos M. Travieso	Offline Geometric Parameters for Automatic Signature Verification Using Fixed-Point Arithmetic.	IEEE Trans. Pattern Anal. Mach. Intell.	2005	DBLP DOI BibTeX RDF
2	Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung	Automating custom-precision function evaluation for embedded processors.	CASES	2005	DBLP DOI BibTeX RDF	embedded systems, reconfigurable computing, fixed-point arithmetic, function evaluation
2	Sanghamitra Roy, Prith Banerjee	An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	field programmable gate arrays, Automation, quantization, floating-point arithmetic, fixed-point arithmetic
2	G. Robert Redinbo	Feedback decoding of fixed-point arithmetic convolutional codes.	IEEE Transactions on Communications	2004	DBLP DOI BibTeX RDF
2	James F. Whidborne, J. Mckernan, Da-Wei Gu	Kolmogorov-Chaitin complexity of linear digital controllers implemented using fixed-point arithmetic.	ICARCV	2004	DBLP DOI BibTeX RDF
2	Behzad Akbarpour, Sofiène Tahar	Modeling System C Fixed-Point Arithmetic in HOL.	ICFEM	2003	DBLP DOI BibTeX RDF
2	G. Robert Redinbo	Failure-Detecting Arithmetic Convolutional Codes and an Iterative Correcting Strategy.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	convolutional codes over integers, free modules, burst-correcting codes, real number codes, Algorithm-based fault tolerance, iterative decoding, fixed-point arithmetic, syndrome decoding
2	Behzad Akbarpour, Abdelkader Dekdouk, Sofiène Tahar	Formalization of Cadence SPW Fixed-Point Arithmetic in HOL.	IFM	2002	DBLP DOI BibTeX RDF	SPW, Theorem-Proving, Signal Processing, Floating-point, Fixed-point, HOL
2	Tanja Karp, Alfred Mertins	Implementation of biorthogonal cosine-modulated filter banks with fixed-point arithmetic.	ISCAS	2001	DBLP DOI BibTeX RDF
1	G. Alonzo Vera, Marios S. Pattichis, James Lyke	A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs.	Int. J. Reconfig. Comp.	2011	DBLP DOI BibTeX RDF
1	Nobuyuki Nishizawa, Tsuneo Kato	Accurate parameter generation using fixed-point arithmetic for embedded HMM-based speech synthesizers.	ICASSP	2011	DBLP DOI BibTeX RDF
1	Joaquín Cortez González, Miguel Bazdresch, Deni Torres Román, Erica Ruiz-Ibarra	An Efficient Scheduling Architecture for QR Decomposition Using Fixed-Point Arithmetic for Detection of STBC-VBLAST Codes.	ICCCN	2011	DBLP DOI BibTeX RDF
1	Yu Pang, Katarzyna Radecka	An efficient algorithm of performing range analysis for fixed-point arithmetic circuits based on SAT checking.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Jhing-Fa Wang, Ta-Wen Kuan, Jia-Ching Wang, Ta-Wei Sun	Dynamic Fixed-Point Arithmetic Design of Embedded SVM-Based Speaker Identification System.	ISNN	2010	DBLP DOI BibTeX RDF
1	Gabor Ferencz, Eric Peskin, Charles Peskin	Accuracy of the Immersed Boundary Method in Fixed-Point Arithmetic.	CSC	2010	DBLP BibTeX RDF
1	Xiang Tian, Khaled Benkrid	Fixed-Point Arithmetic Error Estimation in Monte-Carlo Simulations.	ReConFig	2010	DBLP DOI BibTeX RDF
1	O. Sarbishei, Katarzyna Radecka	Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Octavian Catrina, Sebastiaan de Hoogh	Secure Multiparty Linear Programming Using Fixed-Point Arithmetic.	ESORICS	2010	DBLP DOI BibTeX RDF
1	Karthick Parashar, Romuald Rocher, Daniel Menard, Olivier Sentieys	A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems.	VLSI Design	2010	DBLP DOI BibTeX RDF	Wordlength Optimization, Quantization Noise, System, Roundoff errors, Fixed point arithmetic
1	Abdul-Rahman Elshafei, Azzedine Zerguine, Abdelhafid Bouhraoua	Scalable FPGA implementation for mixed-norm LMS-LMF adaptive filters.	IWCMC	2009	DBLP DOI BibTeX RDF	LMS-LMF, FPGA, adaptive filters, scalable architecture
1	Linsheng Zhang, Yan Zhang, Wenbiao Zhou	Floating-point to Fixed-point Transformation Using Extreme Value Theory.	ACIS-ICIS	2009	DBLP DOI BibTeX RDF
1	J. Manikandan, B. Venkataramani, V. Avanthi	FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Brent E. Nelson	FPGA Design Productivity - A Discussion of the State of the Art and a Research Agenda.	ARC	2009	DBLP DOI BibTeX RDF
1	Rodrigo Martins da Silva, Nadia Nedjah, Luiza de Macedo Mourelle	Reconfigurable MAC-Based Architecture for Parallel Hardware Implementation on FPGAs of Artificial Neural Networks Using Fractional Fixed Point Representation.	ICANN	2009	DBLP DOI BibTeX RDF
1	Yu Pang, Katarzyna Radecka	Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform.	DAC	2008	DBLP DOI BibTeX RDF	DSP circuit synthesis, optimization, error analysis, Taylor Series
1	Constantin Paleologu, Felix Albu, Andrei Alexandru Enescu, Silviu Ciochina	Square-Root-Free QRD-LSL Adaptive Algorithm with Improved Numerical Robustness.	ICN	2008	DBLP DOI BibTeX RDF	QR-decomposition-based least-squares lattice (QRD-LSL), Adaptive filters, logarithmic number system (LNS), fixed-point arithmetic
1	Ernesto Ordoñez-Cardenas, René de Jesús Romero-Troncoso	Mlp neural network and on-line backpropagation learning implementation in a low-cost fpga.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	backpropagation learning, low-cost FPGA, neural network
1	Ulrich Freund	Mulit-level system integration based on AUTOSAR.	ICSE	2008	DBLP DOI BibTeX RDF	rapid prototyping, embedded software, automotive, automatic code-generation
1	Yoshihide Hosokawa	A location-aware information browser implemented on BREW-based mobile phones.	SAC	2008	DBLP DOI BibTeX RDF	user interface, mobile computing, location-awareness
1	Yee-Pien Yang, Xian-Yee Xing	Design of electric differential system for an electric vehicle with dual wheel motors.	CDC	2008	DBLP DOI BibTeX RDF
1	Hauke Krüger, Peter Vary	RTPROC: A System for Rapid Real-Time Prototyping in Audio Signal Processing.	DS-RT	2008	DBLP DOI BibTeX RDF
1	Xin Jin, Stephen B. Furber, John V. Woods	Efficient modelling of spiking neural networks on a scalable chip multiprocessor.	IJCNN	2008	DBLP DOI BibTeX RDF
1	Lei Ma, Kevin Dickson, John McAllister, John V. McCanny, Mathini Sellathurai	Reduced-complexity MSGR-based matrix inversion.	SiPS	2008	DBLP DOI BibTeX RDF
1	M. G. Buddika Sumanasena	A Scale Factor Correction Scheme for the CORDIC Algorithm.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
1	J. Gomes, V. A. N. Barroso	Array-Based QR-RLS Multichannel Lattice Filtering.	IEEE Transactions on Signal Processing	2008	DBLP DOI BibTeX RDF
1	Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope	Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models.	ARC	2008	DBLP DOI BibTeX RDF
1	Sung-Uk Jung, Yun-Su Chung, Jang-Hee Yoo, Ki-Young Moon	Real-Time Face Verification for Mobile Platforms.	ISVC	2008	DBLP DOI BibTeX RDF	Face Component Detection, Face Recognition, Mobile Platform
1	Dimitrios E. Maroulis, Dimitrios K. Iakovidis, Dimitris G. Bariamis	FPGA-based System for Real-Time Video Texture Analysis.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	Field programmable gate arrays, Pattern recognition, Real-time system, Parallel architectures, Video signal processing
1	Earl E. Swartzlander Jr.	Systolic FFT Processors: A Personal Perspective.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	systolic systems, frequency domain adaptive digital filters, systolic FFT, fast fourier transforms
1	Miwa Miyata, Yuichiro Shibata, Kiyoshi Oguri	An optimization method focusing on fixed-point arithmetic in applications for dynamically reconfigurable processor.	Systems and Computers in Japan	2007	DBLP DOI BibTeX RDF
1	Yevgen Voronenko, Markus Püschel	Multiplierless multiple constant multiplication.	ACM Transactions on Algorithms	2007	DBLP DOI BibTeX RDF	directed graph, FIR filter, Addition chains, fixed-point arithmetic, strength reduction
1	Mihai Sima, Michael McGuire	Embedded Reconfigurable Solution for OFDM Detection Over Fast Fading Radio Channels.	SiPS	2007	DBLP DOI BibTeX RDF
1	Martin J. Pearson, Anthony G. Pipe, Benjamin Mitchinson, Kevin N. Gurney, Chris Melhuish, Ian Gilhespy, Mokhtar Nibouche	Implementing Spiking Neural Networks for Real-Time Signal-Processing and Control Applications: A Model-Validated FPGA Approach.	IEEE Transactions on Neural Networks	2007	DBLP DOI BibTeX RDF
1	Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Architectures for efficient face authentication in embedded systems.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
1	Andreas Raabe, Stefan Hochgürtel, Joachim K. Anlauf, Gabriel Zachmann	Space-efficient FPGA-accelerated collision detection for virtual prototyping.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
1	Elie H. Sarraf, Messaoud Ahmed-Ouameur, Daniel Massicotte	FPGA Implementation of Beamforming Receivers Based on MRC and NC-LMS for DS-CDMA System.	ASAP	2006	DBLP DOI BibTeX RDF
1	Earl E. Swartzlander Jr.	Systolic FFT Processors: Past, Present and Future.	ASAP	2006	DBLP DOI BibTeX RDF
1	Miwa Miyata, Hideyuki Tsuchiya, Yuichiro Shibata, Kiyoshi Oguri	An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable Processor.	FPL	2006	DBLP DOI BibTeX RDF
1	Stéphane Mancini, Michel Desvignes	Ray Casting on a SOPC : Algorithm and Memory Hierarchy Trade-Off.	CIT	2006	DBLP DOI BibTeX RDF
1	Romuald Rocher, Nicolas Hervé, Daniel Menard, Olivier Sentieys	Fixed-point configurable hardware components for adaptive filters.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Davide Anguita, Stefano Pischiutta, Sandro Ridella, Dario Sterpi	Feed-Forward Support Vector Machine Without Multipliers.	IEEE Transactions on Neural Networks	2006	DBLP DOI BibTeX RDF
1	Dongwuk Kyoung, Keechul Jung	Fully-Pipelining Hardware Implementation of Neural Network for Text-Based Images Retrieval.	ISNN	2006	DBLP DOI BibTeX RDF
1	Ebrahim Saberinia, K. C. Chang, Gerald E. Sobelman, Ahmed H. Tewfik	Implementation of a Multi-band Pulsed-OFDM Transceiver.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF
1	Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides	Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic.	FPL	2005	DBLP BibTeX RDF
1	Chee Kiat Ng, Marios Savvides, Pradeep K. Khosla	Real-Time Face Verification System on a Cell-Phone Using Advanced Correlation Filters.	AutoID	2005	DBLP DOI BibTeX RDF	minimum average correlation energy (MACE), face recogntion, face verification, fixed-point arithmetic, Correlation filters
1	Miriam Leeser, Srdjan Coric, Eric L. Miller, Haiqian Yu, Marc Trepanier	Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	FPGA, medical imaging, tomography, fixed point arithmetic, backprojection
1	Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Efficient fingerprint-based user authentication for embedded systems.	DAC	2005	DBLP DOI BibTeX RDF	embedded systems, fingerprint, user authentication, extensible processors
1	Min-wuk Lee, Byeong-Gyu Nam, Ju-Ho Sohn, Namjun Cho, Hyejung Kim, Kwanho Kim, Hoi-Jun Yoo	A fixed-point 3D graphics library with energy-efficient cache architecture for mobile multimedia systems.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Miriam Primbs	Worst-case error analysis of lifting-based fast DCT-algorithms.	IEEE Transactions on Signal Processing	2005	DBLP DOI BibTeX RDF
1	Changchun Shi, Robert W. Brodersen	Automated fixed-point data-type optimization tool for signal processing and communication systems.	DAC	2004	DBLP DOI BibTeX RDF	optimization, FPGA, digital signal processing, ASIC, communication systems, fixed-point arithmetic
1	Sanghamitra Roy, Prithviraj Banerjee	An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design.	DAC	2004	DBLP DOI BibTeX RDF	quantization, quantizer, floating point, fixed point
1	Wang Chen, Panos Kosmas, Miriam Leeser, Carey M. Rappaport	An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm.	FPGA	2004	DBLP DOI BibTeX RDF	finite-difference time-domain, FPGA, hardware acceleration, hardware implementation, FDTD
1	Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee	An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design.	FPGA	2004	DBLP DOI BibTeX RDF
1	Daniel Ferrer, Ramiro González, Roberto Fleitas, Julio Pérez Acle, Rafael Canetti	NeuroFPGA - Implementing Artificial Neural Networks on Programmable Logic Devices.	DATE	2004	DBLP DOI BibTeX RDF
1	Jinfei Xie, Wei-Yong Yan	Stability robustness analysis of digital control systems.	ICARCV	2004	DBLP DOI BibTeX RDF
1	J. S. Chen, Y. S. Moon, K. F. Fong	Efficient Fingerprint Image Enhancement for Mobile Embedded Systems.	ECCV Workshop BioAW	2004	DBLP DOI BibTeX RDF
1	Daniel Menard, Olivier Sentieys	DSP Code Generation with Optimized Data Word-Length Selection.	SCOPES	2004	DBLP DOI BibTeX RDF
1	Ramón Mollá Vayá, P. Jorquera, Roberto Vivó	Fixed-Point Arithmetic Line Clipping.	WSCG	2003	DBLP BibTeX RDF
1	Mark G. Arnold, Thomas A. Bailey, John R. Cowles, Colin D. Walter	Fast Fourier Transforms Using the Complex Logarithmic Number System.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	Fast Fourier Transform (FFT), addition, logarithmic number system (LNS), fixed-point arithmetic, complex numbers, polar coordinates
1	Artur Krukowski, Izzet Kale	Polyphase IIR filter banks for subband adaptive echo cancellation applications.	ISCAS	2003	DBLP DOI BibTeX RDF
1	R. Thamvichai, Tamal Bose, Milena Radenkovic	Fast Integer Fourier Transform (FIFT) based on lifting matrices.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Andrew Y. Lin, Karl S. Gugel, José Carlos Príncipe	Feasibility of Fixed-Point Transversal Adaptive Filters in FPGA Devices with Embedded DSP Blocks.	IWSOC	2003	DBLP DOI BibTeX RDF
1	Vijay P. Shah, Anthony Skjellum, Nicolas H. Younan, Torey Alford, D. Whitcomb, A. Watkins	inAspect: interfacing Java and VSIPL.	Java Grande	2002	DBLP DOI BibTeX RDF	VSIPL, embedded Java, image processing, signal processing, high-performance, linear algebra, fixed-point arithmetic, multi-platform, JNI
1	Frank Livingston, Vikram Chandrasekhar, M. Vaya, Joseph R. Cavallaro	Handset detector architectures for DS-CDMA wireless systems.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Manuel L. Anido, Nader Bagherzadeh, Nozar Tabrizi, Haitao Du, Marcos Sanchez-Elez	Interactive Ray Tracing Using a SIMD Reconfigurable Architecture.	SBAC-PAD	2002	DBLP DOI BibTeX RDF
1	Yingtao Jiang, Yuke Wang, Edwin Hsing-Mean Sha	Distributed Scaling Algorithm for FFT Computation Using Fixed-Point Arithmetic.	ISCA PDCS	2001	DBLP BibTeX RDF
1	Peter Stephenson, Bruce E. Litow	Making the DDA Run: Two-Dimensional Ray Traversal Using Runs and Runs of Runs.	ACSC	2001	DBLP DOI BibTeX RDF	line digitisation, ray traversal, volume visualisation, ray tracing, Digital geometry
1	Keun-Sup Lee, Hyen-O Oh, Young-Cheol Park, Dae Hee Youn	High quality MPEG-audio layer III algorithm for a 16-bit DSP.	ISCAS	2001	DBLP DOI BibTeX RDF
1	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk	Multiple Precision for Resource Minimization.	FCCM	2000	DBLP DOI BibTeX RDF
1	Alberto L. Sangiovanni-Vincentelli, Marco Re, Luciano Lavagno, Gian-Carlo Cardarilli, Roberto Lojacono	Analysis of the quantization noise effects on the SQNR behaviour in analog to digital conversion.	ISCAS	1999	DBLP DOI BibTeX RDF
1	P. Szabe	VLSI implementation of minimum order state-space structures for adaptive digital filters.	KES	1999	DBLP DOI BibTeX RDF
1	Harald Wüst, Klaus Kasper, Herbert Reininger	Hybrid Number Representation for the FPGA-Realization of a Versatile Neuro-Processor.	EUROMICRO	1998	DBLP DOI BibTeX RDF
1	Paolo Ienne, Marc A. Viredaz	GENES IV: A bit-serial processing element for a multi-model neural-network accelerator.	VLSI Signal Processing	1995	DBLP DOI BibTeX RDF
1	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Digit pipelined arithmetic on fine-grain array processors.	VLSI Signal Processing	1995	DBLP DOI BibTeX RDF
1	Louis-Jérôme Leclerc, Peter H. Bauer	New criteria for asymptotic stability of one- and multidimensional state-space digital filters in fixed-point arithmetic.	IEEE Transactions on Signal Processing	1994	DBLP DOI BibTeX RDF
1	Kamal Premaratne, Peter H. Bauer	Limit Cycles and Asymptotic Stability of Delta-Operator Formulated Discrete-Time Systems in Fixed-Point Arithmetic.	ISCAS	1994	DBLP BibTeX RDF
1	Gui Liang Feng, T. R. N. Rao, Mahadev S. Kolluru	Error Correcting Codes over Z_{2^m} for Algorithm Based Fault Tolerance.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	low-cost error protection, real-time digital signal processing, encoding data, error correction codes, error correcting codes, encoding, decoding, algorithm-based fault tolerance, fixed-point arithmetic
1	Naoki Mikami, Masaki Kobayashi, Yukiko Yokoyama	Roundoff-error reduction for evaluation of a function by polynomial approximation with error feedback in fixed-point arithmetic.	IEEE Transactions on Signal Processing	1993	DBLP DOI BibTeX RDF
1	Shotaro Nishimura	A steady-state analysis of adaptive notch filters realized with fixed-point arithmetic.	ISCAS	1993	DBLP BibTeX RDF
1	Stamatis Vassiliadis, James Phillips, Bart Blaner	Interlock Collapsing ALU's.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	interlocked fixed point arithmetic logic unit, unsigned binary, binary logical operations, single instruction execution, machine cycle, architectural compatibility, parallel processing, digital arithmetic, adders, CMOS integrated circuits, CMOS technology, carry-save adder, carry-lookahead adder, two's complement
1	Krste Asanovic, Nelson Morgan, John Wawrzynek	Using simulations of reduced precision arithmetic to design a neuro-microprocessor.	VLSI Signal Processing	1993	DBLP DOI BibTeX RDF
1	Chintana Griffin, Preeti Rao, Fred Taylor	Roundoff error analysis of the discrete Wigner distribution using fixed-point arithmetic.	IEEE Transactions on Signal Processing	1991	DBLP DOI BibTeX RDF
1	Dan Field	Incremental Linear Interpolation.	ACM Trans. Graph.	1985	DBLP DOI BibTeX RDF