Search results for "flipflops"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Hans-Georg Martin	Retiming for Circuits with Enable Registers.	EUROMICRO	1996	DBLP DOI BibTeX RDF	enable registers, circuit retiming, combinational paths, D-Flipflops, retiming algorithm, sequential elements, high level synthesis, high level synthesis, digital circuits
1	Ning Chen, Bing Li, Ulf Schlichtmann	Timing Modeling of Flipflops Considering Aging Effects.	PATMOS	2011	DBLP DOI BibTeX RDF
1	Hiroki Sunagawa, Hidetoshi Onodera	Variation-tolerant design of D-flipflops.	SoCC	2010	DBLP DOI BibTeX RDF
1	Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita	Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	overclocking, timing error detection, timing error recovery, fpga
1	Flavio Carbognani, Luca Henzen	Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking.	ISLPED	2009	DBLP DOI BibTeX RDF	flipflops, low power design, clock, digital circuits, adiabatic
1	Dong Xiang, Mingjing Chen, Jia-Guang Sun	Scan BIST with biased scan test signals.	Science in China Series F: Information Sciences	2008	DBLP DOI BibTeX RDF	random testability, test signal, biased random testing, scan-based BIST
1	Ganesh Venkataraman, Jiang Hu	A Placement Methodology for Robust Clocking.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Sanjay Burman, Debdeep Mukhopadhyay, Kamakoti Veezhinathan	LFSR Based Stream Ciphers Are Vulnerable to Power Attacks.	INDOCRYPT	2007	DBLP DOI BibTeX RDF	Linear Feed Back Shift Registers, Dynamic Power Dissipation, Side Channel Attacks, Power Analysis, Hamming Distance
1	Rajeev R. Rao, David Blaauw, Dennis Sylvester	Soft error reduction in combinational logic using gate resizing and flipflop selection.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Kentaroh Katoh, Hideo Ito	Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices.	European Test Symposium	2006	DBLP DOI BibTeX RDF	Coarse Grained Dynamically Reconfigurable Devices, DRP, BIST(Built-In Self Test), PE, DFT
1	Vivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester	Logic SER Reduction through Flipflop Redesign.	ISQED	2006	DBLP DOI BibTeX RDF
1	Hans-Dieter Wohlmuth, Daniel Kehrer	A 24 GHz dual-modulus prescaler in 90nm CMOS.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Mario R. Casu, Luca Macchiarulo	Floorplanning for throughput.	ISPD	2004	DBLP DOI BibTeX RDF	systems-on-chip, throughput, floorplanning, wire pipelining
1	Gundolf Kiefer, Hans-Joachim Wunderlich	Deterministic BIST with Partial Scan.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	deterministic scan-based BIST, partial scan
1	Jason Cong, Chang Wu	FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits.	DAC	1997	DBLP DOI BibTeX RDF
1	Sybille Hellebrand, Hans-Joachim Wunderlich	An efficient procedure for the synthesis of fast self-testable controller structures.	ICCAD	1994	DBLP DOI BibTeX RDF
1	Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal	The optimistic update theorem for path delay testing in sequential circuits.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	test generation, Fault simulation, timing analysis, path delay faults
1	Hyoung B. Min, William A. Rogers	A test methodology for finite state machines using partial scan design.	J. Electronic Testing	1992	DBLP DOI BibTeX RDF	loop-free circuits, test generation, ATPG, fault, partial scan
1	Arno Kunzmann, Hans-Joachim Wunderlich	An analytical approach to the partial scan problem.	J. Electronic Testing	1990	DBLP DOI BibTeX RDF	partial scan path, sequential test generation, design for testability
1	Winfried Hahn, Kristian Fischer	MuSiC: an event-flow computer for fast simulation of digital systems.	DAC	1985	DBLP DOI BibTeX RDF
1	Klaus Lagemann	Ein Vorschlag zur Darstellung asynchron betriebener JK-Flipflops.	Elektronische Rechenanlagen	1968	DBLP BibTeX RDF