Search results for "floating-point"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
7	David W. Matula, Asger Munk Nielsen	Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, packet forwarding floating point format, rounder design, packet forwarding format, standard binary IEEE 754 floating point format, multiplication algorithms, ALU pipeline paradigm, data hazards, pipelined floating point operations, execution phases, multiplier packet forwarding pipelines, execution phase, logic levels, multiplier pipelines, forwarding pipelines, IEEE 754 binary floating point compatibility, pipeline arithmetic, data dependent operations
7	Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even	Pipelined Packet-Forwarding Floating Point: II. An Adder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, floating point addition algorithm, adder pipeline design, packet forwarding pipeline paradigm, data hazards, deeply pipelined floating point pipelines, four stage execution phase pipeline, short clock period, fifteen logic levels, addition algorithm, standard binary floating point format, standard IEEE 754 rounded result, two cycle latency, cooperating multiplier pipeline, packet forwarding operand, IEEE 754 binary floating point compatibility, pipeline arithmetic
5	Guy Even, Wolfgang J. Paul	On the Design of IEEE Compliant Floating Point Units.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	floating-point rounding, floating-point arithmetic, IEEE 754 Standard, floating-point addition
5	Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even	An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	IEEE floating-point rounding, Floating-point arithmetic, redundant number representations, floating-point addition
5	H. Yamada, T. Hotta, T. Nishiyama, F. Murabayashi, T. Yamauchi, H. Sawamoto	A 13.3ns double-precision floating-point ALU and multiplier. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	double-precision floating-point ALU, floating-point multiplier, carry select addition, prerounding techniques, noise tolerant precharge circuit, two-cycle latency, 13.3 ns, 0.3 micron, 2.5 V, 150 MHz, normalization, floating point arithmetic, CMOS integrated circuits, multiplying circuits, CMOS technology, arithmetic logic unit
5	Hosahalli R. Srinivas, Keshab K. Parhi	A floating point radix 2 shared division/square root chip. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	floating point radix 2 shared division/square root chip, full-custom 1.2 micron CMOS VLSI chip, single precision IEEE 754 std. floating point numbers, square root algorithm, digit-by-digit schemes, quotient/root digit selection, 5.0 V, 66 MHz, VLSI, floating point arithmetic, CMOS integrated circuits, IEEE standards, dividing circuits, 1.2 micron, division algorithm
5	Geoff Barrett	Formal Methods Applied to a Floating-Point Number System.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	floating-point number system, binary floating-point arithmetic, ANSI/IEEE Std. 754-1985, set-theoretic specification language, sequential components, unpack, operands, proven rules, mathematically rigorous method, Inmos IMS T800 transputer, formal specification, formal methods, specification languages, digital arithmetic, Z, formalization, round, pack, program development, IEEE standard, floating-point unit, internal representations
4	Lance Saldanha, Roman L. Lysecky	Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	floating point to fixed conversion, floating point, fixed point, hardware/software partitioning
4	J. Dido, N. Geraudie, L. Loiseau, O. Payeur, Yvon Savaria, D. Poirier	A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs.	FPGA	2002	DBLP DOI BibTeX RDF	data-path optimization, floating-point/fixed-point conversion, hardware division, hyardware optimization, FPGA, floating-point, video-processing
4	Brigitte Verdonk, Annie A. M. Cuyt, Dennis Verschaeren	A precision- and range-independent tool for testing floating-point arithmetric I: basic operations, square root, and remainder.	ACM Trans. Math. Softw.	2001	DBLP DOI BibTeX RDF	IEEE floating-point standard, multiprecision, validation, floating-point, arithmetic
4	Brigitte Verdonk, Annie A. M. Cuyt, Dennis Verschaeren	A precision- and range-independent tool for testing floating-point arithmetic II: conversions.	ACM Trans. Math. Softw.	2001	DBLP DOI BibTeX RDF	IEEE floating-point standard, multiprecision, validation, conversion, floating-point, arithmetic, decimal
4	Guy Even, Peter-Michael Seidel	A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	floating-point multiplication, IEEE rounding, Floating-point arithmetic, IEEE 754 Standard
4	Guy Even, Wolfgang J. Paul	On the Design of IEEE Compliant Floating Point Units.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	floating point arithmetic, rounding, floating point unit
4	Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens, Amulya K. Garga	Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline.	ASAP	1996	DBLP DOI BibTeX RDF	floating point multiply-accumulate unit, three-dimensional graphics engines, normalized space, virtual reality, virtual reality, parallelism, computer graphics, scientific visualization, matrix multiplication, matrix multiplications, data visualisation, floating point arithmetic, architectural optimizations, graphics pipeline
4	H. Dhanesha, K. Falakshahi, Mark Horowitz	Array-of-arrays architecture for parallel floating point multiplication.	ARVLSI	1995	DBLP DOI BibTeX RDF	array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron
4	Michael J. Flynn, Kevin J. Nowka, Gary Bewick, Eric M. Schwarz, Nhon T. Quach	The SNAP Project: Towards Sub-Nanosecond Arithmetic.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	floating-point multiplication, computer arithmetic, floating-point arithmetic, wave pipelining, floating-point addition
3	Florian Loitsch	Printing floating-point numbers quickly and accurately with integers.	PLDI	2010	DBLP DOI BibTeX RDF	dtoa, floating-point printing
3	Enyi Tang, Earl T. Barr, Xuandong Li, Zhendong Su	Perturbing numerical calculations for statistical analysis of floating-point program (in)stability.	ISSTA	2010	DBLP DOI BibTeX RDF	testing, stability, floating-point, perturbation, numerical code
3	Zhanpeng Jin, Richard Neil Pittman, Alessandro Forin	Reconfigurable custom floating-point instructions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	emips, reconfigurable, extension, floating-point, partial reconfiguration
3	Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo, Jie Zhou, Li Shen	FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing.	ICS	2010	DBLP DOI BibTeX RDF	double-double precision, high precision floating-point multiplication and accumulation (HP-MAC), quad-double precision, FPGA
3	Mustafa Gök, Metin Mete Özbilen	Evaluation of Sticky-Bit Generation Methods for Floating-Point Multipliers.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Floating-point multiplier, Sticky-bit, Rounding
3	Diego F. Sánchez, Daniel M. Muñoz, Carlos H. Llanos, Mauricio Ayala-Rincón	Parameterizable floating-point library for arithmetic operations in FPGAs.	SBCCI	2009	DBLP DOI BibTeX RDF	goldschmidt, FPGA, computer arithmetic, floating-point
3	Yee Jern Chong, Sri Parameswaran	Flexible multi-mode embedded floating-point unit for field programmable gate arrays.	FPGA	2009	DBLP DOI BibTeX RDF	dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture
3	Bowei Zhang, Guochang Gu, Lin Sun, Yanxia Wu	32-bit floating-point FPGA gaussian elimination.	FPGA	2009	DBLP DOI BibTeX RDF	fpga., floating-point, gaussian elimination
3	David Monniaux	The pitfalls of verifying floating-point computations.	ACM Trans. Program. Lang. Syst.	2008	DBLP DOI BibTeX RDF	AMD64, FPU, IA32, x87, Verification, Static analysis, Abstract interpretation, Program testing, Embedded software, Floating point, Safety-Critical Software, Rounding, PowerPC, IEEE-754
3	Yee Jern Chong, Sri Parameswaran	Rapid application specific floating-point unit generation with bit-alignment.	DAC	2008	DBLP DOI BibTeX RDF	bit-alignment, datapath merging, floating-point
3	Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran	When FPGAs are better at floating-point than microprocessors.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, floating-point, arithmetic
3	Jurgen A. Doornik	Conversion of high-period random numbers to floating point.	ACM Trans. Model. Comput. Simul.	2007	DBLP DOI BibTeX RDF	Conversion to floating point, precision
3	Laurent Fousse, Guillaume Hanrot, Vincent Lefèvre, Patrick Pélissier, Paul Zimmermann	MPFR: A multiple-precision binary floating-point library with correct rounding.	ACM Trans. Math. Softw.	2007	DBLP DOI BibTeX RDF	correct rounding, floating-point arithmetic, elementary function, Multiple-precision arithmetic, IEEE 754 standard, portable software
3	Liang-Kai Wang, Michael J. Schulte	A Decimal Floating-Point Divider Using Newton-Raphson Iteration.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	Newton-Raphson iteration, initial approximation, computer arithmetic, floating-point, division, hardware design, decimal
3	Chichyang Chen, Paul Chow	Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	exponential computation, logarithmic computation, logarithmic number system (LNS) arithmetic, floating-point arithmetic
3	Son Dao Trong, Martin S. Schmookler, Eric M. Schwarz, Michael Kroener	P6 Binary Floating-Point Unit.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF	denormal result handling, aggressive data forwarding, high-frequency design, data processing without stalls, Floating-point unit
3	Jérémie Detrey, Florent de Dinechin, Xavier Pujol	Return of the hardware floating-point elementary function.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF	Floating-point elementary functions, hardware operator, FPGA, exponential, logarithm
3	Tateaki Sasaki, Fujio Kako	Computing floating-point gröbner bases stably.	SNC	2007	DBLP DOI BibTeX RDF	Gröbner base, approximate Gröbner base, floating-point Gröbner base, stabilization
3	Julio Villalba, Tomás Lang, Mario A. González	Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Range-reduction, elementary function evaluation, floating-point arithmetic
3	George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	testability conditions, datapath testing, floating-point unit testing, Test generation, processor testing
3	Ahmet Akkas	Dual-Mode Quadruple Precision Floating-Point Adder.	DSD	2006	DBLP DOI BibTeX RDF	Quadruple precision, dualmode, computer arithmetic, floating-point, adder, double precision
3	Anuja Jayraj Thakkar, Abdel Ejnioui	Pipelining of double precision floating point division and square root operations.	ACM Southeast Regional Conference	2006	DBLP DOI BibTeX RDF	FPGA, pipelining, floating point, division, square root
3	K. Scott Hemmert, Keith D. Underwood	Open Source High Performance Floating-Point Modules.	FCCM	2006	DBLP DOI BibTeX RDF	IEEE floating point, FPGA, reconfigurable computing
3	Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert	Embedded floating-point units in FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	FPU, FPGA, floating-point, FPGA architecture
3	Alexander Serebrenik, Danny De Schreye	Termination of Floating-Point Computations.	J. Autom. Reasoning	2005	DBLP DOI BibTeX RDF	floating point, numerical computation, termination analysis
3	Christian Jacobi 0002, Christoph Berg	Formal Verification of the VAMP Floating Point Unit.	Formal Methods in System Design	2005	DBLP DOI BibTeX RDF	IEEE standard 754, formal verification, theorem proving, PVS, floating point unit
3	K. Scott Hemmert, Keith D. Underwood	An Analysis of the Double-Precision Floating-Point FFT on FPGAs.	FCCM	2005	DBLP DOI BibTeX RDF	IEEE floating point, FPGA, FFT, Fast Fourier Transform, reconfigurable computing
3	Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, Georgi Gaydadjiev	64-bit floating-point FPGA matrix multiplication.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, matrix multiplication, floating-point
3	Peter-Michael Seidel, Guy Even	Delay-Optimized Implementation of IEEE Floating-Point Addition.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	IEEE rounding, dual path algorithm, optimized gate sizing, buffer insertion, delay optimization, logical effort, Floating-point addition
3	Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen	A compact DSP core with static floating-point unit & its microcode generation.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	DSP core, digital signal processor, floating-point units
3	Sanghamitra Roy, Prithviraj Banerjee	An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design.	DAC	2004	DBLP DOI BibTeX RDF	quantization, quantizer, floating point, fixed point
3	Steven D. Krueger, Peter-Michael Seidel	Design of an On-Line IEEE Floating-Point Addition Unit for FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF	IEEE rounding, Floating-point addition, on-line arithmetic
3	Keith D. Underwood, K. Scott Hemmert	Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance.	FCCM	2004	DBLP DOI BibTeX RDF	IEEE floating point, re-configurable computing, FPGA, arithmetic
3	Lianfang Tian, Curtis Collins	Motion Planning for Redundant Manipulators Using a Floating Point Genetic Algorithm.	Journal of Intelligent and Robotic Systems	2003	DBLP DOI BibTeX RDF	genetic algorithm, motion planning, redundant robot, floating point representation
3	Yves Nievergelt	Scalar fused multiply-add instructions produce floating-point matrix arithmetic provably accurate to the penultimate digit.	ACM Trans. Math. Softw.	2003	DBLP DOI BibTeX RDF	Doubly compensated summation, fused multiply-add instruction, matrix arithmetic, provable accuracy, floating-point arithmetic, rounding error
3	Álvaro Vázquez, Elisardo Antelo	Implementation of the Exponential Function in a Floating-Point Unit.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	exponential function, computer arithmetic, floating-point unit, transcendental functions
3	Ahmet Akkas, Michael J. Schulte	A Quadruple Precision and Dual Double Precision Floating-Point Multiplier.	DSD	2003	DBLP DOI BibTeX RDF	Quadruple precision, computer arithmetic, normalization, floating-point, multiplier, rounding, double precision
3	Xu Zhou, Zhimin Tang	A New Architecture of a Fast Floating-Point Multiplier.	APPT	2003	DBLP DOI BibTeX RDF	Floating-point Multiplier, Processor
3	Mikio Takeuchi, Hideaki Komatsu, Toshio Nakatani	A new speculation technique to optimize floating-point performance while preserving bit-by-bit reproducibility.	ICS	2003	DBLP DOI BibTeX RDF	bit-by-bit reproducibility, floating-point speculation, fused multiply-add, reassociation, striding, Java, prefetching, accuracy, instruction-level parallelism, software pipelining, just-in-time compiler, loop unrolling, privatization, IA-64, IEEE 754
3	Keith O. Geddes, Wei Wei Zheng	Exploiting fast hardware floating point in high precision computation.	ISSAC	2003	DBLP DOI BibTeX RDF	arbitrary precision, floating point, least squares, nonlinear systems, linear systems, iterative refinement, multiple precision
3	Ahmet Akkas	A Combined Interval and Floating-Point Comparator/Selector.	ASAP	2002	DBLP DOI BibTeX RDF	VLSI design, Interval arithmetic, floating-point arithmetic, comparator, specialized hardware, selector
3	Daniel Menard, Daniel Chillet, François Charot, Olivier Sentieys	Automatic floating-point to fixed-point conversion for DSP code generation.	CASES	2002	DBLP DOI BibTeX RDF	digital signal processing systems, floating-point to fixed-point conversion, quantization noise, code generation, DSP, fixed-point
3	David M. Smith	Algorithm 814: Fortran 90 software for floating-point multiple precision arithmetic, gamma and related functions.	ACM Trans. Math. Softw.	2001	DBLP DOI BibTeX RDF	gamma function, mathematical library, Fortran, Accuracy, floating point, function evaluation, multiple precision, portable software
3	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah	A Low Power Approach to Floating Point Adder Design for DSP Applications.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	digital-CMOS, power-consumption-model, VLSI, low-power-design, computer-arithmetic, floating-point, switching-activity
3	Henrik Koy, Claus-Peter Schnorr	Segment LLL-Reduction with Floating Point Orthogonalization.	CaLC	2001	DBLP DOI BibTeX RDF	LLL-reduction, Householder reflexion, scaled basis, segment LLL-reduction, local LLL-reduction, stability, floating point arithmetic
3	E. Pearse O'Grady	Hardware Support for Floating Point Map Function Generation.	Annual Simulation Symposium	1999	DBLP DOI BibTeX RDF	simulation, table-lookup, function generation, Floating point computation
3	Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, Cheng-Chew Lim	Reduced Latency IEEE Floating-Point Standard Adder Architectures.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF	VLSI, floating-point, adder, arithmetic
3	James E. Stine, Michael J. Schulte	A Combined Interval and Floating Point Multiplier.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	computer arithmetic, accuracy, multiplication, floating point, hardware design, rounding, Interval, double precision
3	R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili	A Low Power Floating Point Accumulator.	VLSI Design	1998	DBLP DOI BibTeX RDF	low power CMOS, Digital arithmetic, VLSI architecture, floating point
3	Walter Krämer	A Priori Worst-Case Error Bounds for Floating-Point Computations.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	Reliable Error Estimates, Table-lookup Algorithm, Error Bounds, Floating-Point Computations
3	Stuart F. Oberman, Hesham A. Al-Twaijry, Michael J. Flynn	The SNAP Project: Design of Floating Point Arithmetic Unit.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	performance-area tradeoffs, computer arithmetic, multiplication, division, Addition, floating point unit
3	Yirng-An Chen, Randal E. Bryant	PHDD: an efficient graph representation for floating point circuit verification.	ICCAD	1997	DBLP DOI BibTeX RDF	KFDD, BMD, HDD, KBMD, Verification, Formal Verifications, BDD, Floating Point, FDD, BMD
3	John R. Hauser	Handling Floating-Point Exceptions in Numeric Programs.	ACM Trans. Program. Lang. Syst.	1996	DBLP DOI BibTeX RDF	exception handling, floating-point, arithmetic
3	Robert G. Burger, R. Kent Dybvig	Printing Floating-Point Numbers Quickly and Accurately.	PLDI	1996	DBLP DOI BibTeX RDF	floating-point printing, run-time systems
3	Jean-Claude Bajard, Laurent-Stéphane Didier, Jean-Michel Muller	A New Euclidean Division Algorithm For Residue Number Systems.	ASAP	1996	DBLP DOI BibTeX RDF	Euclidean division algorithm, large moduli, very large integers, high-radix division method, parallel computer, computational geometry, digital arithmetic, residue number systems, residue number systems, floating point arithmetic, floating-point arithmetic, modular arithmetic, special-purpose architecture
3	Richard J. Fateman, Kevin A. Broughan, Diane M. K. Willcock, Duane Rettig	Fast Floating Point Processing in Common Lisp.	ACM Trans. Math. Softw.	1995	DBLP DOI BibTeX RDF	Fortran, Lisp, compiler optimization, floating-point arithmetic, symbolic computation, numerical algorithms, Common Lisp, Common Lisp, C programming language
3	S. Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian	A GaAs IEEE Floating Point Standard Single Precision Multiplier.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	floating point multiplier, rounding algorithm, modified carry save array, GaAs technology
3	Mark Aagaard, Carl-Johan H. Seger	The formal verification of a pipelined double-precision IEEE floating-point multiplier.	ICCAD	1995	DBLP DOI BibTeX RDF	ANSI/IEEE Std 754-1985, model checking, theorem proving, floating-point arithmetic, Hardware verification
3	A. Houelle, Habib Mehrez, N. Vaucher, Luis A. Montalvo, Alain Guyot	Application of fast layout synthesis environment to dividers evaluation.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	layout synthesis environment, dividers evaluation, GenOptim, IEEE 754 floating-point macro-cell generators, programming environments, generator programs, division, floating point arithmetic, square root, dividing circuits
3	Miriam Leeser, John W. O'Leary	Verification of a subtractive radix-2 square root algorithm and implementation. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	subtractive radix-2 square root, floating point square root hardware, Intel Pentium, radix-2 square root, MIPS R4400, RTL level, verification, formal verification, theorem proving, theorem proving, floating point arithmetic, optimizing transformations
3	Gerd Bohlender	Floating-Point Computation of Functions with Maximum Accuracy.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	multiple-length mantissas, roots of floating-point numbers, Accuracy, errors, rounding, floating-point computations
3	Peter Linz	Accurate floating-point summation.	Commun. ACM	1970	DBLP DOI BibTeX RDF	round-off error propagation, summation, round-off error, floating-point addition
3	R. de Vogelaere	Algorithms: Algorithm 335: a set of basic input-output procedures.	Commun. ACM	1968	DBLP DOI BibTeX RDF	ALGOL 60, Berkeley style, decompose integer, decompose real, equivalent ALGOL statements, fixed point representation, input echo, input outpur array, input output Boolean, input output procedures, integer format, out integer, output channel interpretation, output documentation, procedures relationship, quality output, read real, real format, ALGOL, style, transput, input output, floating point representation, floating point representational
2	Jim Rasmusson, Jacob Ström, Tomas Akenine-Möller	Error-bounded lossy compression of floating-point color buffers using quadtree decomposition.	The Visual Computer	2010	DBLP DOI BibTeX RDF	Color buffer compression, Real-time, Quadtree, High dynamic range, Lossy compression, Texture compression
2	Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin	Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Adder/subtractor, redundant format, computer arithmetic, floating point, rounding, signed-digit number system
2	Patrice Godefroid, Johannes Kinder	Proving memory safety of floating-point computations by combining static and dynamic program analysis.	ISSTA	2010	DBLP DOI BibTeX RDF	static and dynamic program analysis, program verification
2	Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler	Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs.	ISMVL	2010	DBLP DOI BibTeX RDF	Memory-based floating-point numeric function generators, piecewise-split EVMDDs
2	Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik	A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm.	VLSI Design	2010	DBLP DOI BibTeX RDF	multiply-accumulate, Fused and continuous MAC, VLSI, Floating-point
2	Kentaro Sano, Kazuya Katahira, Satoru Yamamoto	Segment-Parallel Predictor for FPGA-Based Hardware Compressor and Decompressor of Floating-Point Data Streams to Enhance Memory I/O Bandwidth.	DCC	2010	DBLP DOI BibTeX RDF	prediction-based compresson, hardware, floating point, memory bandwidth, lossless compression
2	Y. Hamid, Martin Langhammer	Multiplier architectures for FPGA double precision functions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, floating point
2	George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units.	IEEE Trans. Dependable Sec. Comput.	2009	DBLP DOI BibTeX RDF
2	Marius Cornea, John Harrison, Cristina Anderson, Ping Tak Peter Tang, Eric Schneider, Evgeny Gvozdev	A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
2	Liang-Kai Wang, Michael J. Schulte, John D. Thompson, Nandini Jairam	Hardware Designs for Decimal Floating-Point Addition and Related Operations.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
2	Dimitri Tan, Carl Lemonds, Michael J. Schulte	Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
2	Martin Burtscher, Paruj Ratanaworabhan	FPC: A High-Speed Compressor for Double-Precision Floating-Point Data.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
2	Angelo Brillout, Daniel Kroening, Thomas Wahl	Mixed abstractions for floating-point arithmetic.	FMCAD	2009	DBLP DOI BibTeX RDF
2	Sylvie Boldo, Jean-Christophe Filliâtre, Guillaume Melquiond	Combining Coq and Gappa for Certifying Floating-Point Programs.	Calculemus/MKM	2009	DBLP DOI BibTeX RDF
2	T. Chun Pong Chau, S. Man Ho Ho, Philip Heng Wai Leong, Peter Zipf, Manfred Glesner	Generation of Synthetic Floating-Point benchmark circuits.	IPDPS	2009	DBLP DOI BibTeX RDF
2	Christoph Fünfzig, Dominique Michelucci, Sebti Foufou	Nonlinear systems solver in floating-point arithmetic using LP reduction.	Symposium on Solid and Physical Modeling	2009	DBLP DOI BibTeX RDF	intersection computation, subdivision solver, linear programming, CAD, interval arithmetic, geometric constraints, geometric constraint solving, distance computation
2	Charles Tsen, Sonia Gonzalez-Navarro, Michael J. Schulte, Brian J. Hickmann, Katherine Compton	A Combined Decimal and Binary Floating-Point Multiplier.	ASAP	2009	DBLP DOI BibTeX RDF
2	Martin Langhammer, Tom VanCourt	FPGA Floating Point Datapath Compiler.	FCCM	2009	DBLP DOI BibTeX RDF	performance computing, optimization, FPGA, floating point
2	Manish Kumar Jaiswal, Nitin Chandrachoodan	Efficient Implementation of Floating-Point Reciprocator on FPGA.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Stefan Funke	Of What Use Is Floating-Point Arithmetic in Computational Geometry?	Efficient Algorithms	2009	DBLP DOI BibTeX RDF
2	David Monniaux	On Using Floating-Point Computations to Help an Exact Linear Arithmetic Decision Procedure.	CAV	2009	DBLP DOI BibTeX RDF