Search results for "force-directed scheduling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Pradeep Prabhakaran, Prithviraj Banerjee	Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	parallel algorithms, multiprocessors, High-level synthesis, network of workstations, hierarchical graphs, force-directed scheduling
2	Rehab F. Abdel-Kader	Resource-constrained loop scheduling in high-level synthesis.	ACM Southeast Regional Conference	2005	DBLP DOI BibTeX RDF	scheduling, high-level synthesis, force-directed scheduling
2	Gang Wang, Wenrui Gong, Ryan Kastner	Instruction scheduling using MAX-MIN ant system optimization.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	MAX-MIN ant system, instruction scheduling, list scheduling, force-directed scheduling
2	Suvodeep Gupta, Srinivas Katkoori	Force-Directed Scheduling for Dynamic Power Optimization.	ISVLSI	2002	DBLP DOI BibTeX RDF
2	Wen-Tsong Shiue	High Level Synthesis for Peak Power Minimization Using ILP.	ASAP	2000	DBLP DOI BibTeX RDF	Peak power minimization, latency-constrained scheduling, High-level synthesis, low power design, integer linear programming, force-directed scheduling
2	Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jan H. M. Korst, Jef L. van Meerbergen, Albert van der Werf	Improved force-directed scheduling in high-throughput digital signal processing.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	Pierre G. Paulin, John P. Knight	Force-directed scheduling for the behavioral synthesis of ASICs.	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
2	Pierre G. Paulin, John P. Knight	Force-Directed Scheduling in Automatic Data Path Synthesis.	DAC	1987	DBLP DOI BibTeX RDF
1	Rohit Sinha, Hiren D. Patel	Extending Force-Directed Scheduling with Explicit Parallel and Timed Constructs for High-Level Synthesis.	FCCM	2011	DBLP DOI BibTeX RDF
1	Matthew Areno, Brandon Eames, Joshua Templin	A Force-Directed Scheduling based architecture generation algorithm and design tool for FPGAs.	Journal of Systems Architecture - Embedded Systems Design	2010	DBLP DOI BibTeX RDF
1	Wei Zhang 0012, Niraj K. Jha, Li Shang	A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow.	JETC	2009	DBLP DOI BibTeX RDF	design optimization flow, logic folding, Dynamic reconfiguration, NATURE
1	Zhixiong Zhou, Hu He, Yanjun Zhang, Yihe Sun, Adriel Cheng	A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture.	ASAP	2007	DBLP DOI BibTeX RDF
1	Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner	Exploring time/resource trade-offs by solving dual scheduling problems with the ant colony optimization.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	max-min ant system, ant colony optimization, Design space exploration, instruction scheduling
1	Wei Zhang 0012, Li Shang, Niraj K. Jha	NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture.	DAC	2007	DBLP DOI BibTeX RDF
1	David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee	Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs.	ISQED	2007	DBLP DOI BibTeX RDF
1	Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner	Ant Colony Optimizations for Resource- and Timing-Constrained Operation Scheduling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner	Design space exploration using time and resource duality with the ant colony optimization.	DAC	2006	DBLP DOI BibTeX RDF	MAX-MIN ant system, instruction scheduling algorithms, ant colony optimization, design space exploration
1	Mahmoud Meribout, Masato Motomura	A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Dynamic reconfigurable logic, scheduling, partitioning, allocation, communication cost
1	Mahmoud Meribout, Masato Motomura	Efficient metrics and high-level synthesis for dynamically reconfigurable logic.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Fu San Hiew, Kah Hoe Koay	High-Level Language and Compiler for Reconfigurable Computing.	CIS	2004	DBLP DOI BibTeX RDF
1	Yang Qu, Juha-Pekka Soininen	Estimating the Utilization of Embedded FPGA Co-Processor.	DSD	2003	DBLP DOI BibTeX RDF
1	Bharath Radhakrishnan, Muthukumar Venkatesan	Multiple Voltage and Frequency Scheduling for Power Minimization.	DSD	2003	DBLP DOI BibTeX RDF
1	Dongku Kang, Mark C. Johnson, Kaushik Roy	Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan.	ICCD	2003	DBLP DOI BibTeX RDF
1	Tomoo Inoue, Tomokazu Miura, Akio Tamura, Hideo Fujiwara	A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
1	V. Muresan, Xiaojun Wang, Mircea Vladutiu	A combined tree growing technique for block-test scheduling under power constraints.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Thierry J.-F. Omnés, Thierry Franzetti, Francky Catthoor	Interactive co-design of high throughput embedded multimedia.	DAC	2000	DBLP DOI BibTeX RDF
1	Sriram Govindarajan, Ranga Vemuri	Improving the Schedule Quality of Static-List Time-Constrained Scheduling.	DATE	2000	DBLP DOI BibTeX RDF
1	Thierry J.-F. Omnés, Francky Catthoor, Thierry Franzetti	Multi-dimensional Selection Techniques for Minimizing Memory Bandwidth in High-Throughput Embedded Systems.	HiPC	2000	DBLP DOI BibTeX RDF
1	Pradeep Prabhakaran, Prithviraj Banerjee	Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF
1	Douglas Chang, Malgorzata Marek-Sadowska	Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Dynamically reconfigurable FPGAs, time-mulitplexed FPGA, Dharma, DPGA, field programmable gate array, partitioning, reconfigurable computing, sequential circuit, force directed scheduling
1	Christoph Jäschke, Rainer Laur, Friedrich Beckmann	Time Constrained Modulo Scheduling with Global Resource Sharing.	DATE	1999	DBLP DOI BibTeX RDF
1	Douglas Chang, Malgorzata Marek-Sadowska	Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
1	Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jan H. M. Korst, Albert van der Werf, Jef L. van Meerbergen	Efficiency improvements for force-directed scheduling.	ICCAD	1992	DBLP DOI BibTeX RDF
1	Richard J. Cloutier, Donald E. Thomas	The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm.	DAC	1990	DBLP DOI BibTeX RDF