Search results for "full-scan circuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel	Cyclic stress tests for full scan circuits.	VTS	1995	DBLP DOI BibTeX RDF	cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits
2	Irith Pomeranz, Sudhakar M. Reddy	The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits.	DATE	2005	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Multiple Full-Scan Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Reducing test application time for full scan circuits by the addition of transfer sequences.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	transfer sequences, primary input vectors, scan-in operation, scan-out operation, static compaction procedure, compaction levels, fault diagnosis, logic testing, design for testability, fault detection, automatic testing, boundary scan testing, test set, test application time, full scan circuits
2	Irith Pomeranz, Sudhakar M. Reddy	Functional Test Generation for Full Scan Circuits.	DATE	2000	DBLP DOI BibTeX RDF
2	Ilker Hamzaoglu, Janak H. Patel	Compact two-pattern test set generation for combinational and full scan circuits.	ITC	1998	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Static test compaction for diagnostic test sets of full-scan circuits.	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Output-Dependent Diagnostic Test Generation.	VLSI Design	2010	DBLP DOI BibTeX RDF	diagnostic test generation, stuck-at faults, full-scan circuits
1	Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute	Comprehensive bridging fault diagnosis based on the SLAT paradigm.	DDECS	2009	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests.	VTS	2008	DBLP DOI BibTeX RDF	functional broadside tests, test generation, transition faults, reachable states, full-scan circuits
1	Irith Pomeranz, Sudhakar M. Reddy	Synthesis for Broadside Testability of Transition Faults.	VTS	2008	DBLP DOI BibTeX RDF	broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
1	Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz	On the Detectability of Scan Chain Internal Faults An Industrial Case Study.	VTS	2008	DBLP DOI BibTeX RDF	Faults in scan cells, stuck-at and stuck-on faults
1	Irith Pomeranz, Sudhakar M. Reddy	The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits	CoRR	2007	DBLP BibTeX RDF
1	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker	Automatic Test Pattern Generation for Resistive Bridging Faults.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	resistive short defects, ATPG, SAT, bridging faults
1	Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu	Fault simulation and response compaction in full scan circuits using HOPE.	IEEE T. Instrumentation and Measurement	2005	DBLP DOI BibTeX RDF
1	Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu	Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization.	IEEE T. Instrumentation and Measurement	2005	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Scan circuits, test application time, static test compaction
1	Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy	Test Application Time Reduction for Scan Circuits Using Limited Scan Operations.	ISQED	2004	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Madhu K. Iyer, Kwang-Ting Cheng	Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs.	VTS	2002	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits.	Journal of Systems Architecture	2001	DBLP DOI BibTeX RDF
1	Tsung-Chu Huang, Kuen-Jong Lee	Reduction of power consumption in scan-based circuits during testapplication by an input control technique.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	On achieving complete coverage of delay faults in full scan circuits using locally available lines.	ITC	1999	DBLP DOI BibTeX RDF
1	Tsung-Chu Huang, Kuen-Jong Lee	An Input Control Technique for Power Reduction in Scan Circuits During Test Application.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	ATPG, VLSI testing, Power Minimization, Low-power Test, Full-scan
1	Zhide Zeng, Jihua Chen, Hefeng Cao	Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	finite backtracking test pattern generation, n to 1 tightly coupled integration mode, parallel-pattern, single-fault propagation, ultra large scale combinational circuit (ULSCC
1	Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng	An almost full-scan BIST solution-higher fault coverage and shorter test application time.	ITC	1998	DBLP DOI BibTeX RDF
1	Sreejit Chakravarty, Yiming Gong, Srikanth Venkataraman	Diagnostic simulation of stuck-at faults in combinational circuits.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	diagnostic power, diagnostic simulation, diagnosis, equivalence classes, diagnostic resolution
1	Kaushik De, Arun Gunda	Failure Analysis for Full-Scan Circuits.	ITC	1995	DBLP DOI BibTeX RDF
1	Elizabeth M. Rudnick, Janak H. Patel	A genetic approach to test application time reduction for full scan and partial scan circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	partial scan circuits, design-for-testability techniques, compact test set generation, genetic algorithms, genetic algorithms, logic testing, design for testability, logic design, sequential circuits, combinational circuits, DFT, flip-flops, test application time reduction, full scan circuits
1	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Partial scan design and test sequence generation based on reduced scan shift method.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	partial scan circuit, short test sequence, reduced scan shift, scan design, test sequence generation
1	Sreejit Chakravarty, Sivaprakasam Suresh	IDDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits.	VLSI Design	1994	DBLP BibTeX RDF