Search results for "functional units"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Taniya Siddiqua, Sudhanva Gurumurthi	A multi-level approach to reduce the impact of NBTI on processor functional units.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	reliability, NBTI
2	Taemin Kim, Xun Liu	Better than optimum?: register reduction using idle pipelined functional units.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	high level synthesis, register binding
2	Tsuyoshi Sadakata, Yusuke Matsunaga	An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Temperature and Process Variations Aware Power Gating of Functional Units.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Power Reduction of Functional Units Considering Temperature and Process Variations.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Shih-Hao Ou, Yi Cho, Tay-Jyi Lin, Chih-Wei Liu	Improving datapathutilization of programmable DSP with composite functional units.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Linfeng Pan, Minyi Guo, Yanqin Yang, Meng Wang, Zili Shao	A State-Based Predictive Approach for Leakage Reduction of Functional Units.	EUC	2008	DBLP DOI BibTeX RDF
2	Kaushal R. Gandhi, Nihar R. Mahapatra	Partitioned reuse cache for energy-efficient soft-error protection of functional units.	SoCC	2008	DBLP DOI BibTeX RDF
2	Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida, Francisco Tirado	Applying speculation techniques to implement functional units.	ICCD	2008	DBLP DOI BibTeX RDF
2	Nagarajan Venkateswaran, Karthik Chandrasekar 0001, Shrikanth Ganapathy	Design for Testability of Functional Cores in High Performance Node Architectures.	DELTA	2008	DBLP DOI BibTeX RDF	Integrated Memory and Logic, Memory-in-Logic Cells, Higher Level Functional Units, Performance Consistency, Reliabilty, Heterogenous Multi-Core
2	Yousuke Nakamura, Kei Hiraki	Heterogeneous Functional Units for High Speed Fault-Tolerant Execution Stage.	PRDC	2007	DBLP DOI BibTeX RDF
2	Kyle Rupnow, Keith D. Underwood, Katherine Compton	Scientific Application Acceleration with Reconfigurable Functional Units.	FCCM	2007	DBLP DOI BibTeX RDF
2	Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan	A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Nagaraju Pothineni, Anshul Kumar, Kolin Paul	Application Specific Datapath Extension with Distributed I/O Functional Units.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Elias Mizan, Tileli Amimeur, Margarida F. Jacome	Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional Units.	SBAC-PAD	2007	DBLP DOI BibTeX RDF
2	Awni Itradat, M. Omair Ahmad, Ali Shatnawi	Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional Units.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz	Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor.	ICCD	2007	DBLP DOI BibTeX RDF
2	Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López	A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar	A Power-Aware Technique for Functional Units in High-Performance Processors.	DSD	2006	DBLP DOI BibTeX RDF
2	Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry	Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units.	MICRO	2006	DBLP DOI BibTeX RDF
2	Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi	Automatic identification of application-specific functional units with architecturally visible storage.	DATE	2006	DBLP DOI BibTeX RDF
2	Jui-Chin Chu, Chih-Wen Huang, He-Chun Chen, Keng-Po Lu, Ming-Shuan Lee, Jiun-In Guo, Tien-Fu Chen	Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Compiler-directed thermal management for VLIW functional units.	LCTES	2006	DBLP DOI BibTeX RDF	VLIW, thermal, IPC
2	Miroslav N. Velev	Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units.	CHARME	2005	DBLP DOI BibTeX RDF
2	Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha	High-level synthesis for DSP applications using heterogeneous functional units.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Kaushal R. Gandhi, Nihar R. Mahapatra	Dynamically Exploiting Frequent Operand Values for Energy Efficiency in Integer Functional Units.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero	with Wide Functional Units.	SAMOS	2004	DBLP DOI BibTeX RDF
2	Akihiro Chiyonobu, Toshinori Sato	Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture.	ISICT	2004	DBLP DOI BibTeX RDF
2	Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne	Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units.	SCOPES	2004	DBLP DOI BibTeX RDF
2	Zili Shao, Qingfeng Zhuge, Yi He, Chun Xue, Meilin Liu, Edwin Hsing-Mean Sha	Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units.	IPDPS	2004	DBLP DOI BibTeX RDF
2	Marc Epalza, Paolo Ienne, Daniel Mlynek	Dynamic Reallocation of Functional Units in Superscalar Processors.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
2	João M. P. Cardoso	On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	scheduling, FPGAs, reconfigurable computing, temporal partitioning
2	Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman	Managing static leakage energy in microprocessor functional units.	MICRO	2002	DBLP DOI BibTeX RDF
2	M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha	A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.	ISSS	2002	DBLP DOI BibTeX RDF	Trimaran, performance, design space exploration, VLIW, ASIP
2	Siddharth Rele, Santosh Pande, Soner Önder, Rajiv Gupta	Optimizing Static Power Dissipation by Functional Units in Superscalar Processors.	CC	2002	DBLP DOI BibTeX RDF
2	Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama	Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units.	DATE	2002	DBLP DOI BibTeX RDF
2	Lori Carter, Weihaw Chuang, Brad Calder	An EPIC Processor with Pending Functional Units.	ISHPC	2002	DBLP BibTeX RDF
2	Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac	High-Level Synthesis with SIMD Units.	VLSI Design	2002	DBLP DOI BibTeX RDF	SIMD functional units, High-level synthesis, high performance design
2	Junghwan Choi, Jinhwan Jeon, Kiyoung Choi	Power minimization of functional units partially guarded computation.	ISLPED	2000	DBLP DOI BibTeX RDF	partially guarded computation, low power
2	Miroslav N. Velev, Randal E. Bryant	Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction.	DAC	2000	DBLP DOI BibTeX RDF
2	Michele Favalli, Cecilia Metra	On the Design of Self-Checking Functional Units Based on Shannon Circuits.	DATE	1999	DBLP DOI BibTeX RDF
2	Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi	Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units.	VLSI Signal Processing	1998	DBLP DOI BibTeX RDF
2	Salil Raje, Reinaldo A. Bergamaschi	Generalized resource sharing.	ICCAD	1997	DBLP DOI BibTeX RDF	clique-partitioning-based algorithms, generalized resource sharing, global clique partitioning based framework, interconnect cost estimation, merging cost estimation, sharing possibilities, high level synthesis, high-level synthesis, functional unit, functional units
2	Raghava V. Cherabuddi, Magdy A. Bayoumi, H. Krishnamurthy	A low power based system partitioning and binding technique for multi-chip module architectures.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	binding technique, multi-chip module architectures, high-level synthesis framework, inter-chip buses, stochastic evolution based technique, multichip modules, switching activity, MCM, functional units, system partitioning, benchmark designs
2	Samit Chaudhuri, Robert A. Walker	Computing lower bounds on functional units before scheduling.	IEEE Trans. VLSI Syst.	1996	DBLP DOI BibTeX RDF
2	Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi	Loop-List Scheduling for Heterogeneous Functional Units.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
2	Roger Collins, Gordon Steven	Instruction Scheduling for a Superscalar Architecture.	EUROMICRO	1996	DBLP DOI BibTeX RDF	compile-time instruction scheduling, conditional group scheduler, HSA processor model, guarded instruction execution, instruction squashing, instruction buffer, performance evaluation, superscalar processors, superscalar architecture, functional units, branch instructions
2	Eliseu M. Chaves Filho, Edil S. Tavares Fernandes, Andrew Wolfe	Load Balancing in Superscalar Architectures.	EUROMICRO	1996	DBLP DOI BibTeX RDF	multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources
2	Stéphan Jourdan, Pascal Sainrat, Daniel Litaize	Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor.	ISCA	1995	DBLP DOI BibTeX RDF
2	Enric Musoll, Jordi Cortadella	Scheduling and resource binding for low power.	ISSS	1995	DBLP DOI BibTeX RDF	data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding
2	Siamak Arya, Howard Sachs, Sreeram Duvvuru	An architecture for high instruction level parallelism.	HICSS	1995	DBLP DOI BibTeX RDF	high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, branches, program control structures, registers, functional units, multiple instructions, conditional execution
2	Rahul Razdan, Michael D. Smith	A high-performance microarchitecture with hardware-programmable functional units.	MICRO	1994	DBLP DOI BibTeX RDF	automatic instruction set design, compile-time optimization, general-purpose microarchitectures, logic synthesis, programmable logic
2	Miguel Valero-García, Juan J. Navarro, José María Llabería, Mateo Valero, Tomás Lang	A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units.	VLSI Signal Processing	1992	DBLP DOI BibTeX RDF
2	Yiwan Wong, Jean-Marc Delosme	Optimization of Computation Time for Systolic Arrays.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	multiple functional units, pipelined functional units, computation time minimization, linear scheduling function, bounded search space, parallel algorithms, concurrency, multiprocessor interconnection networks, systolic arrays, systolic arrays, minimisation, combinatorial optimization problem, branch-and-bound method
2	Nam Sung Woo, H. Shin	A Technology-adaptive Allocation of Functional Units and Connections.	DAC	1989	DBLP DOI BibTeX RDF
2	Ashok Singhal, Yale N. Patt	Implementing a Prolog machine with multiple functional units.	MICRO	1988	DBLP DOI BibTeX RDF	Prolog
1	Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh	Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy.	TACO	2011	DBLP DOI BibTeX RDF
1	Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, Jose Manuel Mendias, Román Hermida	A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Miroslav N. Velev, Ping Gao 0002	Exploiting Abstraction for Efficient Formal Verification of DSPs with Arrays of Reconfigurable Functional Units.	ICFEM	2011	DBLP DOI BibTeX RDF
1	Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck	Energy-efficient specialization of functional units in a coarse-grained reconfigurable array.	FPGA	2011	DBLP DOI BibTeX RDF
1	Chia-Jung Chen, Rong-Guey Chang	Thermal-Aware Code Transformation across Functional Units.	EUC	2011	DBLP DOI BibTeX RDF
1	Aditi Kajala, Gayaprasad Sinsinwar, Rahul Raj Choudhary, Jaynarayan T. Tudu, Virendra Singh	On selection of state variables for delay test of identical functional units.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Andreas Koltes, John T. O'Donnell	A framework for FPGA functional units in high performance computing.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
1	Paolo Missier, Katy Wolstencroft, Franck Tanoh, Peter Li, Sean Bechhofer, Khalid Belhajjame, Steve Pettifer, Carole A. Goble	Functional Units: Abstractions for Web Service Annotations.	SERVICES	2010	DBLP DOI BibTeX RDF	service annotations, service discovery
1	Jongbok Lee	A Superscalar Processor Model for Limited Functional Units Using Instruction Dependencies.	CATA	2010	DBLP BibTeX RDF
1	Lin Li, Youtao Zhang, Jun Yang 0002, Jianhua Zhao	Proactive NBTI mitigation for busy functional units in out-of-order microprocessors.	DATE	2010	DBLP BibTeX RDF
1	Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Román Hermida, Seda Ogrenci Memik	Using Speculative Functional Units in high level synthesis.	DATE	2010	DBLP BibTeX RDF
1	Shih-Hao Ou, Yen-Cheng Lin, Tay-Jyi Lin, Chih-Wei Liu	Improving energy efficiency of functional units by exploiting their data-dependent latency.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Danial Lashkari, Ramesh Sridharan, Polina Golland	Categories and Functional Units: An Infinite Hierarchical Model for Brain Activations.	NIPS	2010	DBLP BibTeX RDF
1	Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto	A revisit to voltage partitioning problem.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	quasiconvex assumption, voltage partition
1	Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	Understanding sources of inefficiency in general-purpose chips.	ISCA	2010	DBLP DOI BibTeX RDF	tensilica, energy efficiency, chip multiprocessor, customization, ASIC, h.264, high performance
1	Somnath Paul, Swarup Bhunia	VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement.	ISLPED	2010	DBLP DOI BibTeX RDF	narrow-width operand, superscalar processor, within-die variation
1	Jason Cong, Guojie Luo	An analytical placer for mixed-size 3D placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, 3D integration, analytical method
1	Jan A. Bergstra, C. A. Middelburg	Functional units for natural numbers	CoRR	2009	DBLP BibTeX RDF
1	Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori	A Framework for Power-Gating Functional Units in Embedded Microprocessors.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Nicholas Weaver, John H. Kelm, Matthew I. Frank	Emµcode: Masking hard faults in complex functional units.	DSN	2009	DBLP DOI BibTeX RDF
1	Antoine Trouve, Lovic Gauthier, Takayuki Kando, Benoit Ryder, Sebastien Pouzols, Pradeep Rao, Norifumi Yoshimatsu, Kazuaki Murakami	Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units.	ReConFig	2009	DBLP DOI BibTeX RDF	compiler, Dynamic reconfiguration, accelerator
1	Shih-Hsu Huang, Chun-Hua Cheng	Timing driven power gating in high-level synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Gregory Lucas, Scott Cromar, Deming Chen	FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Feng Wang 0004, Yuan Xie, Andrés Takach	Variation-aware resource sharing and binding in behavioral synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Yingchao Zhao, Chun Jason Xue, Minming Li, Bessie C. Hu	Energy-aware register file re-partitioning for clustered VLIW architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Insup Shin, Seungwhun Paik, Youngsoo Shin	Register allocation for high-level synthesis using dual supply voltages.	DAC	2009	DBLP DOI BibTeX RDF	low power, high-level synthesis, register allocation, dual supply voltage
1	Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González	End-to-end register data-flow continuous self-test.	ISCA	2009	DBLP DOI BibTeX RDF	end-to-end protection, online testing, degradation, design errors, control logic
1	Wael Adi, Nizar Kassab	Hardware architecture for trustable vehicular electronic control units.	IWCMC	2009	DBLP DOI BibTeX RDF	clone-resistant identity, vehicular security, identification
1	Weifeng Xu, Russell Tessier	Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors.	TACO	2009	DBLP DOI BibTeX RDF	Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure
1	Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	coarse-grained FPGA, VLIW, ASIP
1	Jason Cong, Yiping Fan, Junjuan Xu	Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	distributed register file, Behavioral synthesis, resource binding
1	Meikang Qiu, Edwin Hsing-Mean Sha	Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Embedded Systems, real-time, high-level synthesis, heterogeneous
1	Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux	Vector Processing as a Soft Processor Accelerator.	TRETS	2009	DBLP DOI BibTeX RDF	parallelism, Computer architecture, embedded processor, vector processor, multimedia processing, soft processor
1	Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich	Impact of Loop Tiling on the Controller Logic of Acceleration Engines.	ASAP	2009	DBLP DOI BibTeX RDF
1	Uolevi Nikula, Petri Oinonen, Lea Hannola	Extending Process Improvement into a New Organizational Unit.	Australian Software Engineering Conference	2009	DBLP DOI BibTeX RDF
1	Yi-Chi Chen, Hui-Chin Yang, Chung-Ping Chung, Wei-Ting Wang	Dynamic Reconfigurable Shaders with Load Balancing for Embedded Graphics Processing.	CSE	2009	DBLP DOI BibTeX RDF
1	Bian Wu, Minhong Wang, Hongmin Yun, Haijing Jiang	An agent-based cognitive approach for healthcare process management.	IEEE ICCI	2009	DBLP DOI BibTeX RDF
1	Ricardo S. Ferreira, Marcone Laure, Antonio Carlos Schneider Beck, Thiago Lo, Mateus B. Rutzig, Luigi Carro	A low cost and adaptable routing network for reconfigurable systems.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Young-Duk Kim, Yoon-Gu Kim, Seung-Hyun Lee, Jeong-Ho Kang, Jinung An	Portable fire evacuation guide robot system.	IROS	2009	DBLP DOI BibTeX RDF
1	Syed M. Alam, Robert E. Jones, Scott Pozder, Ankur Jain	Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology.	ISQED	2009	DBLP DOI BibTeX RDF
1	António Gusmão, L. Miguel Silveira, José C. Monteiro	Parameter tuning in SVM-based power macro-modeling.	ISQED	2009	DBLP DOI BibTeX RDF
1	Hua Wang, Ke Zhou, Ling Yuan	Fault-Tolerant Online Backup Service: Formal Modeling and Reasoning.	NAS	2009	DBLP DOI BibTeX RDF
1	Tyrel Russell, Abid M. Malik, Michael Chase, Peter van Beek	Learning Heuristics for the Superblock Instruction Scheduling Problem.	IEEE Trans. Knowl. Data Eng.	2009	DBLP DOI BibTeX RDF
1	Sylvain Cussat-Blanc, Hervé Luga, Yves Duthen	Making a Self-feeding Structure by Assembly of Digital Organs.	ACAL	2009	DBLP DOI BibTeX RDF