Search results for "functional validation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Fulvio Corno, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero	Code Generation for Functional Validation of Pipelined Microprocessors.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	pipelined micro processors, evolutionary algorithms, functional validation, automatic test program generation
3	Guofei Jiang, George Cybenko	Functional Validation in Grid Computing.	Autonomous Agents and Multi-Agent Systems	2004	DBLP DOI BibTeX RDF	keywords and ontology, grid computing, PAC learning, service matching, functional validation
2	Heon-Mo Koo, Prabhat Mishra	Specification-based compaction of directed tests for functional validation of pipelined processors.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	processor validation, test compaction
2	Prabhat Mishra, Nikil Dutt	Specification-driven directed test generation for validation of pipelined processors.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Model checking, test generation, functional validation
2	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou	Observability Analysis on HDL Descriptions for Effective Functional Validation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Todd J. Foster, Dennis L. Lastor, Padmaraj Singh	First Silicon Functional Validation and Debug of Multicore Microprocessors.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Tommy Bojan, Igor Frumkin, Robert Mauri	Intel First Ever Converged Core Functional Validation Experience: Methodologies, Challenges, Results and Learning.	MTV	2007	DBLP DOI BibTeX RDF
2	Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang	Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	hybrid technique, simulation, formal verification, functional validation
2	Samar Abdi, Daniel D. Gajski	Functional Validation of System Level Static Scheduling.	DATE	2005	DBLP DOI BibTeX RDF
2	Serdar Tasiran, Kurt Keutzer	Coverage Metrics for Functional Validation of Hardware Designs.	IEEE Design & Test of Computers	2001	DBLP DOI BibTeX RDF
2	Jan Hlavicka, Stanislav Racek, Pavel Smrha	Functional Validation of Fault-Tolerant Asynchronous Algorithms.	EUROMICRO	1996	DBLP DOI BibTeX RDF	fault-tolerant asynchronous algorithms, distributed asynchronous algorithms, algorithm correctness, process-oriented discrete simulation, fault injector, C-based validation tool, C-Sim, C-coded implementation, distributed election algorithm, formal specification, communication channels, time behavior, functional validation, state observer, failure semantics
1	Taejong Yoo, Buhwan Jeong, Hyunbo Cho	A Petri Nets based functional validation for services composition.	Expert Syst. Appl.	2010	DBLP DOI BibTeX RDF
1	Mathias Moehring, Bernd Froehlich	Enabling functional validation of virtual cars through Natural Interaction metaphors.	VR	2010	DBLP DOI BibTeX RDF
1	Jing Liu, Xinming Ye, Jun Li	Analyzing Performance for Complex Protocol using Validated CP-nets Models.	CIT	2010	DBLP DOI BibTeX RDF	complex protocol, performance analysis, colored Petri nets, functional validation
1	Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Giovanni Squillero	Design validation of multithreaded architectures using concurrent threads evolution.	SBCCI	2009	DBLP DOI BibTeX RDF	simulation based techniques, functional validation
1	Heon-Mo Koo, Prabhat Mishra	Functional test generation using design and property decomposition techniques.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	design decomposition, property decomposition, Model checking, test generation, pipelined processor, functional validation
1	Patrice Gerin, Mian Muhammad Hamayun, Frédéric Pétrot	Native MPSoC co-simulation environment for software performance estimation.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	code annotation, MPSoC, system simulation, cross-compilation
1	Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra	Generating test programs to cover pipeline interactions.	DAC	2009	DBLP DOI BibTeX RDF	pipelines, automated test generation, state space exploration
1	M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter Kollig	Design of a low power MPEG-1 motion vector reconstructor.	SBCCI	2009	DBLP DOI BibTeX RDF	behavioural synthesis, low power
1	Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton	Instruction set simulator generation using HARMLESS, a new hardware architecture description language.	SimuTools	2009	DBLP DOI BibTeX RDF	hardware architecture description language, instruction set simulation
1	Andrew DeOrio, Ilya Wagner, Valeria Bertacco	Dacota: Post-silicon validation of the memory subsystem in multi-core designs.	HPCA	2009	DBLP DOI BibTeX RDF
1	Prabhat Mishra, Mingsong Chen	Efficient Techniques for Directed Test Generation Using Incremental Satisfiability.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Nathaniel August	A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intels Test Chips.	ISQED	2008	DBLP DOI BibTeX RDF	pre-silicon, validation, mixed-signal
1	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Incremental ABV for functional validation of TL-to-RTL design refinement.	DATE	2007	DBLP DOI BibTeX RDF
1	Yi Feng 0003, Zheng Zhou, Dong Tong, Xu Cheng	Clock domain crossing fault model and coverage metric for validation of SoC design.	DATE	2007	DBLP DOI BibTeX RDF
1	Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V. Kodakara, David J. Lilja, Ajit Dingankar	Design fault directed test generation for microprocessor validation.	DATE	2007	DBLP DOI BibTeX RDF
1	Kathy Dang Nguyen, P. S. Thiagarajan, Weng-Fai Wong	A UML-Based Design Framework for Time-Triggered Applications.	RTSS	2007	DBLP DOI BibTeX RDF
1	Hideya Ochiai, Zhiyong Wang, Ryo Oguchi, Tetsuhiro Sugiyama, Yusuke Sakamoto, Shinichi Ishida, Hiroshi Esaki	Application of Content-Based Network for Sensor Data Distribution System.	SAINT Workshops	2007	DBLP DOI BibTeX RDF	CBN, Sensor Network
1	Samarjit Chakraborty, Abhik Roychoudhury	Tutorial T8B: Performance Debugging of Complex Embedded Systems.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja	Model Based Test Generation for Microprocessor Architecture Validation.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Youssef Serrestou, Vincent Beroulle, Chantal Robach	Impact of hardware emulation on the verification quality improvement.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Jian Kang, Sharad C. Seth, Vijay Gangaram	Efficient RTL Coverage Metric for Functional Test Selection.	VTS	2007	DBLP DOI BibTeX RDF
1	Vittorio Cortellessa, Antinisca Di Marco, Paola Inverardi	Non-Functional Modeling and Validation in Model-Driven Architecture.	WICSA	2007	DBLP DOI BibTeX RDF
1	Vittorio Cortellessa, Antinisca Di Marco, Paola Inverardi	Integrating Performance and Reliability Analysis in a Non-Functional MDA Framework.	FASE	2007	DBLP DOI BibTeX RDF
1	Yvon Resplandy	Use of a computer algebra software in the functional validation of continuous simulations.	Winter Simulation Conference	2006	DBLP DOI BibTeX RDF
1	Heon-Mo Koo, Prabhat Mishra	Test generation using SAT-based bounded model checking for validation of pipelined processors.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	test generation, functional validation
1	Heon-Mo Koo, Prabhat Mishra	Functional test generation using property decompositions for validation of pipelined processors.	DATE	2006	DBLP DOI BibTeX RDF
1	Jaime Martín Serrano, Joan Serrat, Alex Galis	Ontology-Based Context Information Modelling for Managing Pervasive Applications.	ICAS	2006	DBLP DOI BibTeX RDF
1	Alexander Kamkin	The UniTESK Approach to Specification-Based Validation of Hardware Designs.	ISoLA	2006	DBLP DOI BibTeX RDF
1	Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli	EFSM Manipulation to Increase High-Level ATPG Effectiveness.	ISQED	2006	DBLP DOI BibTeX RDF
1	Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir	Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study.	MTV	2006	DBLP DOI BibTeX RDF
1	J. B. Pérez-Ramas, David Atienza, Miguel Peón Quirós, Ivan Magan, Jose Manuel Mendias, Román Hermida	Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs.	PARCO	2005	DBLP BibTeX RDF
1	Arjun K. Pai, Khaled Benkrid, Danny Crookes	Embedded Reconfigurable DCT Architectures Using Adder-Based Distributed Arithmetic.	CAMP	2005	DBLP DOI BibTeX RDF
1	Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor	A Complete Network-On-Chip Emulation Framework.	DATE	2005	DBLP DOI BibTeX RDF
1	Sérgio Martins, José Carlos Alves	A high-level tool for the design of custom image processing systems.	DSD	2005	DBLP DOI BibTeX RDF
1	Phan C. Vinh, Jonathan P. Bowen	Semantics of RTL and Validation of Synthesized RTL Designs Using Formal Verification in Reconfigurable Computing Systems.	ECBS	2005	DBLP DOI BibTeX RDF
1	Pasquale di Tommaso, Francesco Flammini, Armando Lazzaro, Raffaele Pellecchia, Angela Sanseviero	The Simulation of Anomalies in the Functional Testing of the ERTMS/ETCS Trackside System.	HASE	2005	DBLP DOI BibTeX RDF	ERTMS/ETCS, Verification & Validation, Safety-Critical Systems, Functional Testing, Simulation Environments
1	Daniel Pakkala, Pekka Pääkkönen, Markus Sihvonen	A Generic Communication Middleware Architecture for Distributed Application and Service Messaging.	ICAS/ICNS	2005	DBLP DOI BibTeX RDF
1	Elena Dubrova	Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programs.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor	A novel approach for network on chip emulation.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Prabhat Mishra, Heon-Mo Koo, Zhuo Huang	Language-driven Validation of Pipelined Processors using Satisfiability Solvers.	MTV	2005	DBLP DOI BibTeX RDF
1	Ivan Augé, Frédéric Pétrot, François Donnet, Pascal Gomez	Platform-based design from parallel C specifications.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Prabhat Mishra, Nikil D. Dutt	Functional Validation of Programmable Architectures.	DSD	2004	DBLP DOI BibTeX RDF
1	José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Teixeira	A Probabilistic Method for the Computation of Testability of RTL Constructs.	DATE	2004	DBLP DOI BibTeX RDF
1	B. Hecker, M. Chavassieux, M. Laflutte, E. Beguin, L. Lagasse, Jean Oudinot	VHDL-AMS Library Development for Pacemaker Applications.	DATE	2004	DBLP DOI BibTeX RDF
1	Qibin Mei, Chengbo Wang, Xiaolan Mei	Description Mathematical Approach to Validation for Grid Service Matching Function.	Web Intelligence	2004	DBLP DOI BibTeX RDF
1	Hoonmo Yang, Moonkey Lee	Design of a Cycle-Accurate User-Retargetable Instruction-Set Simulator Using Process-Based Scheduling Scheme.	CIS	2004	DBLP DOI BibTeX RDF
1	Kanna Shimizu, David L. Dill	Using Formal Specifications for Functional Validation of Hardware Designs.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
1	Aarti Gupta, Albert E. Casavant, Pranav Ashar, X. G. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi	Property-Specific Testbench Generation for Guided Simulation.	VLSI Design	2002	DBLP DOI BibTeX RDF	guided simulation, intelligent testbench generation, witness graph, property-specific testbench, approximate model checking, symbolic model checking, iterative refinement
1	Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer	A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage.	ICCD	2001	DBLP BibTeX RDF
1	Laurent Arditi, Hédi Boufaïed, Arnaud Cavanié, Vincent Stehlé	Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System.	FME	2001	DBLP DOI BibTeX RDF
1	Anna Slobodová	Formal Verification Methods for Industrial Hardware Design.	SOFSEM	2001	DBLP DOI BibTeX RDF
1	Axel Jantsch, Johann Notbauer, Thomas W. Albrecht	Functional Validation of Mixed Hardware/Software Systems based on Specification, Partitioning, and Simulation of Test Cases.	Design Autom. for Emb. Sys.	2000	DBLP DOI BibTeX RDF
1	Luc Hohwiller, Serge Wendling	Fieldbus Network Simulation Using a Time Extended Estelle Formalism. (PDF / PS)	MASCOTS	2000	DBLP DOI BibTeX RDF
1	P. Poure, F. Aubépart, F. Braun	A Design Methodology for Hardware Prototyping of Integrated AC Drive Control: Application to Direct Torque Control of an Induction Machine. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF
1	Pradip Bose	Testing for Function and Performance: Towards an Integrated Processor Validation Methodology.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	performance test cases, bounds modeling, performance validation, integrated methodology, test generation, microprocessor testing
1	Jules P. Bergmann, Mark Horowitz	Improving coverage analysis and test generation for large designs.	ICCAD	1999	DBLP BibTeX RDF
1	Aarti Gupta, Pranav Ashar, Sharad Malik	Exploiting Retiming in a Guided Simulation Based Validation Methodology.	CHARME	1999	DBLP DOI BibTeX RDF
1	Teresa Riesgo, Yago Torroja, Eduardo de la Torre, J. Uceda	Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models.	DATE	1998	DBLP DOI BibTeX RDF	VHDL, Fault modelling, Design validation, Design errors
1	Rachid Helaihel, Kunle Olukotun	Java as a specification language for hardware-software systems.	ICCAD	1997	DBLP DOI BibTeX RDF	java, Java, specification languages, hardware-software co-design
1	Ranga Vemuri, Paddy Mamtora, Praveen Sinha, Nand Kumar, Jayanta Roy, Raghu Vutukuru	Experiences in Functional Validation of a High Level Synthesis System.	DAC	1993	DBLP DOI BibTeX RDF	VHDL