Search results for "functional verification"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	George Sobral Silveira, Alisson Vasconcelos De Brito, Elmar U. K. Melcher	Functional verification of power gate design in SystemC RTL.	SBCCI	2009	DBLP DOI BibTeX RDF	simulation, SystemC, RTL, functional verification, power gate
3	Cássio L. Rodrigues, Karina R. G. da Silva, Henrique do N. Cunha	Improving functional verification of embedded systems using hierarchical composition and set theory.	SAC	2009	DBLP DOI BibTeX RDF	hierarchical composition, embedded systems, set theory, functional verification, functional coverage
3	Kwang-Ting (Tim) Cheng	Cocktail approach to functional verification.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	validation, functional verification, multiprocessor SoC, SiP, BISR
3	Guy Dupenloup, Thierry Lemeunier, Roland Mayr	Transistor abstraction for the functional verification of FPGAs.	DAC	2006	DBLP DOI BibTeX RDF	cone model, logic equivalence checking, transistor abstraction, FPGA, register transfer level, multiplexer, functional verification
3	Francesco Bruschi, Fabrizio Ferrandi, Donatella Sciuto	A Framework for the Functional Verification of SystemC Models.	International Journal of Parallel Programming	2005	DBLP DOI BibTeX RDF	SystemC, test pattern generator, Functional verification
3	Edgar L. Romero, Marius Strum, Wang Jiang Chau	Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	verification strategy, optimization, functional verification, coverage analysis, hierarchical verification
3	Shai Fine, Avi Ziv	Coverage directed test generation for functional verification using bayesian networks.	DAC	2003	DBLP DOI BibTeX RDF	bayesian networks, functional verification, coverage analysis
3	Satoshi Matsushita	Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification.	ISSS	2002	DBLP DOI BibTeX RDF	deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading
3	William L. Bradley, Ranga Vemuri	Transformations for functional verification of synthesized designs.	VLSI Design	1995	DBLP DOI BibTeX RDF	low-level functional verification, synthesized designs, clocking mechanisms, provably equivalent model, hierarchical network of modules, reduced state set, de-phase transform, align transform, algorithm, formal verification, transforms, transforms, logic CAD, clocks, hierarchical system, reachable states
2	Jing Liu, Xinming Ye, Jun Li	CP-Nets Based Methodology for Integrating Functional Verification and Performance Analysis of Network Protocol.	SNPD	2010	DBLP DOI BibTeX RDF	BitTorrent protocol, performance analysis, colored Petri nets, functional verification
2	Kenneth S. Kundert, Henry Chang	Model-based functional verification.	DAC	2010	DBLP DOI BibTeX RDF
2	Yingpan Wu, Lixin Yu, Wei Zhuang, Jianyong Wang	A Coverage-Driven Constraint Random-Based Functional Verification Method of Pipeline Unit.	ACIS-ICIS	2009	DBLP DOI BibTeX RDF
2	Michael Siegel, Adriana Maggiore, Christian Pichler	Untwist your brain: efficient debugging and diagnosis of complex assertions.	DAC	2009	DBLP DOI BibTeX RDF	SystemVerilog assertions, debugging, assertions, fault localization, functional verification, root cause analysis
2	Carlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau	A PD-based methodology to enhance efficiency in testbenches with random stimulation.	SBCCI	2009	DBLP DOI BibTeX RDF	parameter domains, system-on-chip, design methodologies, functional verification, coverage analysis
2	Michael Katelman, José Meseguer, Santiago Escobar	Directed-Logical Testing for Functional Verification of Microprocessors.	MEMOCODE	2008	DBLP DOI BibTeX RDF
2	Primoz Puhar, Andrej Zemva	Functional Verification of a USB Host Controller.	DSD	2008	DBLP DOI BibTeX RDF
2	Hossein Hojjat, Mohammad Reza Mousavi, Marjan Sirjani	A framework for performance evaluation and functional verification in stochastic process algebras.	SAC	2008	DBLP DOI BibTeX RDF
2	Eyad Alkassar, Mark A. Hillebrand	Formal Functional Verification of Device Drivers.	VSTTE	2008	DBLP DOI BibTeX RDF
2	Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Foster	Functional test selection based on unsupervised support vector analysis.	DAC	2008	DBLP DOI BibTeX RDF	learning, functional verification, support vector
2	Andrea Fedeli, Franco Fummi, Graziano Pravadelli	Properties Incompleteness Evaluation by Functional Verification.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	property coverage, Model checking, fault models, functional verification
2	Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray	A Survey of Hybrid Techniques for Functional Verification.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	informal techniques, hybrid, functional verification, formal techniques
2	Chin-Lung Chuang, Wei-Hsiang Cheng, Dong-Jung Lu, Chien-Nan Jimmy Liu	Hybrid Approach to Faster Functional Verification with Full Visibility.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	simulator, emulator, visibility, hybrid, functional verification, debugging environment
2	George Sobral Silveira, Karina R. G. da Silva, Elmar U. K. Melcher	Functional verification of an MPEG-4 decoder design using a random constrained movie generator.	SBCCI	2007	DBLP DOI BibTeX RDF	VeriSC, randmovie, stimuli, verification, SystemC, movie, functional coverage
2	Youssef Serrestou, Vincent Beroulle, Chantal Robach	Functional Verification of RTL Designs driven by Mutation Testing metrics.	DSD	2007	DBLP DOI BibTeX RDF
2	Oleg Petlin, Wilson Snyder	Functional Verification of SiCortex Multiprocessor System-on-a-Chip.	DAC	2007	DBLP DOI BibTeX RDF
2	Jianfeng An, Xiaoya Fan, Shengbing Zhang, Danghui Wang, Yi Wang	VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification.	ITNG	2006	DBLP DOI BibTeX RDF
2	Tathagato Rai Dastidar, Partha Ray	A New Device Level Digital Simulator for Simulation and Functional Verification of Large Semiconductor Memories.	VLSI Design	2006	DBLP DOI BibTeX RDF
2	Vasco Jerinic, Jan Langer, Ulrich Heinkel, Dietmar Müller	New methods and coverage metrics for functional verification.	DATE	2006	DBLP DOI BibTeX RDF
2	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Functional Verification of Networked Embedded Systems.	ISQED	2005	DBLP DOI BibTeX RDF
2	Sanggyu Park, Soo-Ik Chae	A C/C++-Based Functional Verification Framework Using the SystemC Verification Library.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
2	Iñigo Ugarte, Pablo Sanchez	Extended abstract: polynomial model-based evaluation of the branch coverage metric for functional verification of hardware systems.	MEMOCODE	2005	DBLP DOI BibTeX RDF
2	Hao Shen, Yuzhuo Fu	Priority directed test generation for functional verification using neural networks.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Grant Martin	Verification by the pound.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	complex ICs, verification methodologies, hardware verification languages, formal verification, functional verification, dynamic verification
2	Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir	Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation.	IEEE Design & Test of Computers	2004	DBLP DOI BibTeX RDF
2	Karina R. G. da Silva, Elmar U. K. Melcher, Guido Araujo, Valdiney Alves Pimenta	An automatic testbench generation tool for a SystemC functional verification methodology.	SBCCI	2004	DBLP DOI BibTeX RDF	Brazilip, SCV, VeriSC, tool, SystemC
2	Shai Fine, Shmuel Ur, Avi Ziv	Probabilistic regression suites for functional verification.	DAC	2004	DBLP DOI BibTeX RDF	regression suite, functional verification, coverage analysis
2	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	At-Speed Functional Verification of Programmable Devices.	DFT	2004	DBLP DOI BibTeX RDF
2	Prabhat Mishra, Nikil D. Dutt, Yaron Kashai	Functional Verification of Pipelined Processors: A Case Study.	MTV	2004	DBLP DOI BibTeX RDF
2	Franco Fummi, Graziano Pravadelli	Logic-level analysis of high-level faults.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	fault models, functional verification
2	Amir Hekmatpour, James Coulter	Coverage-Directed Management and Optimization of Random Functional Verification.	ITC	2003	DBLP DOI BibTeX RDF
2	F. Hunsinger, Sebastien Francois, Ahmed Amine Jerraya	Definition of a systematic method for the generation of software test programs allowing the functional verification of System On Chip (SoC).	MTV	2003	DBLP DOI BibTeX RDF
2	Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan	Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).	VLSI Design	2002	DBLP DOI BibTeX RDF
2	Surrendra Dudani, Jayant Nagda	High Level Functional Verification Closure.	ICCD	2002	DBLP DOI BibTeX RDF
2	Farzan Fallah, Srinivas Devadas, Kurt Keutzer	OCCOM-efficient computation of observability-based code coveragemetrics for functional verification.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
2	F. Sforza, L. Battú, M. Brunelli, A. Castelnuovo, M. Magnaghi	A "Design for Verification" Methodology.	ISQED	2001	DBLP DOI BibTeX RDF	IP re-use, simulation, prototyping, emulation, functional verification, testbenches
2	Laurent Fournier, Yaron Arbetman, Moshe Levinger	Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family.	DATE	1999	DBLP DOI BibTeX RDF
2	Jainendra Kumar, Carl Pixley	Logic and Functional Verification in a Commercial Semiconductor Environment.	ACSD	1998	DBLP DOI BibTeX RDF
2	Farzan Fallah, Srinivas Devadas, Kurt Keutzer	OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification.	DAC	1998	DBLP DOI BibTeX RDF	high-level synthesis, telecommunication
2	Scott A. Taylor, Michael Quinn, Darren Brown, Nathan Dohm, Scot Hildebrandt, James Huggins, Carl Ramey	Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor - The DEC Alpha 21264 Microprocessor.	DAC	1998	DBLP DOI BibTeX RDF	21264, coverage anaysis, verification, architecture, validation, microprocessor, pseudo-random, Alpha
2	Adrian Evans, Allan Silburt, Gary Vrckovnik, Thane Brown, Mario Dufresne, Geoffrey Hall, Tung Ho, Ying Liu	Functional Verification of Large ASICs.	DAC	1998	DBLP DOI BibTeX RDF	ASIC verification, simulation, emulation
2	Xiao Sun, Carmie Hull	Functional Verification Coverage vs. Physical Stuck-at Fault Coverage. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	functional property, stuck-at fault coverage, verification coverage, UIO, verification, validation, ATPG, FSM, signature analysis, test application time
2	Elizabeth J. Brauer, Sung-Mo Kang	An algorithm for functional verification of digital ECL circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Christopher A. Krygowski, Eli Almog, Dean G. Bair, R. Breil, G. Dittmann, Rebecca M. Gott, William J. Lewis, A. D. Shah, Brian W. Thompto	Key advances in the presilicon functional verification of the IBM zEnterprise microprocessor and storage hierarchy.	IBM Journal of Research and Development	2012	DBLP DOI BibTeX RDF
1	Vladimir Zlokolica, Nebojsa Milutinovic, Vladimir Marinkovic, Vukota Pekovic, Jan Zloh	Automatic Set-Top Box Menu Navigation Scheme for STB Menu Functional Verification.	ECBS	2012	DBLP DOI BibTeX RDF
1	Nicola Bombieri, Franco Fummi, Valerio Guarnieri	FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs.	DATE	2012	DBLP BibTeX RDF
1	Michelangelo Grosso, Wilson Javier Perez Holguin, Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda, Jaime Velasco-Medina	Functional Verification of DMA Controllers.	J. Electronic Testing	2011	DBLP DOI BibTeX RDF
1	Carlos Ivan Castro Marquez, Edgar Leonardo Romero Tobar, Marius Strum, Wang Jiang Chau	A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling.	J. Electronic Testing	2011	DBLP DOI BibTeX RDF
1	Giuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli	Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs.	J. Electronic Testing	2011	DBLP DOI BibTeX RDF
1	Michael D. Moffitt, Gernot E. Günther	Scalable Scheduling for Hardware-Accelerated Functional Verification.	ICAPS	2011	DBLP BibTeX RDF
1	Michael D. Moffitt, Mátyás A. Sustik, Paul G. Villarrubia	Robust partitioning for hardware-accelerated functional verification.	DAC	2011	DBLP DOI BibTeX RDF
1	Lingkan Gong, Oliver Diessel	Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification.	FCCM	2011	DBLP DOI BibTeX RDF
1	YuHan Gao, LinTao Liu, RuZhang Li	Model Based Comprehensive Functional Verification of RF SoC.	ICDMA	2011	DBLP DOI BibTeX RDF
1	Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Foster	Increasing the Efficiency of Simulation-Based Functional Verification Through Unsupervised Support Vector Analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Jianwu Wu	Functional Verification Methodology of Complex Electronics System Based Modeling and Simulation.	JCP	2010	DBLP DOI BibTeX RDF
1	Qi Guo, Tianshi Chen, Haihua Shen, Yunji Chen, Weiwu Hu	On-the-Fly Reduction of Stimuli for Functional Verification.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Stefano Soffia, Marco Roveri	Semi-formal functional verification by EFSM traversing via NuSMV.	HLDVT	2010	DBLP DOI BibTeX RDF
1	Jing Liu, Xinming Ye, Jun Zhang 0001, Jun Li, Yi Sun	Integrating functional verification and performance analysis for network protocols using CP-nets.	ISCC	2010	DBLP DOI BibTeX RDF
1	Jonathan B. David	Radio receiver mixer model for event-driven simulators to support functional verification of RF-SOC wireless links.	BMAS	2010	DBLP DOI BibTeX RDF
1	Morteza Fayyazi, Laurent Kirsch	Efficient simulation of oscillatory combinational loops.	DAC	2010	DBLP DOI BibTeX RDF	oscillatory combinational loops, emulation, functional verification
1	Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor	Bridging pre-silicon verification and post-silicon validation.	DAC	2010	DBLP DOI BibTeX RDF	post-silicon, pre-silicon, verification, validation
1	Brian W. Thompto, Bodo Hoppe	Verification for fault tolerance of the IBM system z microprocessor.	DAC	2010	DBLP DOI BibTeX RDF	CFI, error detection, fault injection, error recovery, SER, RAS
1	Jun Wu, Yong-Bin Kim, Minsu Choi	Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	substitution box, substitution box (S-box), differential power/noise analysis, power/noise measurement, security, advanced encryption standard, advanced encryption standard, side-channel attacks (SCA), null convention logic
1	Gabor Madl, Sudeep Pasricha, Nikil Dutt, Sherif Abdelwahed	Cross-abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs.	IEEE Trans. Industrial Informatics	2009	DBLP DOI BibTeX RDF
1	Yifan Wang, Stefan Joeres, Ralf Wunderlich, Stefan Heinen	Modeling Approaches for Functional Verification of RF-SoCs: Limits and Future Requirements.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Christopher A. Krygowski, Dean G. Bair, Rebecca M. Gott, M. H. Decker, A. V. Giri, Christian Habermann, Matthias Heizmann, Stefan Letz, William J. Lewis, Steven M. Licker, H. Mallar, Edward C. McCain, Wolfgang Roesner, N. Siddique, A. E. Seigler, Brian W. Thompto, K. Weber, Ralf Winkelmann	Functional verification of the IBM System z10 processor chipset.	IBM Journal of Research and Development	2009	DBLP DOI BibTeX RDF
1	Osman Hasan, Sofiène Tahar	Performance Analysis and Functional Verification of the Stop-and-Wait Protocol in HOL.	J. Autom. Reasoning	2009	DBLP DOI BibTeX RDF	Real-time systems, Communication protocols, Higher-order-logic, Probability theory, HOL theorem prover
1	Cindy Eisner, Amir Nahir, Karen Yorav	Functional verification of power gated designs by compositional reasoning.	Formal Methods in System Design	2009	DBLP DOI BibTeX RDF
1	Andrew Piziali	Panel: Functional Verification Planning and Management - Are Good Intentions Good Enough?	VTS	2009	DBLP DOI BibTeX RDF
1	Yassine Aydi, Ramzi Tligue, Maissa Elleuch, Mohamed Abid, Jean-Luc Dekeyser	A multi level functional verification of multistage interconnection network for MPSOC.	ICECS	2009	DBLP DOI BibTeX RDF
1	Harry Foster	Pain, Possibilities, and Prescriptions Industry Trends in Advanced Functional Verification.	Haifa Verification Conference	2009	DBLP DOI BibTeX RDF
1	Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong	Guess, solder, measure, repeat: how do I get my mixed-signal chip right?	DAC	2009	DBLP DOI BibTeX RDF	Verilog-AMS, analog behavioral modeling, low power verification, mixed-signal verification, VHDL, SPICE, functional verification, Verilog, performance verification
1	P. Subramanian, Jagonda Patil, Manish Kumar Saxena	FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications.	IWCMC	2009	DBLP DOI BibTeX RDF	ECMA-368, FPGA-physical implementation, FPGA-synthesis, SoC (system-on-chip), synthesis constraints, FPGA, ASIC (application specific integrated circuits), functional verification, clock gating
1	Benny Godlin, Ofer Strichman	Regression verification.	DAC	2009	DBLP DOI BibTeX RDF	software verification, equivalence checking
1	Jürgen Sommer, Simon Lüders, Suguna Subramanian, Stephen Schmitt, Wolfgang Rosenstiel	SySifoS: SystemC simulator for sensor and communication systems.	Mobility Conference	2009	DBLP DOI BibTeX RDF	short range communication, sensor networks, pervasive computing, wireless communication, network simulation, indoor localization
1	Armen Kostanyan, Vardan Matevosyan, Samvel K. Shoukourian, Anna Varosyan	An approach for formal verification of business processes.	SpringSim	2009	DBLP DOI BibTeX RDF	cycle transformation, formal verification, business process
1	Heon-Mo Koo, Prabhat Mishra	Functional test generation using design and property decomposition techniques.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	design decomposition, property decomposition, Model checking, test generation, pipelined processor, functional validation
1	Yokesh Kumar, Prosenjit Gupta	External memory layout vs. schematic.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	verification of layouts, Graph, design automation, external memory algorithms, subgraph isomorphism
1	Bharathram Sivasubramanian, Warren J. Gross, Harry Leib	Design and FPGA implementation of iterative decoders for codes on graphs.	CCECE	2009	DBLP DOI BibTeX RDF
1	Brian Keng, Andreas G. Veneris	Scaling VLSI design debugging with interpolation.	FMCAD	2009	DBLP DOI BibTeX RDF
1	Anmol Mathur, Qi Wang	Power Reduction Techniques and Flows at RTL and System Level.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Nicolas Coste, Holger Hermanns, Etienne Lantreibecq, Wendelin Serwe	Towards Performance Prediction of Compositional Models in Industrial GALS Designs.	CAV	2009	DBLP DOI BibTeX RDF
1	Ofer Strichman	Regression Verification: Proving the Equivalence of Similar Programs.	CAV	2009	DBLP DOI BibTeX RDF
1	Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi	Graph based test case generation for TLM functional verification.	Microprocessors and Microsystems - Embedded Hardware Design	2008	DBLP DOI BibTeX RDF
1	Mihaela Elena Radu, Shannon M. Sexton	Integrating Extensive Functional Verification Into Digital Design Education.	IEEE Trans. Education	2008	DBLP DOI BibTeX RDF
1	Karen Zee, Viktor Kuncak, Martin C. Rinard	Full functional verification of linked data structures.	PLDI	2008	DBLP DOI BibTeX RDF	java, verification, data structure, decision procedure, theorem prover
1	Colin Yu Lin, Song Cao, Junshe An, Fei Han, Qifei Fan	A Network Based Functional Verification Method of IEEE 1394a PHY Core.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Yingpan Wu, Lixin Yu, Lidong Lan, Haiyang Zhou	A Coverage-Driven Constraint Random-Based Functional Verification Method of Memory Controller.	IEEE International Workshop on Rapid System Prototyping	2008	DBLP DOI BibTeX RDF
1	George Sobral Silveira, Karina R. G. da Silva, Elmar U. K. Melcher	A Random Constrained Movie Versus a Random Unconstrained Movie Applied to the Functional Verification of an MPEG-4 Decoder Design.	SIGMAP	2008	DBLP BibTeX RDF
1	Cindy Eisner, Amir Nahir, Karen Yorav	Functional Verification of Power Gated Designs by Compositional Reasoning.	CAV	2008	DBLP DOI BibTeX RDF
1	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	TBV, Model checking, fault models, functional verification, TLM