Search results for "gate level"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Lifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike, Hirokazu Yonezawa, Yoshiyuki Kawakami	GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design.	ISQED	2000	DBLP DOI BibTeX RDF	Hot Carrier Effect, Gate level modeling, Gate level simulation, Circuit reliability simulation, VLSI
4	Ghassan Al Hayek, Chantal Robach	On the Adequacy of Deriving Hardware Test Data from the Behavioral Specification.	EUROMICRO	1996	DBLP DOI BibTeX RDF	hardware test data, behavioral fault modeling, gate-level strategies, high-level fault detection, gate-level fault detection, design automation tools, generated test set, gate-level fault coverage, hardware description languages, hardware description languages, behavioral specification
3	Sheng Wei, Saro Meguerdichian, Miodrag Potkonjak	Gate-level characterization: foundations and hardware security applications.	DAC	2010	DBLP DOI BibTeX RDF	gate-level characterization, hardware Trojan horse, thermal conditioning, manufacturing variability
3	Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco	Event-driven gate-level simulation with GP-GPUs.	DAC	2009	DBLP DOI BibTeX RDF	gate-level simulation, general purpose graphics processing unit (GP-GPU), high-performance simulation
3	Mu-Shun Matt Lee, Chin-Hsun Lin, Chien-Nan Jimmy Liu, Shih-Che Lin	Quick supply current waveform estimation at gate level using existed cell library information.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	current waveform estimation, gate-level
3	Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng	Automatic synthesis of gate-level timed circuits with choice.	ARVLSI	1995	DBLP DOI BibTeX RDF	gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
3	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
3	Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey	A simple technique for locating gate-level faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electron probe analysis, optical microscopy, gate-level faults, error sources, fault deduction, fault elimination, ISCAS'85 benchmark circuits, physical defect analysis, electron beam probing, light emission microscopy, computational complexity, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, digital simulation, circuit analysis computing, computation time, scanning electron microscopy, scanning electron microscopy, diagnostic resolution
3	Scott Woods, Giorgio Casinovi	Gate-level simulation of digital circuits using multi-valued Boolean algebras.	ICCAD	1995	DBLP DOI BibTeX RDF	Gate-level logic simulation, mixed-mode simulation, boolean equations solution, multi-valued logic
2	Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Ryan Kastner	Theoretical analysis of gate level information flow tracking.	DAC	2010	DBLP DOI BibTeX RDF	hardware security, Boolean logic, information flow tracking
2	Mark A. Hillebrand, Sergey Tverdyshev	Formal Verification of Gate-Level Computer Systems.	CSR	2009	DBLP DOI BibTeX RDF
2	Sriram Sambamurthy, Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham	Functionally valid gate-level peak power estimation for processors.	ISQED	2009	DBLP DOI BibTeX RDF
2	Sergey Tverdyshev	A verified platform for a gate-level electronic control unit.	FMCAD	2009	DBLP DOI BibTeX RDF
2	MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada	Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dcvsl, high speed digital, pipeline, error detect, soft error
2	Miodrag Potkonjak, Ani Nahapetian, Michael Nelson, Tammara Massey	Hardware Trojan horse detection using gate-level characterization.	DAC	2009	DBLP DOI BibTeX RDF	Hardware Trojan horses, gate-level characterization, linear programming, manufacturing variability
2	Mohit Tiwari, Hassan M. G. Wassel, Bita Mazloom, Shashidhar Mysore, Frederic T. Chong, Timothy Sherwood	Complete information flow tracking from the gates up.	ASPLOS	2009	DBLP DOI BibTeX RDF	provably sound, gate level, information flow tracking
2	Mohit Tiwari, Xun Li 0001, Hassan M. G. Wassel, Frederic T. Chong, Timothy Sherwood	Execution leases: a hardware-supported mechanism for enforcing strong non-interference.	MICRO	2009	DBLP DOI BibTeX RDF	gate level information flow tracking, covert channels, high assurance systems, timing channels
2	Shengchao Ding, Zhi Jin, Qing Yang	Evolving quantum circuits at the gate level with a hybrid quantum-inspired evolutionary algorithm.	Soft Comput.	2008	DBLP DOI BibTeX RDF	Quantum circuits design, Optimization, Evolutionary algorithm
2	Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw	A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Lijun Li, Carl Tropper	A Multiway Partitioning Algorithm for Parallel Gate Level Verilog Simulation.	ICPP	2008	DBLP DOI BibTeX RDF
2	Eyad Alkassar, Peter Böhm, Steffen Knapp	Formal Correctness of an Automotive Bus Controller Implementation at Gate-Level.	DIPES	2008	DBLP DOI BibTeX RDF
2	Xin Wang, Alireza Kasnavi, Harold Levy	An Efficient Method for Fast Delay and SI Calculation Using Current Source Models.	ISQED	2008	DBLP DOI BibTeX RDF	Delay calculation, gate-level analysis, transient simulation, SI
2	Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda	Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Bao Liu	Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations.	ISQED	2007	DBLP DOI BibTeX RDF
2	Zbysek Gajda, Lukás Sekanina	Reducing the number of transistors in digital circuits using gate-level evolutionary design.	GECCO	2007	DBLP DOI BibTeX RDF	digital circuits, evolvable hardware, evolutionary design
2	Hong Luo, Yu Wang 0002, Ku He, Rong Luo, Huazhong Yang, Yuan Xie	A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect.	PATMOS	2007	DBLP DOI BibTeX RDF
2	Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas	Probabilistic gate-level power estimation using a novel waveform set method.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	probabilistic power estimation, probability waveform, transition density, combinational logic, gate-level
2	Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José C. Monteiro	Optimization of Area in Digital FIR Filters using Gate-Level Metrics.	DAC	2007	DBLP DOI BibTeX RDF
2	Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu	Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Leticia Maria Veiras Bolzani, Edgar E. Sánchez, Matteo Sonza Reorda	A software-based methodology for the generation of peripheral test sets based on high-level descriptions.	SBCCI	2007	DBLP DOI BibTeX RDF	RT-level test metrics, code coverage metrics, gate-level test metrics, test block, fault coverage, SoC testing
2	Justin Lee, Joaquin Sitte	Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs.	AHS	2006	DBLP DOI BibTeX RDF
2	B. Chung, J. B. Kuo	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Diganchal Chakraborty, P. P. Chakrabarti, Arijit Mondal, Pallab Dasgupta	A Framework for Estimating Peak Power in Gate-Level Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Lukás Sekanina, Zdenek Vasícek	On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level.	EvoWorkshops	2006	DBLP DOI BibTeX RDF
2	Margrit R. Krug, Marcelo Lubaszewski, Marcelo de Souza Moraes	Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
2	Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli	Improving Gate-Level ATPG by Traversing Concurrent EFSMs.	VTS	2006	DBLP DOI BibTeX RDF
2	Xinyue Fan, Will R. Moore, Camelia Hora, Mario H. Konijnenburg, Guido Gronthoud	A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis.	VTS	2006	DBLP DOI BibTeX RDF
2	B. Chung, J. B. Kuo	Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Zhimin Chen, Yujie Zhou	Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage.	CHES	2006	DBLP DOI BibTeX RDF	Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA
2	Alexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton	Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator.	ISVLSI	2005	DBLP DOI BibTeX RDF
2	Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director	Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.	DAC	2005	DBLP DOI BibTeX RDF	correlation, variability, yield, leakage
2	Wieland Fischer, Berndt M. Gammel	Masking at Gate Level in the Presence of Glitches.	CHES	2005	DBLP DOI BibTeX RDF	random masking, masked logic circuits, Cryptanalysis, side-channel attacks, DPA, power analysis, logic circuits, digital circuits, masking, glitches
2	Ying-Tsai Chang, Kwang-Ting Cheng	Self-referential verification for gate-level implementations of arithmetic circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
2	Alexander Maili, Damian Dalton, Christian Steger	A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment.	PATMOS	2004	DBLP DOI BibTeX RDF
2	Frank Sill, Frank Grassert, Dirk Timmermann	Low power gate-level design with mixed-Vth (MVT) techniques.	SBCCI	2004	DBLP DOI BibTeX RDF	MVT, leakage currents, threshold voltage
2	Brian Marshall	Beyond P-Cell and Gate-Level: Accuracy Requirements for Simulation of Nanometer SoC Designs.	IWSOC	2004	DBLP DOI BibTeX RDF
2	Mark Litterick, Joachim Geishauser	Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments.	MTV	2004	DBLP DOI BibTeX RDF
2	Qi Wang, Sumit Roy	RTL Power Optimization with Gate-Level Accuracy.	ICCAD	2003	DBLP DOI BibTeX RDF
2	Ali Reza Ejlali, Seyed Ghassem Miremadi	Switch-level emulation.	DAC	2003	DBLP DOI BibTeX RDF	FPGA chips, gate-level models, emulation, switch-level models
2	Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi	Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
2	Ying-Tsai Chang, Kwang-Ting Cheng	Self-referential verification of gate-level implementations of arithmetic circuits.	DAC	2002	DBLP DOI BibTeX RDF	arithmetic circuit verification
2	Bernard N. Sheehan	Library Compatible Ceff for Gate-Level Timing.	DATE	2002	DBLP DOI BibTeX RDF
2	Ismet Bayraktaroglu, Alex Orailoglu	Gate Level Fault Diagnosis in Scan-Based BIST.	DATE	2002	DBLP DOI BibTeX RDF
2	Kyu-won Choi, Abhijit Chatterjee	HA2TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI.	ISLPED	2002	DBLP DOI BibTeX RDF	gate-level power optimization, time slack distribution, low-power design
2	Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura	Power analysis techniques for SoC with improved wiring models.	ISLPED	2002	DBLP DOI BibTeX RDF	custom wire load model, SoC, power analysis, gate-level
2	Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik	Multi-Level Fault Simulation of Digital Systems on Decision Diagrams.	DELTA	2002	DBLP DOI BibTeX RDF	register transfer and gate level descriptions, fault simulation, decision diagrams, Digital systems
2	Chingwei Yeh, Yin-Shuin Kang	Cell-based layout techniques supporting gate-level voltage scaling for low power.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
2	Masaya Iwata, Isamu Kajitani, Yong Liu, Nobuki Kajihara, Tetsuya Higuchi	Implementation of a Gate-Level Evolvable Hardware Chip.	ICES	2001	DBLP DOI BibTeX RDF
2	Chingwei Yeh, Yin-Shuin Kang	Cell-based layout techniques supporting gate-level voltage scaling for low power.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
2	Kenji Shimazaki, Hiroyuki Tsujikawa, Seijiro Kojima, Shouzou Hirano	LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator.	ISQED	2000	DBLP DOI BibTeX RDF
2	J. W. Smith	The gsim gate-level simulator.	ACM Southeast Regional Conference	2000	DBLP DOI BibTeX RDF
2	Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana	A Technique for Identifying RTL and Gate-Level Correspondences. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	On the feasibility of fault simulation using partial circuit descriptions.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	partial circuit description, gate-level circuits, subcircuits, logic testing, fault simulation, fault simulation, memory requirements
2	Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy	Fsimac: a fault simulator for asynchronous sequential circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
2	Ruofan Xu, Michael S. Hsiao	Embedded core testing using genetic algorithms.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	gate level implementation, user defined logic, random inputs, high level benchmarks, wrapper size, genetic algorithms, genetic algorithms, fault diagnosis, logic testing, controllability, controllability, high level synthesis, automatic test pattern generation, observability, observability, application specific integrated circuits, fault coverage, SOC, test application time, test patterns, embedded core testing, internal state
2	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	A genetic algorithm-based system for generating test programs for microprocessor IP cores.	ICTAI	2000	DBLP DOI BibTeX RDF	industrial property, genetic algorithm based system, test program generation, microprocessor IP cores, digital systems design trend, design-and-reuse paradigm, intellectual property cores, encrypted gate-level netlist, testability problems, automatic approach, processor cores, fault coverage figures, random approach, genetic algorithms, genetic algorithms, microprocessor chips, automatic test software, test program, electronic engineering computing
2	Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng	POSET timing and its application to the synthesis and verification of gate-level timed circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
2	Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani	Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion.	ASP-DAC	1999	DBLP DOI BibTeX RDF
2	Tatjana Serdar, Carl Sechen	AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths.	ICCAD	1999	DBLP BibTeX RDF
2	Chunhong Chen, Majid Sarrafzadeh	An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages.	ICCD	1999	DBLP DOI BibTeX RDF	Two-voltage, Algorithm, Low power, Gate-level
2	Sandip Kundu	GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification.	ITC	1998	DBLP DOI BibTeX RDF
2	Peter Wohl, John A. Waicukauski	Extracting gate-level networks from simulation tables.	ITC	1998	DBLP DOI BibTeX RDF
2	Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques.	DATE	1998	DBLP DOI BibTeX RDF	software testing, sequential circuits, automatic test generation, test sequence compaction
2	Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò	Gate-level power and current simulation of CMOS integrated circuits.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
2	Kazumi Hatayama, Kazunori Hikone, T. Miyazaki, H. Yamada	A practical approach to instruction-based test generation for functional modules of VLSI processors.	VTS	1997	DBLP DOI BibTeX RDF	VLSI processors, instruction-based test generation, functional test pattern generation, gate level faults, constrained test generation, ALU oriented test pattern generation system, VLSI, functional modules, ALPS
2	Kwang-Ting Cheng	Gate-level test generation for sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	testing, automatic test generation, IC testing, sequential circuit test generation
2	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register-transfer level estimation techniques for switching activity and power consumption.	ICCAD	1996	DBLP DOI BibTeX RDF	gate-level implementation, register-transfer level estimation, logic design, power consumption, switching activity, glitching, RTL designs
2	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Design tradeoffs in high speed multipliers and FIR filters.	VLSI Design	1996	DBLP DOI BibTeX RDF	high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed
2	Jitendra Khare, Wojciech Maly, Nathan Tiday	Fault characterization of standard cell libraries using inductive contamination.	VTS	1996	DBLP DOI BibTeX RDF	surface contamination, fault characterization, standard cell libraries, inductive contamination analysis, contamination diagnosis, gate-level delay characterization, fault diagnosis, test generation, integrated circuit testing, cellular arrays, defect coverage
2	Oriol Roig, Jordi Cortadella, Enric Pastor	Hierarchical gate-level verification of speed-independent circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	hierarchical gate-level verification, state signals, computational complexity, logic testing, time complexity, asynchronous circuits, speed-independent circuits, complex gates
2	Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz	LOT: logic optimization with testability-new transformations using recursive learning.	ICCAD	1995	DBLP DOI BibTeX RDF	EX-OR gates, logic optimization with testability, multi-level logic circuits, tstfx, logic design, combinational circuits, logic CAD, gate level, random-pattern testability, recursive learning
2	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation
2	C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal	A STAFAN-like functional testability measure for register-level circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
2	Enrico Macii, Massimo Poncino	Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	worst-case power consumption, symbolic neural networks, gate level description, symbolic domain, algebraic decision diagrams, graph specification, delays, combinational circuits, combinational circuits, logic CAD, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, energy dissipation
2	Enric Pastor, Jordi Cortadella, Oriol Roig	A new look at the conditions for the synthesis of speed-independent circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	gate-level synthesis, gate library constraint, fan-in reduction, VLSI, logic design, logic CAD, integrated circuit design, circuit CAD, integrated logic circuits, circuit optimisation, optimization techniques, speed-independent circuits
2	Franco Fummi, Donatella Sciuto, M. Serro	Synthesis for testability of large complexity controllers. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	large complexity controllers, industrial design environments, top-down methodology, hierarchical descriptions, irredundant circuits, optimized gate-level descriptions, testable descriptions, specification, high level synthesis, finite state machines, finite state machines, design for testability, design for testability, VHDL, automatic testing, logic CAD, hardware description languages, FSM, synthesis for testability, logic gates
2	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
2	Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda	Statistics on concurrent fault and design error simulation. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	concurrent fault/design error simulation, design error simulation processes, c-sim, gate level concurrent simulator, event based statistics, gate evaluation statistics, simulator developers, hardware accelerator designers, design options, parallel algorithms, formal verification, circuit analysis computing, design verification, memory requirements, experimental data, concurrent simulators
2	Michael S. Hsiao, Janak H. Patel	A new architectural-level fault simulation using propagation prediction of grouped fault-effects. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	architectural-level fault simulation, propagation prediction, grouped fault-effects, fault effects, intelligent propagation prediction, automated behavioral simulation, ALFSIM, Architectural Level Fault Simulation, gate level fault simulation, VLSI, fault diagnosis, circuit analysis computing, stuck at faults, integrated circuit design, deterministic algorithm, data types, symbolic data, architectural level
2	Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller	Emulation verification of the Motorola 68060. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level
2	Manish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain	Extraction of finite state machines from transistor netlists by symbolic simulation. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	finite state machine extraction, transistor netlists, clock level finite state machines, gate level representation, circuit clocking, output timing, simulation patterns, next state, output function, equivalent FSM, static storage structures, time multiplexed inputs, time multiplexed outputs, finite state machines, logic design, logic CAD, circuit analysis computing, FSMs, symbolic simulation, symbolic simulator, Ordered Binary Decision Diagrams
2	Shiu-Kai Chin, John Faust, Joseph Giordano	Integrating formal methods tools to support system design.	ICECCS	1995	DBLP DOI BibTeX RDF	formal methods tools integration, top-level process descriptions, gate-level hardware designs, simulators, formal specification, system design, specification languages, specification languages, systems analysis, system engineering, theorem-provers, computer-aided design tools, model checkers
2	S. M. Aziz	A C-testable modified Booth's array multiplier.	VLSI Design	1995	DBLP DOI BibTeX RDF	C-testable multiplier, modified Booth algorithm, gate-level design, parallel processing, logic testing, integrated circuit testing, digital arithmetic, stuck-at faults, CMOS logic circuits, multiplying circuits, logic arrays, array multiplier, parallel multiplier
2	C. P. Ravikumar, Hemant Joshi	HISCOAP: a hierarchical testability analysis tool.	VLSI Design	1995	DBLP DOI BibTeX RDF	HISCOAP, hierarchical testability analysis tool, SCOAP measure, gate-level netlist, SCOAP expression diagrams, VLSI, logic testing, controllability, controllability, sequential circuits, sequential circuits, combinational circuits, combinational circuits, observability, observability, circuit analysis computing, integrated logic circuits, VLSI circuits, functional modules, stuck at fault model
2	Niraj K. Jha, Abha Ahuja	Easily testable nonrestoring and restoring gate-level cellular array dividers.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
2	Sean Monaghan	A gate-level reconfigurable Monte carlo processor.	VLSI Signal Processing	1993	DBLP DOI BibTeX RDF
2	Ahmed E. Barbour	Test patterns for fault-tolerant logic circuits using block design concepts.	ACM Southeast Regional Conference	1992	DBLP DOI BibTeX RDF	System and Gate level, Testing and Testability, Redundancy, Fault-Tolerant Design, Block Design
2	Andres R. Takach, Niraj K. Jha	Easily testable gate-level and DCVS multipliers.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF
2	Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori	Datapath Generator Based on Gate-Level Symbolic Layout.	DAC	1990	DBLP DOI BibTeX RDF
2	Foong-Charn Chang, Chin-Fu Chen, Prasad Subramaniam	An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits.	DAC	1988	DBLP BibTeX RDF