Search results for "hardware"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
6	Kees A. Vissers	Trade-offs in the design of mixed hardware-software systems-a perspective from industry.	CODES	1997	DBLP DOI BibTeX RDF	consumer electronics devices, dedicated components, end-user applications, hardware interface, hardware-software systems design, on-screen display, programmable components, well defined interfaces, embedded systems, software architecture, operating system, high level synthesis, application programming interfaces, device drivers, television, software interfaces, industry perspective, hardware platform
6	Ghassan Al Hayek, Chantal Robach	On the Adequacy of Deriving Hardware Test Data from the Behavioral Specification.	EUROMICRO	1996	DBLP DOI BibTeX RDF	hardware test data, behavioral fault modeling, gate-level strategies, high-level fault detection, gate-level fault detection, design automation tools, generated test set, gate-level fault coverage, hardware description languages, hardware description languages, behavioral specification
5	Lang Lin, Markus Kasper, Tim Güneysu, Christof Paar, Wayne Burleson	Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering.	CHES	2009	DBLP DOI BibTeX RDF	Trojan Hardware, Trojan Side-Channel, Hardware Trojan Detection, Covert Channel, Side-Channel Analysis
5	David Szczesny, Sebastian Hessel, Felix Bruns, Attila Bilgic	On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	embedded systems, real-time, hardware acceleration, virtual prototyping, hardware/software co-design, LTE, DMA
5	Rajat Subhra Chakraborty, Swarup Bhunia	Hardware protection and authentication through netlist level obfuscation.	ICCAD	2008	DBLP DOI BibTeX RDF	IP piracy, design for security, hardware authentication, hardware obfuscation, hardware protection
5	Li-Yi Wei	Tile-based texture mapping on graphics hardware.	Graphics Hardware	2004	DBLP DOI BibTeX RDF	texture mapping, texture synthesis, graphics hardware
5	Timothy J. Purcell, Craig Donner, Mike Cammarano, Henrik Wann Jensen, Pat Hanrahan	Photon mapping on programmable graphics hardware.	Graphics Hardware	2003	DBLP DOI BibTeX RDF	global illumination, programmable graphics hardware, photon mapping
5	Mark J. Harris, William V. Baxter, Thorsten Scheuermann, Anselmo Lastra	Simulation of cloud dynamics on graphics hardware.	Graphics Hardware	2003	DBLP DOI BibTeX RDF	graphics hardware, clouds, physically-based simulation, fluid dynamics, light scattering
5	Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim	Gene Finding Using Evolvable Reasoning Hardware.	ICES	2003	DBLP DOI BibTeX RDF	evolving hardware system, evolutionary hardware design methodologies, genome informatics
5	Adel Baganne, Jean Luc Philippe, Eric Martin	Hardware interface design for real time embedded systems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	real time digital signal processing, hardware interface design, codesign approach, storage components, hardware-software components, I/O data modeling style, hardware I/O transfer sequences, high level synthesis tool, GAUT, I/O transfer order, cosynthesis tool, real-time systems, ASICs, timing constraints, generic model, data communication, real time embedded systems, formal technique, interface specification, FFT algorithms, allocation problem
5	Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya	A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor.	CODES	1997	DBLP DOI BibTeX RDF	hardware/software co-operation, a computer architecture using FPGA, bus-based reconfigurable co-processor architecture, high-level synthesis and optimization, C compiler to hardware modules
5	Ghassan Al Hayek, Yves Le Traon, Chantal Robach	Considering Test Economics in the Process of Hardware/Software Partitioning.	EUROMICRO	1996	DBLP DOI BibTeX RDF	hardware/software testing, specifications, logic testing, estimate, testability, co-design, mutation-test, hardware/software partitioning, test economics
5	Mark Genoe, Paul Vanoostende, Geert van Wauwe	On the use of VHDL-based behavioral synthesis for telecom ASIC design.	ISSS	1995	DBLP DOI BibTeX RDF	Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
5	Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller	Emulation verification of the Motorola 68060. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level
5	Jeffrey J. Joyce	Totally Verified Systems: Linking Verified Software to Verified Hardware.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF	machine-assisted theorem proving, safety-critical systems, higher-order logic, hardware verification, compiler correctness
4	Rishiyur S. Nikhil	Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design).	GPCE	2009	DBLP DOI BibTeX RDF	bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing
4	Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez	Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers.	CHES	2009	DBLP DOI BibTeX RDF	Karatsuba-Ofman multiplier, FPGA, elliptic curve, hardware accelerator, Tate pairing, finite field arithmetic, ? T pairing
4	Rajesh Sankaran, Brygg Ullmer, Jagannathan Ramanujam, Karun Kallakuri, Srikanth Jandhyala, Cornelius Toole, Christopher Laan	Decoupling interaction hardware design using libraries of reusable electronics.	Tangible and Embedded Interaction	2009	DBLP DOI BibTeX RDF	blades and tiles, decoupling TUI design, hardware toolkit, reusable hardware, modularity
4	Andreas Raabe, Philipp A. Hartmann, Joachim K. Anlauf	ReChannel: Describing and simulating reconfigurable hardware in systemC.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	hardware description, simulation, refinement, dynamic reconfiguration, SystemC, Reconfigurable hardware
4	Naoki Iwasaki, Katsumi Wasaki	A Meta Hardware Description Language Melasy for Model-Checking Systems.	ITNG	2008	DBLP DOI BibTeX RDF	Hardware/Software co-design and co-verification, Model Checking, Haskell, Design-for-test, Hardware Compilers
4	Greg Stitt	Hardware/software partitioning with multi-version implementation exploration.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	fpga, synthesis, hardware/software codesign, hardware/software partitioning
4	Túlio Cicero Salvaro de Souza, Jean Everson Martina, Ricardo Felipe Custódio	Audit and backup procedures for hardware security modules.	IDtrust	2008	DBLP DOI BibTeX RDF	PKI ceremony, embedded cryptographic hardware, hardware security module, key life-cycle, key management, public key infrastructure
4	Dai Yamamoto, Jun Yajima, Kouichi Itoh	A Very Compact Hardware Implementation of the MISTY1 Block Cipher.	CHES	2008	DBLP DOI BibTeX RDF	MISTY1, Compact Implementation, Block cipher, Hardware, ASIC
4	Patrick Rocke, Brian McGinley, John Maher, Fearghal Morgan, Jim Harkin	Investigating the Suitability of FPAAs for Evolved Hardware Spiking Neural Networks.	ICES	2008	DBLP DOI BibTeX RDF	FPAA Hardware Evolution, Analogue Neural Networks, Spiking Neural Networks
4	Stanislaw Deniziak, Adam Gorski	Hardware/Software Co-synthesis of Distributed Embedded Systems Using Genetic Programming.	ICES	2008	DBLP DOI BibTeX RDF	Genetic programming, hardware/software co-design
4	Stephen L. Smith, Andrew J. Greensted, Jon Timmis	Hardware Acceleration of an Immune Network Inspired Evolutionary Algorithm for Medical Diagnosis.	ICES	2008	DBLP DOI BibTeX RDF	Parkinson’s disease, Evolutionary algorithm, Artificial immune systems, Hardware acceleration, Immune networks
4	Lance Saldanha, Roman L. Lysecky	Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	floating point to fixed conversion, floating point, fixed point, hardware/software partitioning
4	Laura Frigerio, Fabio Salice	A performance-oriented hardware/software partitioning for datapath applications.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	hardware/software systems, performance oriented patitioning
4	Soonhoi Ha, Sungchan Kim, Choonseung Lee, Youngmin Yi, Seongnam Kwon, Young-Pyo Joo	PeaCE: A hardware-software codesign environment for multimedia embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	hardware-software cosimulation, embedded systems, design-space exploration, model-based design, Hardware-software codesign
4	Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham	Improved verification of hardware designs through antecedent conditioned slicing.	STTT	2007	DBLP DOI BibTeX RDF	LTL property, Antecedent conditioned slicing, Verilog RTL, Model checking, Program slicing, Hardware description languages, Hardware verification
4	Zoltán Ádám Mann, András Orbán, Péter Arató	Finding optimal hardware/software partitions.	Formal Methods in System Design	2007	DBLP DOI BibTeX RDF	Branch-and-bound, Integer linear programming, Hardware/software partitioning, Hardware/software co-design
4	M. Hase, K. Akie, M. Nobori, K. Matsumoto	Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware.	ASP-DAC	2007	DBLP DOI BibTeX RDF	54 MHz, real-time VC-1/H.264/MPEG-4 video processing hardware, multifunctional hardware intellectual property, digital moving pictures, mobile products, VC-1 functionality, Internet content, AVC functionality, digital television broadcasting, MPEG-4 functionality, TV telephony, encoding, decoding
4	Magnus Strengert, Thomas Klein, Thomas Ertl	A hardware-aware debugger for the OpenGL shading language.	Graphics Hardware	2007	DBLP DOI BibTeX RDF
4	Jeremy W. Sheaffer, David P. Luebke, Kevin Skadron	A hardware redundancy and recovery mechanism for reliable scientific computation on graphics processors.	Graphics Hardware	2007	DBLP DOI BibTeX RDF
4	Andrey Bogdanov, Thomas Eisenbarth, Andy Rupp	A Hardware-Assisted Realtime Attack on A5/2 Without Precomputations.	CHES	2007	DBLP DOI BibTeX RDF	A5/2, SMITH, cryptanalysis, GSM, Gaussian elimination, special-purpose hardware, linear systems of equations
4	Min Xie, Youren Wang, Li Wang, Yuan Zhang	Design on Operator-Based Reconfigurable Hardware Architecture and Cell Circuit.	ICES	2007	DBLP DOI BibTeX RDF	Operator-based programmable cell circuit, FPGA, Reconfigurable computing, Reconfigurable hardware, Information processing
4	Rui Yao, Youren Wang, Sheng-lin Yu, Guijun Gao	Research on the Online Evaluation Approach for the Digital Evolvable Hardware.	ICES	2007	DBLP DOI BibTeX RDF	online evolution, digital circuit, Evolvable hardware, incremental evaluation
4	Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou	Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost.	ASP-DAC	2007	DBLP DOI BibTeX RDF	hardware modifications, software modifications, hardware timers, interrupt controllers, software/device driver, distributed software-defined radio system, hardware measurements, power manager, power management, multiprocessor systems, distributed real-time systems, power constraints, low-power embedded systems
4	Tianyi Ma, Jun Yang, Xinglan Wang	Low Power Hardware-Software Partitioning Algorithm for Heterogeneous Distributed Embedded Systems.	EUC	2006	DBLP DOI BibTeX RDF	low power, tabu search, chaotic neural network, Hardware-software co-design, hardware-software partitioning
4	Roshan G. Ragel, Sri Parameswaran	Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	embedded processor reliability, hardware/software technique, micro-instruction routines, preemptive fault detection, reliable processors, control flow checking
4	Hayden Kwok-Hay So, Artem Tkachenko, Robert W. Brodersen	A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	hardware process, reconfigurable computers
4	Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke	Increasing hardware efficiency with multifunction loop accelerators.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	multifunction design, high-level synthesis, modulo scheduling, loop accelerator, application-specific hardware
4	Péter Arató, Zoltán Ádám Mann, András Orbán	Algorithmic aspects of hardware/software partitioning.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	optimization, graph algorithms, hardware/software codesign, Hardware/software partitioning, graph bipartitioning
4	Mahmoud Meribout, Mamoru Nakanishi	A New Real Time Object Segmentation and Tracking Algorithm and its Parallel Hardware Architecture.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	real-time object segmentation, real-time object tracking, parallel hardware for video processing, hardware-software dessign, video processing
4	Matt Ryan, Sojan Markose, Xiaoqing Frank Liu, Ying Cheng	Structured Object-Oriented Co-Analysis/Co-Design of Hardware/Software for the FACTS Power System.	COMPSAC	2005	DBLP DOI BibTeX RDF	Hardware/Software Co-analysis, Structured Object-Oriented Method, Embedded Systems, Integration, Hardware/Software Co-design, Concurrent Process
4	Budirijanto Purnomo, Jonathan Bilodeau, Jonathan D. Cohen, Subodh Kumar	Hardware-compatible vertex compression using quantization and simplification.	Graphics Hardware	2005	DBLP DOI BibTeX RDF
4	Gregor Wetekam, Dirk Staneker, Urs Kanus, Michael Wand	A hardware architecture for multi-resolution volume rendering.	Graphics Hardware	2005	DBLP DOI BibTeX RDF
4	Jens Franke, Thorsten Kleinjung, Christof Paar, Jan Pelzl, Christine Priplata, Colin Stahlke	SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers.	CHES	2005	DBLP DOI BibTeX RDF	GNFS, lattice sieving, RSA 1024 bit, Integer factorization, special hardware
4	Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto	Efficient Hardware for the Tate Pairing Calculation in Characteristic Three.	CHES	2005	DBLP DOI BibTeX RDF	tower fields, hardware accelerator, Tate pairing, characteristic three
4	Lejla Batina, David Hwang, Alireza Hodjat, Bart Preneel, Ingrid Verbauwhede	Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µP.	CHES	2005	DBLP DOI BibTeX RDF	HECC, genus 2 curves, embedded implementation, hardware/software co- design
4	John C. Gallagher, Sanjay K. Boddhu, Saranyan Vigraham	A Reconfigurable Continuous Time Recurrent Neural Network for Evolvable Hardware Applications.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
4	Nicholas J. Macias, Lisa J. K. Durbeck	A Hardware Implementation of the Cell Matrix Self-Configurable Architecture: The Cell Matrix MOD 88.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
4	Heng Liu, Julian F. Miller, Andy M. Tyrrell	Intrinsic Evolvable Hardware Implementation of a Robust Biological Development Model for Digital Systems.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
4	Arash Hariri, Reza Rastegar, Keivan Navi, Morteza Saheb Zamani, Mohammad Reza Meybodi	Cellular Learning Automata based Evolutionary Computing (CLA-EC) for Intrinsic Hardware Evolution.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
4	Dmitry Berenson, Nicolás S. Estévez, Hod Lipson	Hardware Evolution of Analog Circuits for In-situ Robotic Fault-Recovery.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
4	Timothy G. W. Gordon, Peter J. Bentley	Development Brings Scalability to Hardware Evolution.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
4	Adriano Sarmento, Lobna Kriaa, Arnaud Grasset, Mohamed-Wassim Youssef, Aimen Bouchhima, Frédéric Rousseau, Wander O. Cesário, Ahmed Amine Jerraya	Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	interface design automation, service-based model, systems-on-chip, hardware/software interfaces
4	Greg Stitt, Frank Vahid, Gordon McGregor, Brian Einloth	Hardware/software partitioning of software binaries: a case study of H.264 decode.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	FPGA, embedded systems, synthesis, H.264, hardware/software partitioning, binaries
4	Ben I. Hounsell, Tughrul Arslan, Robert Thomson	Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform.	Soft Comput.	2004	DBLP DOI BibTeX RDF	Robust hardware, Finite impulse response filters, Genetic algorithms, Fault tolerant, Programmable logic arrays, PLAs, FIR filters, Evolvable hardware
4	Robert Strzodka, Marc Droske, Martin Rumpf	Image Registration by a Regularized Gradient Flow. A Streaming Implementation in DX9 Graphics Hardware.	Computing	2004	DBLP DOI BibTeX RDF	graphics hardware computing, DX9 graphics hardware, Image registration, stream processing, multi-scale, gradient flow, multi-grid
4	Annette Bunker, Ganesh Gopalakrishnan, Sally A. McKee	Formal hardware specification languages for protocol compliance verification.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	Heterogeneous Hardware Logic, Hierarchical Annotated Action Diagrams, Lava, Objective VHDL, OpenVera, SpecC, Specification and Description Language, The Unified Modeling Language, Java, Statecharts, SystemC, Message Sequence Charts, Esterel, Live Sequence Charts, timing diagrams, hardware monitors, SystemVerilog, e, Property Specification Language
4	Peter Groen, Panu Hämäläinen, Ben H. H. Juurlink, Timo Hämäläinen	Accelerating the secure remote password protocol using reconfigurable hardware.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	secure remote password protocol, authentication, WLAN, hardware acceleration, reconfigurable hardware, modular exponentiation
4	Katherine Compton, Scott Hauck	Flexibility measurement of domain-specific reconfigurable hardware.	FPGA	2004	DBLP DOI BibTeX RDF	programmable hardware, flexibility, reconfigurable hardware
4	Andreas Kolb, Lutz Latta, Christof Rezk-Salama	Hardware-based simulation and collision detection for large particle systems.	Graphics Hardware	2004	DBLP DOI BibTeX RDF
4	Tim Foley, Mike Houston, Pat Hanrahan	Efficient partitioning of fragment shaders for multiple-output hardware.	Graphics Hardware	2004	DBLP DOI BibTeX RDF
4	Juan Manuel Moreno, Yann Thoma, Eduardo Sanchez, Oriol Torres, Gianluca Tempesti	Hardware Realization of a Bio-inspired POEtic Tissue.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
4	Josh C. Bongard, Hod Lipson	Automated Robot Function Recovery after Unanticipated Failure or Environmental Change using a Minimum of Hardware Trials.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
4	Evangelos F. Stefatos, Tughrul Arslan	An Efficient Fault-Tolerant VLSI Architecture Using Parallel Evolvable Hardware Technology.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
4	Ju Hui Li, Meng-Hiot Lim, Qi Cao	An Intrinsic Evolvable and Online Adaptive Evolvable Fuzzy Hardware Scheme for Packet Switching Network.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
4	Andrew J. Greensted, Andy M. Tyrrell	An Endocrinologic-Inspired Hardware Implementation of a Multicellular System.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
4	Gregory R. Kramer, John C. Gallagher, Michael L. Raymer	On the Relative Efficacies of *cGA Variants for Intrinsic Evolvable Hardware: Population, Mutation, and Random Immigrants.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
4	Yang Zhang, Stephen L. Smith, Andy M. Tyrrell	Digital Circuit Design using Intrinsic Evolvable Hardware.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
4	James Hereford, Charles Pruitt	Robust Sensor Systems using Evolvable Hardware.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
4	James Hereford, David A. Gwaltney	Design Space Issues for Intrinsic Evolvable Hardware.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
4	Radu Muresan, Catherine H. Gebotys	Current flattening in software and hardware for security applications.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	current flattening, hardware architecture, power analysis attacks
4	Jaehwan Lee, Vincent John Mooney III	A novel deadlock avoidance algorithm and its hardware implementation.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	deadlock avoidance hardware IP design
4	Hyunuk Jung, Soonhoi Ha	Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	automatic hardware synthesis, VHDL, system level design, dataflow graph(DFG), HW/SW codesign
4	Alan Mycroft, Richard Sharp	Higher-level techniques for hardware description and synthesis.	STTT	2003	DBLP DOI BibTeX RDF	Static allocation, Behavioural hardware description, High-level synthesis, Functional languages, Hardware/software co-design
4	Kris Gaj, Tarek A. El-Ghazawi, Nikitas A. Alexandridis, Jacek R. Radzikowski, Mohamed Taher, Frederic Vroman	Effective Utilization and Reconfiguration of Distributed Hardware Resources Using Job Management Systems.	IPDPS	2003	DBLP DOI BibTeX RDF	distributed hardware resources, Job Management Systems, accelerator boards, FPGA, job scheduling, reconfigurable hardware
4	Tsuyoshi Yamamoto, Munehiro Doi	Design and Implementation of Panoramic Movie System by Using Commodity 3D Graphics Hardware.	Computer Graphics International	2003	DBLP DOI BibTeX RDF	Panorama movie, Image Mosaicking, Commodity Hardware, Texture Mapping, 3D Graphics Hardware
4	Nolan Goodnight, Cliff Woolley, Gregory Lewin, David P. Luebke, Greg Humphreys	A multigrid solver for boundary value problems using programmable graphics hardware.	Graphics Hardware	2003	DBLP DOI BibTeX RDF
4	S. G. Lee, W. C. Park, W. J. Lee, T. D. Han, S. B. Yang	An effective hardware architecture for bump mapping using angular operation.	Graphics Hardware	2003	DBLP DOI BibTeX RDF
4	Naga K. Govindaraju, Stephane Redon, Ming C. Lin, Dinesh Manocha	CULLIDE: interactive collision detection between complex models in large environments using graphics hardware.	Graphics Hardware	2003	DBLP DOI BibTeX RDF
4	Le-Jeng Shiue, Vineet Goel, Jörg Peters	Mesh mutation in programmable graphics hardware.	Graphics Hardware	2003	DBLP DOI BibTeX RDF
4	A. P. Shanthi, Ranjani Parthasarathi	Exploring FPGA Structures for Evolving Fault Tolerant Hardware.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
4	Jeannette Plante, Harry C. Shaw, Lisa P. Mickens, Charles T. Johnson-Bey	Overview of Field Programmable Analog Arrays as Enabling Technology for Evolvable Hardware for High Reliability Systems.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
4	Garrison W. Greenwood, Edward Ramsden, Saima Ahmed	An Empirical Comparison of Evolutionary Algorithms for Evolvable Hardware.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
4	John R. Koza, Martin A. Keane, Matthew J. Streeter	The Importance of Reuse and Development in Evolvable Hardware.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
4	John C. Gallagher	The Once and Future Analog Alternative: Evolvable Hardware and Analog Computation.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
4	Daniel Roggen, Stephane Hofmann, Yann Thoma, Dario Floreano	Hardware spiking neural network with run-time reconfigurable connectivity in.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
4	David A. Gwaltney, Michael I. Ferguson	Intrinsic Hardware Evolution for the Design and Reconfiguration of Analog Speed Controllers for a DC Motor.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
4	Paul Kohout, Brinda Ganesh, Bruce L. Jacob	Hardware support for real-time operating systems.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	RTOS, hardware-software codesign
4	Wei Ming Lim, Mohammed Benaissa	Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and cryptography.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	GF(2m) arithmetic, forward error control coding, galois field processor, cryptography, advanced encryption standard, elliptic curve cryptography, design space exploration, Reed-Solomon code, hardware-software co-design, BCH code
4	Marc Olano, Bob Kuehne, Maryann Simmons	Automatic shader level of detail.	Graphics Hardware	2003	DBLP DOI BibTeX RDF	multi-pass rendering, computer games, level of detail, languages, simplification, interactive rendering, rendering systems, hardware systems, reflectance & shading models, procedural shading
4	Masatoshi Kameyama, Yoshiyuki Kato, Hitoshi Fujimoto, Hiroyasu Negishi, Yukio Kodama, Yoshitsugu Inoue, Hiroyuki Kawai	3D graphics LSI core for mobile phone "Z3D".	Graphics Hardware	2003	DBLP DOI BibTeX RDF	graphics accelerator, graphics hardware, rendering hardware
4	Eike Grimpe, Frank Oppenheimer	Extending the SystemC synthesis subset by object-oriented features.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	C/C++ based design, object-orientation, high-level synthesis, SystemC, system level design, hardware description language, hardware synthesis
4	Timothy G. W. Gordon, Peter J. Bentley	Towards Development in Evolvable Hardware.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
4	Jonathan R. Evans, Tughrul Arslan	The Implementation of an Evolvable Hardware System for Real Time Image Registration on a System-on-Chip Platform.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
4	Adrian Stoica, Didier Keymeulen, Ricardo Salem Zebulum, Michael I. Ferguson	On Two New Trends in Evolvable Hardware: Employment of HDL-Based Structuring, and Design of Multi-Functional Circuits.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
4	Daler N. Rakhmatov, Sarma B. K. Vrudhula	Hardware-software bipartitioning for dynamically reconfigurable systems.	CODES	2002	DBLP DOI BibTeX RDF	network flows, reconfigurable systems, hardware-software partitioning