Search results for "hardware accelerators"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Frederico Pratas, Leonel Sousa	Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study.	SAMOS	2009	DBLP DOI BibTeX RDF
2	Gregorio Quintana-Ortí, Francisco D. Igual, Enrique S. Quintana-Ortí, Robert A. van de Geijn	Solving dense linear systems on platforms with multiple hardware accelerators.	PPOPP	2009	DBLP DOI BibTeX RDF	algorithms-by-blocks, depencency analysis, dynamic scheduling, out-of-order execution, gpus
2	Sébastien Lafond, Johan Lilius	Interrupt Costs in Embedded System with Short Latency Hardware Accelerators.	ECBS	2008	DBLP DOI BibTeX RDF	Interrupt, Hardware accelerator
2	Maurizio Paganini	Nomadik®: A Mobile Multimedia Application Processor Platform.	ASP-DAC	2007	DBLP DOI BibTeX RDF	mobile multimedia application processor platform, Nomadik platform, industry standard host processor, low-power DSP, hardware accelerators
2	Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne	Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	virtual machine, synthesis, accelerator
2	Emil Jovanov, Veljko M. Milutinovic, Ali R. Hurson	Acceleration of Nonnumeric Operations Using Hardware Support for the Ordered Table Hashing Algorithms.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	nonnumeric processing, searching, sorting, hashing, hardware accelerators, Database operations
1	Ramon Doallo, Margarita Amor, Basilio B. Fraguela	Special issue editorial: Exploitation of hardware accelerators.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Uwe Meyer-Bäse, Guillermo Botella Juan, Soumak Mookherjee, Encarnación Castillo, Antonio García	Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Daniel Hackenberg, Guido Juckeland, Holger Brunst	Performance analysis of multi-level parallelism: inter-node, intra-node and hardware accelerators.	Concurrency and Computation: Practice and Experience	2012	DBLP DOI BibTeX RDF
1	Kah-Hyong Chang, Paramesran Raveendran, Barmak Honarvar Shakibaei Asli, Chern-Loon Lim	Efficient Hardware Accelerators for the Computation of Tchebichef Moments.	IEEE Trans. Circuits Syst. Video Techn.	2012	DBLP DOI BibTeX RDF
1	Alexandru Amaricai, Oana Boncalo	Automatic Generation of FPGA Hardware Accelerators for Graphics Applications.	PECCS	2012	DBLP BibTeX RDF
1	Rick Weber, Akila Gothandaraman, Robert J. Hinde, Gregory D. Peterson	Comparing Hardware Accelerators in Scientific Applications: A Case Study.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	FPGA, GPU, multicore, computational science, CUDA, Accelerator, OpenCL
1	Fabio Cancare, Alessandro Marin, Donatella Sciuto	Dedicated hardware accelerators for the epistatic analysis of human genetic data.	ICSAMOS	2011	DBLP DOI BibTeX RDF
1	Zdenek Pohl, Milan Tichý	Resource Management for the Heterogeneous Arrays of Hardware Accelerators.	FPL	2011	DBLP DOI BibTeX RDF
1	Jaroslav Sykora, Leos Kafka, Martin Danek, Lukas Kohout	Microthreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP Processors.	DSD	2011	DBLP DOI BibTeX RDF
1	Aws Ismail, Lesley Shannon	FUSE: Front-End User Framework for O/S Abstraction of Hardware Accelerators.	FCCM	2011	DBLP DOI BibTeX RDF
1	Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson	High-performance hardware accelerators for sorting and managing priorities.	DDECS	2011	DBLP DOI BibTeX RDF
1	Yen-Kuan Wu, Shervin Sharifi, Tajana Simunic Rosing	Distributed thermal management for embedded heterogeneous MPSoCs with dedicated hardware accelerators.	ICCD	2011	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Vijayalakshmi Srinivasan	Big Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF	Big chips, dark silicon, network scalability, thermal design power, large-scale designs, field-programmable gate arrays, hardware accelerators, dynamic voltage and frequency scaling, 3D integration, physical synthesis, clock network synthesis
1	Adam B. Kinsman, Nicola Nicolici	Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	Bit-width allocation, hardware accelerators
1	Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pratim Pande, Ananth Kalyanaraman	Network-on-Chip Hardware Accelerators for Biological Sequence Alignment.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	DNA/protein sequence alignment, on-chip parallelism, bioinformatics, Network-on-chip, hardware acceleration
1	Adam B. Kinsman, Nicola Nicolici	Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Michael F. Dossis	Automated Extraction of Hardware Accelerators Via an Intelligent Knowledge-based System.	IJIIP	2010	DBLP BibTeX RDF
1	Jens Huthmann, Peter Müller 0004, Florian Stock, Dietmar Hildenbrand, Andreas Koch	Accelerating high-level engineering computations by automatic compilation of Geometric Algebra to hardware accelerators.	ICSAMOS	2010	DBLP DOI BibTeX RDF
1	Manuel Fogue, Francisco D. Igual, Enrique S. Quintana-Ortí, Robert A. van de Geijn	Retargeting PLAPACK to clusters with hardware accelerators.	HPCS	2010	DBLP DOI BibTeX RDF
1	Adam B. Kinsman, Nicola Nicolici	Robust design methods for hardware accelerators for iterative algorithms in scientific computing.	DAC	2010	DBLP DOI BibTeX RDF	bit-width allocation, satisfiability-modulo theory
1	Christophe Alias, Alain Darte, Alexandru Plesco	Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool.	ASAP	2010	DBLP DOI BibTeX RDF
1	Tobias Beisel, Manuel Niekamp, Christian Plessl	Using shared library interposing for transparent application acceleration in systems with heterogeneous hardware accelerators.	ASAP	2010	DBLP DOI BibTeX RDF
1	Jason R. Villarreal, Adrian Park, Walid A. Najjar, Robert Halstead	Designing Modular Hardware Accelerators in C with ROCCC 2.0.	FCCM	2010	DBLP DOI BibTeX RDF
1	Souradip Sarkar, Turbo Majumder, Ananth Kalyanaraman, Partha Pratim Pande	Hardware accelerators for biocomputing: A survey.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker	A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	designflow, toolchain, fpga, partitioning, reconfigurable computing, mpsoc, hardware/software co-design
1	Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev	A 3d-audio reconfigurable processor.	FPGA	2010	DBLP DOI BibTeX RDF	reconfigurable computing, communication systems, beamforming, 3d-audio, wave field synthesis
1	Marco Ceriani, Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto, Antonino Tumeo	Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation.	GECCO	2010	DBLP DOI BibTeX RDF	multi-objective evolution, systems-on-chip synthesis
1	Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis	The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Ricardo Menotti, João M. P. Cardoso, Marcio Merino Fernandes, Eduardo Marques	Automatic generation of FPGA hardware accelerators using a domain specific language.	FPL	2009	DBLP DOI BibTeX RDF
1	Frank Hannig, Hritam Dutta, Jürgen Teich	Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning.	ARCS	2009	DBLP DOI BibTeX RDF
1	Yolanda Becerra, Vicenç Beltran, David Carrera, Marc González, Jordi Torres, Eduard Ayguadé	Speeding Up Distributed MapReduce Applications Using Hardware Accelerators.	ICPP	2009	DBLP DOI BibTeX RDF
1	Jing Yan, Rong Luo, Rui Gao, Ning-Yi Xu	An Efficient Lossless Compression Method for Internet Search Data in Hardware Accelerators.	CSIE	2009	DBLP DOI BibTeX RDF
1	Sebastian Hessel, David Szczesny, Nils Lohmann, Attila Bilgic, Josef Hausner	Implementation and Benchmarking of Hardware Accelerators for Ciphering in LTE Terminals.	GLOBECOM	2009	DBLP DOI BibTeX RDF
1	Rishiyur S. Nikhil	Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design).	GPCE	2009	DBLP DOI BibTeX RDF	bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing
1	Peter Bertels, Wim Heirman, Dirk Stroobandt	Strategies for dynamic memory allocation in hybrid architectures.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	java, memory management, hardware acceleration
1	Ya-shuai Lü, Li Shen, Zhiying Wang, Nong Xiao	Dynamically utilizing computation accelerators for extensible processors in a software approach.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	computation accelerator, ASIP, dynamic binary translation
1	André Brinkmann, Dominic Eschweiler	A microdriver architecture for error correcting codes inside the Linux kernel.	SC	2009	DBLP DOI BibTeX RDF
1	Sören Sonntag, Wenjian Wang	Area and power consumption estimations at system level with SystemQ 2.0.	SimuTools	2009	DBLP DOI BibTeX RDF	SystemQ, area and power estimation, modeling, synthesis, electronic system level
1	Ning Weng, Tilman Wolf	Analytic modeling of network processors for parallel workload mapping.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	embedded systems, network processors, multiprocessor scheduling, Application profiling
1	Peter Bertels, Wim Heirman, Erik H. D'Hollander, Dirk Stroobandt	Efficient memory management for hardware accelerated Java Virtual Machines.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Java Virtual Machine, hardware acceleration, Dynamic memory management
1	Sebastian Hessel, David Szczesny, Shadi Traboulsi, Attila Bilgic, Josef Hausner	On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals.	CSE	2009	DBLP DOI BibTeX RDF
1	Christophe Desmouliers, Erdal Oruklu, Jafar Saniie	FPGA-based design of a high-performance and modular video processing platform.	EIT	2009	DBLP DOI BibTeX RDF
1	Heiner Litz, Holger Fröning, Ulrich Brüning	A HyperTransport 3 Physical Layer Interface for FPGAs.	ARC	2009	DBLP DOI BibTeX RDF
1	Rainer Buchty, David Kramer, Mario Kicherer, Wolfgang Karl	A Light-Weight Approach to Dynamical Runtime Linking Supporting Heterogenous, Parallel, and Reconfigurable Architectures.	ARCS	2009	DBLP DOI BibTeX RDF
1	Hritam Dutta, Frank Hannig, Jürgen Teich	Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis.	ARCS	2009	DBLP DOI BibTeX RDF
1	Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro	Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm.	ARC	2009	DBLP DOI BibTeX RDF	Block Cipher Algorithm, Field Programmable Gate Arrays (FPGA), Cryptography, SEED
1	Eduard Ayguadé, Rosa M. Badia, Francisco D. Igual, Jesús Labarta, Rafael Mayo, Enrique S. Quintana-Ortí	An Extension of the StarSs Programming Model for Platforms with Multiple GPUs.	Euro-Par	2009	DBLP DOI BibTeX RDF	heterogeneous systems, programming models, graphics processors, Task-level parallelism
1	Eladio Gutiérrez, Sergio Romero, María A. Trenas, Oscar G. Plata	Experiences with Mapping Non-linear Memory Access Patterns into GPUs.	ICCS	2009	DBLP DOI BibTeX RDF
1	Eduard Ayguadé, Rosa M. Badia, Daniel Cabrera, Alejandro Duran, Marc González, Francisco D. Igual, Daniel Jiménez-González, Jesús Labarta, Xavier Martorell, Rafael Mayo, Josep M. Pérez, Enrique S. Quintana-Ortí	A Proposal to Extend the OpenMP Tasking Model for Heterogeneous Architectures.	IWOMP	2009	DBLP DOI BibTeX RDF
1	Yahya Jan, Lech Józwiak	CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF	RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC
1	Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silvén	Programmable Accelerators for Reconfigurable Video Decoder.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen	Evaluating SoC Network Performance in MPEG-4 Encoder.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	FPGA multiprocessor, Multiprocessor, System-on-chip, Network-on-chip, MPEG-4, MPSoC, On-chip interconnection
1	Svetlin Manavski, Giorgio Valle	CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment.	BMC Bioinformatics	2008	DBLP DOI BibTeX RDF
1	Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Francisco Rodríguez-Henríquez	A Comparison Between Hardware Accelerators for the Modified Tate Pairing over F2m and F3m.	IACR Cryptology ePrint Archive	2008	DBLP BibTeX RDF
1	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	Cost-Efficient SHA Hardware Accelerators.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Zdenek Vasícek, Lukás Sekanina	Hardware Accelerators for Cartesian Genetic Programming.	EuroGP	2008	DBLP DOI BibTeX RDF
1	Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich	PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications.	ARC	2008	DBLP DOI BibTeX RDF
1	Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Francisco Rodríguez-Henríquez	A Comparison between Hardware Accelerators for the Modified Tate Pairing over F2m and F3m.	Pairing	2008	DBLP DOI BibTeX RDF	Modified Tate pairing, reduced ? T pairing, FPGA, elliptic curve, hardware accelerator, finite field arithmetic
1	Humberto Calderon, Jesús Ortiz, Jean-Guy Fontaine	Disparity Map Hardware Accelerator.	ReConFig	2008	DBLP DOI BibTeX RDF	FPGA, computer vision, computer arithmetic, Hardware accelerators, disparity map
1	Fernando Martin del Campo, René Cumplido, Roberto Perez-Andrade, Aldo G. Orozco-Lugo	Hybrid Architecture for Data-Dependent Superimposed Training in Digital Receivers.	ReConFig	2008	DBLP DOI BibTeX RDF	Data-dependent Superimposed Training, Hardware Accelerators, Hybrid Architecture, Communications Algorithms
1	David Bermingham, Liu Zhen, Xiaojun Wang	SimNP: a flexible platform for the simulation of a network processing system.	ANCS	2008	DBLP DOI BibTeX RDF	network processing system, simulation, performance analysis
1	Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull	DVFS in loop accelerators using BLADES.	DAC	2008	DBLP DOI BibTeX RDF	embedded systems, low power, high-level synthesis, voltage scaling, frequency scaling
1	Christian Haubelt, Thomas Schlichter, Joachim Keinert, Michael Meredith	SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models.	DAC	2008	DBLP DOI BibTeX RDF	rapid prototyping, design space exploration, ESL design
1	Cesare Ferri, Amber Viescas, Tali Moreshet, R. Iris Bahar, Maurice Herlihy	Energy efficient synchronization techniques for embedded architectures.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	embedded systems, transactional memory
1	Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow	A Desktop Computer with a Reconfigurable Pentium®.	TRETS	2008	DBLP DOI BibTeX RDF	Pentium®, simulator, model, FPGA, architecture, operating system, reconfigurable, emulator, exploration, accelerator, processor
1	Sören Sonntag, Helmut Reinig	An Efficient Weighted-Round-Robin Algorithm for Multiprocessor Architectures.	Annual Simulation Symposium	2008	DBLP DOI BibTeX RDF	SystemQ, Algorithm, Multiprocessor, System on Chip, Arbitration, Weighted Round Robin
1	Jie Shao, Ning Ye, Xiao-Yan Zhang	An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs.	CSSE	2008	DBLP DOI BibTeX RDF
1	Zhijun Li, Ning-Yi Xu, Feng-Hsiung Hsu, Xiongfei Cai, Rui Gao, Zenglin Xia	Distributed RankBoost Acceleration Using FPGA and MPI for Web Relevance Ranking.	ICPADS	2008	DBLP DOI BibTeX RDF
1	Yijun Liu, Banghai Wang, Guobo Xie, Pinghua Chen, Zhenkun Li	Designing a Multi-Processor Education Board for High-Performance Embedded Processing.	ICYCS	2008	DBLP DOI BibTeX RDF
1	Santheeban Kandasamy, Andrew Morton, Wayne M. Loucks	Configuration Scheduling Using Temporal Locality and Kernel Correlation.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Richard Bruce, Danny Kershaw, Alastair Reid, Mladen Wilder, Krisztián Flautner	From SODA to scotch: The evolution of a wireless baseband processor.	MICRO	2008	DBLP DOI BibTeX RDF
1	Mingxuan Yuan, Xiuqiang He, Zonghua Gu	Hardware/Software Partitioning and Static Task Scheduling on Runtime Reconfigurable FPGAs using a SMT Solver.	IEEE Real-Time and Embedded Technology and Applications Symposium	2008	DBLP DOI BibTeX RDF
1	Frederik Naessens, Bruno Bougard, Siebert Bressinck, Lieven Hollevoet, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor	A unified instruction set programmable architecture for multi-standard advanced forward error correction.	SiPS	2008	DBLP DOI BibTeX RDF
1	Ajay K. Verma, Philip Brisk, Paolo Ienne	Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Ling Zhuo, Viktor K. Prasanna	Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
1	Brian E. Paul, Sean Ahern, E. Wes Bethel, Eric Brugger, Rich Cook, Jamison Daniel, Ken Lewis, Jens Owen, Dale Southard	Chromium Renderserver: Scalable and Open Remote Rendering Infrastructure.	IEEE Trans. Vis. Comput. Graph.	2008	DBLP DOI BibTeX RDF
1	Guy Gogniat, Tilman Wolf, Wayne P. Burleson, Jean-Philippe Diguet, Lilian Bossuet, Romain Vaslin	Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Kimmo U. Järvinen, Jorma Skyttä	On Parallelization of High-Speed Processors for Elliptic Curve Cryptography.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Pavan Balaji, Sitha Bhagvat, Rajeev Thakur, Dhabaleswar K. Panda	Sockets Direct Protocol for Hybrid Network Stacks: A Case Study with iWARP over 10G Ethernet.	HiPC	2008	DBLP DOI BibTeX RDF
1	Maurice Keller, William P. Marnane	Energy Efficient Elliptic Curve Processor.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Zoran Miljanic, Ivan Seskar, Khanh Le, Dipankar Raychaudhuri	The WINLAB Network Centric Cognitive Radio Hardware Platform - WiNC2R.	MONET	2008	DBLP DOI BibTeX RDF	network centric platforms, cognitive radio, SDR, cooperative system
1	Sung Dae Kim, Myung Hoon Sunwoo	ASIP Approach for Implementation of H.264/AVC.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	low power design, H.264/AVC, hardware accelerator, application specific instruction-set processor, data reuse, hardware software codesign
1	Fredrik Kristensen, Hugo Hedberg, Hongtu Jiang, Peter Nilsson, Viktor Öwall	An Embedded Real-Time Surveillance System: Implementation and Evaluation.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	FPGA, embedded system, real-time, segmentation, tracking, hardware, surveillance, morphology, labeling, video processing, image features
1	Andrew Kinane, Noel E. O'Connor	Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	shape adaptive DCT/IDCT, low power, MPEG-4, hardware acceleration, video objects
1	Giovanni Danese, Mauro Giachero, Francesco Leporati, Giulia Matrone, Nelson Nazzicari	A Dedicated Hardware for Fingerprint Authentication.	KES	2007	DBLP DOI BibTeX RDF	Authentication and Security, Phase-only correlation, FPGA, Image Processing, Fingerprints, Hardware Accelerators
1	Dirk Koch, Christian Haubelt, Jürgen Teich	Efficient hardware checkpointing: concepts, overhead analysis, and implementation.	FPGA	2007	DBLP DOI BibTeX RDF	state access, checkpointing
1	Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh	An FPGA-based Pentium in a complete desktop system.	FPGA	2007	DBLP DOI BibTeX RDF	pentium®, FPGA, emulator, accelerator, processor
1	Nathan Woods	Integrating FPGAs in high-performance computing: the architecture and implementation perspective.	FPGA	2007	DBLP DOI BibTeX RDF	compute acceleration, high-performance computinghigh-performance computing, reconfigurable computing, co-processor
1	Christophe Alias, Fabrice Baray, Alain Darte	Bee+Cl@k: an implementation of lattice-based array contraction in the source-to-source translator rose.	LCTES	2007	DBLP DOI BibTeX RDF	program analysis, lattices, source-to-source transformations, memory reduction
1	Alessandro Mulloni, Daniele Nadalutti, Luca Chittaro	Interactive walkthrough of large 3D models of buildings on mobile devices.	Web3D	2007	DBLP DOI BibTeX RDF	mobile devices, rendering, X3D, architectural models, culling
1	Paolo Bonzini, Laura Pozzi	A Retargetable Framework for Automated Discovery of Custom Instructions.	ASAP	2007	DBLP DOI BibTeX RDF
1	Suman Mamidi, Michael J. Schulte, Daniel Iancu, C. John Glossner	Architecture Support for Reconfigurable Multithreaded Processors in Programmable Communication Systems.	ASAP	2007	DBLP DOI BibTeX RDF
1	Wei Wang, Qiang Wu, Wei Xie	Hardware-Software Co-design for Dynamic Reconfigurable Computing with Collaborative Supports of Architecture and Operating System.	CSCWD	2007	DBLP DOI BibTeX RDF
1	Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani B. Srivastava	A System For Coarse Grained Memory Protection In Tiny Embedded Processors.	DAC	2007	DBLP DOI BibTeX RDF