Search results for "hardware architectures"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Annie A. M. Cuyt, Walter Krämer, Wolfram Luther, Peter W. Markstein	08021 Summary - Numerical Validation in Current Hardware Architectures.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
3	Wolfram Luther, Annie A. M. Cuyt, Walter Krämer, Peter W. Markstein	08021 Abstracts Collection - Numerical Validation in Current Hardware Architectures.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Scott Schneider, Henrique Andrade, Bugra Gedik, Kun-Lung Wu, Dimitrios S. Nikolopoulos	Evaluation of streaming aggregation on parallel hardware architectures.	DEBS	2010	DBLP DOI BibTeX RDF
2	Annie A. M. Cuyt, Walter Krämer, Wolfram Luther, Peter W. Markstein (eds.)	Numerical Validation in Current Hardware Architectures, International Dagstuhl Seminar, Dagstuhl Castle, Germany, January 6-11, 2008. Revised Papers	Numerical Validation in Current Hardware Architectures	2009	DBLP DOI BibTeX RDF
2	Rafael A. Arce-Nazario, Manuel Jiménez, Domingo Rodríguez	Mapping of Discrete Cosine Transforms onto Distributed Hardware Architectures.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	Distributed hardware architecture, Partitioning methodology, Discrete cosine transforms
2	Annie A. M. Cuyt, Walter Krämer, Wolfram Luther, Peter W. Markstein (eds.)	Numerical Validation in Current Hardware Architectures, 6.1. - 11.1.2008	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Paul Zimmermann	Implementation of the reciprocal square root in MPFR.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Markus Grimmer	Extending the Range of C-XSC: Some Tools and Applications for the use in Parallel and other Environments.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Jürgen Wolff von Gudenberg	Interval Arithmetic and Standardization.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Peter W. Markstein	The New IEEE-754 Standard for Floating Point Arithmetic.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Evgenija D. Popova	On the Interoperability between Interval Software.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Mariana Luderitz Kolberg, Walter Krämer, Michael Zimmer	A Note on Solving Problem 7 of the SIAM 100-Digit Challenge Using C-XSC.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Frithjof Blomquist, Werner Hofschuster, Walter Krämer	A Modified Staggered Correction Arithmetic with Enhanced Accuracy and Very Wide Exponent Range.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Michael Zimmer, Walter Krämer	Fast (Parallel) Dense Linear Interval Systems Solvers in C-XSC Using Error Free Transformations and BLAS.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Ulrich W. Kulisch	Complete Interval Arithmetic and its Implementation.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Eva Dyllong	A Note on Some Applications of Interval Arithmetic in Hierarchical Solid Modeling.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Mariana Luderitz Kolberg, Gerd Bohlender, Dalcidio Moraes Claudio	Improving the Performance of a Verified Linear System Solver Using Optimized Libraries and Parallel Computation.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Markus Neher	The CoStLy C++ Class Library.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Ekaterina Auer, Wolfram Luther	Numerical Verification Assessment in Computational Biomechanics.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Andreas Rauh, Johanna Minisini, Eberhard P. Hofer	Towards the Development of an Interval Arithmetic Environment for Validated Computer-Aided Design and Verification of Systems in Control Engineering.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	John D. Pryce, George F. Corliss, R. Baker Kearfott, Nedialko S. Nedialkov, Spencer Smith	Second Note on Basic Interval Arithmetic for IEEE754R.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Werner Hofschuster, Walter Krämer, Markus Neher	C-XSC and Closely Related Software Packages.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Gregorio de Miguel Casado, Juan Manuel García Chamizo	A Software Library for Reliable Online-Arithmetic with Rational Numbers.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Di Jiang, Neil F. Stewart	Robustness of Boolean operations on subdivision-surface models.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Michel Kieffer	Distributed parameter and state estimation in a network of sensors.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
2	Evgenija D. Popova	Mathematica Connectivity to Interval Libraries filib++ and C-XSC.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF	interval software, C-XSC, filib++, MathLink, external programs, interfacing, Mathematica, Software interoperability
2	Walter Krämer, Michael Zimmer	Fast (Parallel) Dense Linear System Solvers in C-XSC Using Error Free Transformations and BLAS.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF	AMS subject classification 65H10, 15-04, 65G10, 65-04, 68W15, 65G99
2	Di Jiang, Neil F. Stewart	Robustness of Boolean Operations on Subdivision-Surface Models.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF
2	Ekaterina Auer, Wolfram Luther	Numerical Verification Assessment in Computational Biomechanics.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF	Numerical verification assessment, validation, uncertainty, result verification
2	Andreas Rauh, Johanna Minisini, Eberhard P. Hofer	Towards the Development of an Interval Arithmetic Environment for Validated Computer-Aided Design and Verification of Systems in Control Engineering.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF
2	Frithjof Blomquist, Werner Hofschuster, Walter Krämer	A Modified Staggered Correction Arithmetic with Enhanced Accuracy and Very Wide Exponent Range.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF	AMS classification 65G20, 65Y99, 37M99, 30-04, 65G30
2	Ulrich W. Kulisch	Complete Interval Arithmetic and Its Implementation on the Computer.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF	arithmetic standards, computer arithmetic, interval arithmetic, floating-point arithmetic
2	Markus Grimmer	Extending the Range of C-XSC: Some Tools and Applications for the Use in Parallel and Other Environments.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF	C-XSC, Verified Linear System Solver, MPI, Maple, Interval Arithmetic, Integral Equations, Parallel Environment
2	Mariana Luderitz Kolberg, Walter Krämer, Michael Zimmer	A Note on Solving Problem 7 of the SIAM 100-Digit Challenge Using C-XSC.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF	C-XSC, 100-digit challenge, reliable linear system solver, large dense linear systems, high performance computing, reliable computing
2	R. Baker Kearfott, John D. Pryce, Nathalie Revol	Discussions on an Interval Arithmetic Standard at Dagstuhl Seminar 08021.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF
2	Stef Graillat, Jean Luc Lamotte, Diep Nguyen Hong	Error-Free Transformation in Rounding Mode toward Zero.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF
2	Werner Hofschuster, Walter Krämer, Markus Neher	C-XSC and Closely Related Software Packages.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF	AMS subject classification 68N30, 68N19, 65F99, 65G20, 65G30
2	Annie A. M. Cuyt, Franky Backeljauw, Stefan Becuwe, Michel Colman, Tom Docx, Joris Van Deun	Continued Fractions for Special Functions: Handbook and Software.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF
2	Andreas Frommer, Valeria Simoncini	Error Bounds for Lanczos Approximations of Rational Functions of Matrices.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF
2	Eva Dyllong	Some Applications of Interval Arithmetic in Hierarchical Solid Modeling.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF	Reliable solid modeling, interval arithmetic, hierarchical data structure
2	Michel Kieffer	Distributed Bounded-Error Parameter and State Estimation in Networks of Sensors.	Numerical Validation in Current Hardware Architectures	2008	DBLP DOI BibTeX RDF
2	Máire McLoone, Ciaran McIvor	High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	hash function implementation, cryptography, whirlpool
2	Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen	Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks.	SAMOS	2007	DBLP DOI BibTeX RDF
2	A. Satoh	High-speed hardware architectures for authenticated encryption mode GCM.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Mark J. Clement, Michael J. Quinn	Symbolic performance prediction of scalable parallel programs. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	symbolic performance prediction, scalable parallel programs, massively parallel processing machines, performance prediction methodology, program source code, algebraic manipulations, parallel processing, analytical model, software performance evaluation, program debugging, hardware architectures, symbol manipulation, performance tuning, symbolic analysis, computational problems
1	Howida Abd A. El-Halym, Imbaby I. Mahmoud, S. E.-D. Habib	Proposed hardware architectures of particle filter for object tracking.	EURASIP J. Adv. Sig. Proc.	2012	DBLP DOI BibTeX RDF
1	Holger Scherl, Markus Kowarschik, Hannes G. Hofmann, Benjamin Keck, Joachim Hornegger	Evaluation of state-of-the-art hardware architectures for fast cone-beam CT reconstruction.	Parallel Computing	2012	DBLP DOI BibTeX RDF
1	Mariano Fons, Francesc Fons, Enrique Cantó	Biometrics-based consumer applications driven by reconfigurable hardware architectures.	Future Generation Comp. Syst.	2012	DBLP DOI BibTeX RDF
1	Dong-U Lee, Lok-Won Kim, John D. Villasenor	Precision-Aware Self-Quantizing Hardware Architectures for the Discrete Wavelet Transform.	IEEE Transactions on Image Processing	2012	DBLP DOI BibTeX RDF
1	Paris Kitsos, Nicolas Sklavos, Maria Parousi, Athanassios N. Skodras	A comparative study of hardware architectures for lightweight block ciphers.	Computers & Electrical Engineering	2012	DBLP DOI BibTeX RDF
1	Holger Scherl	Evaluation of state-of-the-art hardware architectures for fast cone-beam CT reconstructions.		2011	RDF
1	Miaoqing Huang, Kris Gaj, Tarek A. El-Ghazawi	New Hardware Architectures for Montgomery Modular Multiplication Algorithm.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Alejandro Nieto, Victor M. Brea, David López Vilariño, Roberto R. Osorio	Performance analysis of massively parallel embedded hardware architectures for retinal image processing.	EURASIP J. Image and Video Processing	2011	DBLP DOI BibTeX RDF
1	Kris Gaj, Rainer Steinwandt	Hardware architectures for algebra, cryptology, and number theory.	Integration	2011	DBLP DOI BibTeX RDF
1	Adrien Le Masle, Wayne Luk, Csaba Andras Moritz	Parametrized hardware architectures for the Lucas primality test.	ICSAMOS	2011	DBLP DOI BibTeX RDF
1	Camille Leroux, Ido Tal, Alexander Vardy, Warren J. Gross	Hardware architectures for successive cancellation decoding of polar codes.	ICASSP	2011	DBLP DOI BibTeX RDF
1	Eduardo Romero-Aguirre, Ramon Parra-Michel, Aldo G. Orozco-Lugo, Roberto Carrasco-Alvarez	Full-hardware architectures for data-dependent superimposed training channel estimation.	SiPS	2011	DBLP DOI BibTeX RDF
1	Mehran Mozaffari Kermani, Arash Reyhani-Masoleh	Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform.	DFT	2011	DBLP DOI BibTeX RDF
1	Benjamin Ranft, Timo Schönwald, Bernd Kitt	Parallel matching-based estimation - a case study on three different hardware architectures.	Intelligent Vehicles Symposium	2011	DBLP DOI BibTeX RDF
1	Sheng-De Wang, Chih-Hung Weng	Algorithms and Hardware Architectures for Variable Block Size Motion Estimation.	UIC	2011	DBLP DOI BibTeX RDF
1	Christiane Maja Beuschel	Fully programmable LDPC decoder hardware architectures.		2010	RDF
1	Vladimir Tujillo-Olaya, Jaime Velasco-Medina	Hardware Architectures for Elliptic Curve Cryptoprocessors Using Polynomial and Gaussian Normal Basis over GF(2233).	Transactions on Computational Science	2010	DBLP DOI BibTeX RDF
1	Francesco Biscani	Multiplication of sparse Laurent polynomials and Poisson series on modern hardware architectures	CoRR	2010	DBLP BibTeX RDF
1	Camille Leroux, Ido Tal, Alexander Vardy, Warren J. Gross	Hardware architectures for Successive Cancellation Decoding of Polar Codes	CoRR	2010	DBLP BibTeX RDF
1	Aishwarya Nagarajan, Michael J. Schulte, Parameswaran Ramanathan	Galois field hardware architectures for network coding.	ANCS	2010	DBLP DOI BibTeX RDF
1	Florent de Dinechin, Mioara Joldes, Bogdan Pasca	Automatic generation of polynomial-based hardware architectures for function evaluation.	ASAP	2010	DBLP DOI BibTeX RDF
1	Jianzhou Li, Ramesh Karri	Compact hardware architectures for BLAKE and LAKE hash functions.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Mariam Kiran, Paul Richmond, Mike Holcombe, Lee Shawn Chin, David Worth, Chris Greenough	FLAME: simulating large populations of agents on parallel hardware architectures.	AAMAS	2010	DBLP DOI BibTeX RDF
1	Artur Schiefer, Volker Gruhn, Ruslan Hrushchak	VESBA: a middleware oriented architecture for virtualized embedded systems.	EDCC-CARS	2010	DBLP DOI BibTeX RDF
1	Mohamed Faouzi Atig, Ahmed Bouajjani, Sebastian Burckhardt, Madanlal Musuvathi	On the verification problem for weak memory models.	POPL	2010	DBLP DOI BibTeX RDF	lossy channel systems, program verification, infinite state systems, relaxed memory models
1	Andrea Marin, Maria Grazia Vigliotti	A general result for deriving product-form solutions in markovian models.	WOSP/SIPEW	2010	DBLP DOI BibTeX RDF	queueing theory, product form solutions
1	Akashi Satoh, Takeshi Sugawara, Takafumi Aoki	High-Performance Hardware Architectures for Galois Counter Mode.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung	Hardware architectures for eigenvalue computation of real symmetric matrices.	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Kylan Robinson, José G. Delgado-Frias	Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures.	ERSA	2009	DBLP BibTeX RDF
1	Akashi Satoh, Nicolas Sklavos	Compact and High-speed Hardware Architectures for Hash Function Tiger.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras, Atta Badii	A Practical Method for Testing High-Speed Networking Hardware Architectures.	ICNS	2009	DBLP DOI BibTeX RDF
1	Thaísa Leal da Silva, Fabio Pereira, Altamiro Amadeu Susin, Sergio Bampi, Luciano Volcan Agostini	High performance and low cost architecture for H.264/AVC CAVLD targeting HDTV.	SBCCI	2009	DBLP DOI BibTeX RDF	CAVLD, H.264/AVC, video compression, hardware architectures
1	Yahya Jan, Lech Józwiak	Survey of Advanced CABAC Accelerator Architectures for Future Multimedia.	ARC	2009	DBLP DOI BibTeX RDF	RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC
1	Yahya Jan, Lech Józwiak	CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF	RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC
1	Miroslav Knezevic, Ingrid Verbauwhede	Hardware evaluation of the Luffa hash family.	WESS	2009	DBLP DOI BibTeX RDF	Luffa hash algorithm, SHA-3 competition, ASIC implementations
1	Xin He, Jorgen Peddersen, Sri Parameswaran	LOP: a novel SRAM-based architecture for low power and high throughput packet classification.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	low-power, packet classification, hardware design
1	Viktor Pus, Jan Korenek	Fast and scalable packet classification using perfect hash functions.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, sram, packet classification
1	Victor Lotrich, Norbert Flocke, Mark Ponton, Beverly A. Sanders, Erik Deumens, Rodney J. Bartlett, Ajith Perera	An infrastructure for scalable and portable parallel programs for computational chemistry.	ICS	2009	DBLP DOI BibTeX RDF	coupled cluster methods, tensors, distributed arrays
1	Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Torrellas, J.-W. Lee, Xing Fang, Samuel P. Midkiff, David Wong	BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support.	MICRO	2009	DBLP DOI BibTeX RDF	atomic region, chunk-based architecture, compiler optimization, sequential consistency
1	Yifeng Qiu, Wael M. Badawy	The hardware architecture of a novel motion estimator with adaptive crossed quarter polar search patterns for H.264 encoding.	CCECE	2009	DBLP DOI BibTeX RDF
1	Yaohang Li, Douglas Wardell, Vincent W. Freeh	Resource-efficient computing paradigm for computational protein modeling applications.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Magdalena Slawiñska, Jaroslaw Slawinski, Vaidy S. Sunderam	Portable builds of HPC applications on diverse target platforms.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Yizhen Liu, Daxiong Xu, Dong Liu, Lingge Sun	A Fast and Configurable Pattern Matching Hardware Architecture for Intrusion Detection.	WKDD	2009	DBLP DOI BibTeX RDF
1	Won-Ki Jeong, Johanna Beyer, Markus Hadwiger, Amelio Vázquez Reina, Hanspeter Pfister, Ross T. Whitaker	Scalable and Interactive Segmentation and Visualization of Neural Processes in EM Datasets.	IEEE Trans. Vis. Comput. Graph.	2009	DBLP DOI BibTeX RDF
1	John Mylopoulos	Conceptual Modeling in the Time of the Revolution: Part II.	ER	2009	DBLP DOI BibTeX RDF
1	Lukasz Chomatek, Aneta Poniszewska-Maranda	Modern Approach for Building of Multi-Agent Systems.	ISMIS	2009	DBLP DOI BibTeX RDF
1	Roman Gumzej, Wolfgang A. Halang	A safety shell for UML-RT projects structure and methods of the corresponding UML pattern.	ISSE	2009	DBLP DOI BibTeX RDF	Safety shell, Real time, Pattern, Safety, UML-RT
1	Samarjit Chakraborty, Tulika Mitra, Abhik Roychoudhury, Lothar Thiele	Cache-aware timing analysis of streaming applications.	Real-Time Systems	2009	DBLP DOI BibTeX RDF	Timing analysis, Instruction cache, Streaming applications
1	Guido Marco Bertoni, Luca Breveglieri, Pasqualina Fragneto, Gerardo Pelosi	Parallel Hardware Architectures for the Cryptographic Tate Pairing.	I. J. Network Security	2008	DBLP BibTeX RDF
1	Andy M. Tyrrell	Evolvable Hardware Architectures and Their Role in Fault Tolerant Computational Systems.	KES	2008	DBLP DOI BibTeX RDF
1	Kyrre Glette, Jim Torresen, Paul Kaufmann, Marco Platzner	A Comparison of Evolvable Hardware Architectures for Classification Tasks.	ICES	2008	DBLP DOI BibTeX RDF
1	Abdulhadi Shoufan, Sorin A. Huss, Oliver Kelm, Sebastian Schipp	A Novel Rekeying Message Authentication Procedure Based on Winternitz OTS and Reconfigurable Hardware Architectures.	ReConFig	2008	DBLP DOI BibTeX RDF	Winternitz, Security, FPGA, Key Management, Coprocessor, Rekeying
1	Bruno Zatt, Altamiro Amadeu Susin, Sergio Bampi, Luciano Volcan Agostini	High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV.	SBCCI	2008	DBLP DOI BibTeX RDF	video coding, H.264/AVC, motion compensation, hardware architectures
1	Michela Becchi, Patrick Crowley	Efficient regular expression evaluation: theory to practice.	ANCS	2008	DBLP DOI BibTeX RDF
1	Yan Luo, Ke Xiang, Sanping Li	Acceleration of decision tree searching for IP traffic classification.	ANCS	2008	DBLP DOI BibTeX RDF	machine learning, FPGA, decision tree, traffic classification