Search results for "hardware design"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Bernhard Möller	Deductive Hardware Design: A Functional Approach.	Prospects for Hardware Foundations	1998	DBLP DOI BibTeX RDF
2	Giang Nguyen Huong, Yeoul Na, Seon Wook Kim	Applying frame layout to hardware design in FPGA for seamless support of cross calls in CPU-FPGA coupling architecture.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
2	Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar	Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency.	DAC	2010	DBLP DOI BibTeX RDF	scalable effort, support vector machines, low power design, recognition, mining, approximate computing
2	Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer	Soft connections: addressing the hardware-design modularity problem.	DAC	2009	DBLP DOI BibTeX RDF	high-level communication description
2	Rajesh Sankaran, Brygg Ullmer, Jagannathan Ramanujam, Karun Kallakuri, Srikanth Jandhyala, Cornelius Toole, Christopher Laan	Decoupling interaction hardware design using libraries of reusable electronics.	Tangible and Embedded Interaction	2009	DBLP DOI BibTeX RDF	blades and tiles, decoupling TUI design, hardware toolkit, reusable hardware, modularity
2	Roy Chaoming Hsu, Yaw-Yu Lee, Bin-Wen Kao, Din-Yuen Chan	Hardware Design of Shape-Preserving Contour Tracing for Object of Segmented Images.	PSIVT	2009	DBLP DOI BibTeX RDF	AMBA bus, SOC, Boundary Extraction, Contour Tracing
2	Brian Butka, Janusz Zalewski, Andrew J. Kornecki	Issues in Tool Qualification for Safety-Critical Hardware: What Formal Approaches Can and Cannot Do.	SAFECOMP	2009	DBLP DOI BibTeX RDF	Tool Qualification, Formal Methods, Safety-Critical Systems, Hardware Design, HDL, PLD
2	Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero	A hardware design of a massive-parallel, modular NN-based vector quantizer for real-time video coding.	Microprocessors and Microsystems - Embedded Hardware Design	2008	DBLP DOI BibTeX RDF
2	Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu	A Hardware Design for Camera-Based Power Management of Computer Monitor.	DSD	2008	DBLP DOI BibTeX RDF
2	Hiroomi Hikawa, Hirotada Fujimura	Hardware Design of Japanese Hand Sign Recognition System.	ICONIP	2008	DBLP DOI BibTeX RDF
2	Gerald Tripp	Regular expression matching with input compression: a hardware design for use within network intrusion detection systems.	Journal in Computer Virology	2007	DBLP DOI BibTeX RDF
2	Satnam Singh	New parallel programming techniques for hardware design.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
2	Chun-Hsian Huang, Kai-Jung Shih, Chao-Sheng Lin, Shih-Shiue Chang, Pao-Ann Hsiung	Dynamically Swappable Hardware Design in Partially Reconfigurable Systems.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Charles Tsen, Sonia Gonzalez-Navarro, Michael J. Schulte	Hardware design of a Binary Integer Decimal-based floating-point adder.	ICCD	2007	DBLP DOI BibTeX RDF
2	Liang-Kai Wang, Michael J. Schulte	A Decimal Floating-Point Divider Using Newton-Raphson Iteration.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	Newton-Raphson iteration, initial approximation, computer arithmetic, floating-point, division, hardware design, decimal
2	Kim Sandström, Ian Oliver	A UML Profile for Asynchronous Hardware Design.	SAMOS	2006	DBLP DOI BibTeX RDF
2	Chuan-Yung Tsai, Tung-Chien Chen, Liang-Gee Chen	Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder.	ICME	2006	DBLP DOI BibTeX RDF
2	Hadi Esmaeilzadeh, A. Moghimi, E. Ebrahimi, Caro Lucas, Zainalabedin Navabi, A. M. Fakhraie	DCim++: a C++ library for object oriented hardware design and distributed simulation.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Petr Matousek, Ales Smrcka, Tomás Vojnar	High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design.	CHARME	2005	DBLP DOI BibTeX RDF
2	Xiang Xie, Guolin Li, Dongmei Li, Chun Zhang, Zhihua Wang	A new near-lossless image compression algorithm suitable for hardware design in wireless endoscopy system.	ICIP	2005	DBLP DOI BibTeX RDF
2	Lin Zhong, Mike Sinclair, Niraj K. Jha	A personal-area network of low-power wireless interfacing devices for handhelds: system and hardware design.	Mobile HCI	2005	DBLP DOI BibTeX RDF	user interface, low power design, bluetooth, handhelds, personal-area network
2	Ali Ahmadi, Md. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide	A parallel hardware design for parametric active contour models.	AVSS	2005	DBLP DOI BibTeX RDF
2	Fernando Rincón, Francisco Moya, Jesús Barba, Juan Carlos López	Model Reuse through Hardware Design Patterns.	DATE	2005	DBLP DOI BibTeX RDF
2	Petcharat Burapathana, Proadpran Pitsatorn, Boonchai Sowanwanichkul	An Applying Aspect-Oriented Concept to Sequential Logic Design.	ITCC	2005	DBLP DOI BibTeX RDF	Aspect-oriented concept, Hardware design and Sequential logic, Reusability, Crosscutting
2	Ma José Canet, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat, Eduardo R. de Lima	Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2.	FPL	2004	DBLP DOI BibTeX RDF
2	Imed Aouadi, Omar Hammami	Analysis and Hardware Design of a Scalable Dual JPEG-2000 Entropy Coder.	DSD	2004	DBLP DOI BibTeX RDF
2	Donna Nakano, Erric Solomon	Task oriented visual interface for debugging timing problems in hardware design.	AVI	2004	DBLP DOI BibTeX RDF	cognitive model of users, information visualization, visual interface design
2	He Hu, Da-you Liu, Xiaoyong Du	Semi-automatic hardware design using ontologies.	ICARCV	2004	DBLP DOI BibTeX RDF
2	Robertas Damasevicius, Vytautas Stuikys	Application of UML for hardware design based on design process model.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Nico Bannow, Karsten Haug	Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications.	DATE	2004	DBLP DOI BibTeX RDF
2	Apostolos Dollas, Kyprianos Papademetriou, Euripides Sotiriades, Dimitrios Theodoropoulos, Iosif Koidis, George Vernardos	A Case Study on Rapid Prototyping of Hardware Systems: The Effect of CAD Tool Capabilities, Design Flows, and Design Styles.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF	FPGA, Hardware design, Design flow, CAD tools
2	Naehyuck Chang, Ikhwan Lee	Embedded System Hardware Design Course Track For Cs Students.	MSE	2003	DBLP DOI BibTeX RDF
2	Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada	Comparative Study On Verilog-Based And C-Based Hardware Design Education.	MSE	2003	DBLP DOI BibTeX RDF
2	Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai	Hardware Design with a Scripting Language.	FPL	2003	DBLP DOI BibTeX RDF
2	Arvind	Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk.	MEMOCODE	2003	DBLP DOI BibTeX RDF
2	Robertas Damasevicius, Giedrius Majauskas, Vytautas Stuikys	Application of design patterns for hardware design.	DAC	2003	DBLP DOI BibTeX RDF	system-level design processes, UML, design patterns, metaprogramming, wrapping
2	Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim	Gene Finding Using Evolvable Reasoning Hardware.	ICES	2003	DBLP DOI BibTeX RDF	evolving hardware system, evolutionary hardware design methodologies, genome informatics
2	Vincenza Carchiolo, Michele Malgeri, Giuseppe Mangioni	From Specification to Hardware Device: A Synthesis Algorithm.	ICFEM	2003	DBLP DOI BibTeX RDF	Rapid System Prototyping, Synthesis, Hardware Design
2	Shaz Qadeer, Serdar Tasiran	Promising Directions in Hardware Design Verification (invited). (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF
2	Byoungro So, Mary W. Hall, Pedro C. Diniz	A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems.	PLDI	2002	DBLP DOI BibTeX RDF	reuse analysis, design space exploration, loop transformations, data dependence analysis
2	Naoto Kaneko, Hideharu Amano	A General Hardware Design Model for Multicontext FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
2	Jordi Cortadella, Alexandre Yakovlev, Grzegorz Rozenberg (eds.)	Concurrency and Hardware Design, Advances in Petri Nets	Concurrency and Hardware Design	2002	DBLP BibTeX RDF
2	William W. LaRue, Sherry Solden, Bishnupriya Bhattacharya	Functional and Performance Modeling of Concurrency in VCC.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
2	Josep Carmona, Jordi Cortadella, Enric Pastor	Synthesis of Reactive Systems: Application to Asynchronous Circuit Design.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
2	Peter A. Beerel, Aiguo Xie	Performance Analysis of Asynchronous Circuits Using Markov Chains.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
2	Mark B. Josephs, Dennis P. Furey	A Programming Approach to the Design of Asynchronous Logic Blocks.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
2	Walter Vogler, Ralf Wollowski	Decomposition in Asynchronous Circuit Design.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
2	Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe	Modeling and Designing Heterogeneous Systems.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
2	Jesper B. Møller, Henrik Hulgaard, Henrik Reif Andersen	Timed Verification of Asynchronous Circuits.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
2	Igor Benko, Jo C. Ebergen	Composing Snippets.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
2	Victor Varshavsky, Vyacheslav Marakhovsky	GALA (Globally Asynchronous - Locally Arbitrary) Design.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
2	Chun-Yueh Huang, Gwo-Jeng Yu, Bin-Da Liu	A hardware design approach for merge-sorting network.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Alvin R. Albrecht, Alan J. Hu	Register Transformations with Multiple Clock Domains.	CHARME	2001	DBLP DOI BibTeX RDF
2	Krzysztof Mroczek	Shape-Adaptive DCT Algorithm - Hardware Optimized Redesign.	CAIP	2001	DBLP DOI BibTeX RDF	shape-adaptive DCT, hardware design
2	Steven D. Johnson, Yanhong A. Liu, Yuchen Zhang	A Systematic Incrementalization Technique and Its Application to Hardware Design.	CHARME	1999	DBLP DOI BibTeX RDF	design derivation, floating point operations, Formal methods, hardware verification, formal synthesis, transformational programming
2	George Economakos, George K. Papakonstantinou	Refinement and Property Checking in High-Level Synthesis using Attribute Grammars.	CHARME	1999	DBLP DOI BibTeX RDF
2	Jan Philipps, Peter Scholz	Formal Verification and Hardware Design with Statecharts.	Prospects for Hardware Foundations	1998	DBLP DOI BibTeX RDF
2	Wayne Luk, Steve McKeever	Pebble: A Language for Parametrised and Reconfigurable Hardware Design.	FPL	1998	DBLP DOI BibTeX RDF
2	Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri	Hardware Software Partitioning with Integrated Hardware Design Space Exploration.	DATE	1998	DBLP DOI BibTeX RDF	Hadware/Software Partitioning, Genetic Algorithms, Design Space Exploration, Codesign
2	Guido Post, Andrea Müller, Thorsten Grötker	A System-Level Co-Verification Environment for ATM Hardware Design.	DATE	1998	DBLP DOI BibTeX RDF	test bench design and reuse, ATM hardware design, system design methodology, co-simulation, interface modeling, co-verification
2	Sheu-Chih Cheng, Hsueh-Ming Hang	The Impact of Rate Control Algorithms on Video Codec Hardware Design. (PDF / PS)	ICIP	1997	DBLP DOI BibTeX RDF	rate control algorithms, video codec hardware design, system-level VLSI design, optimal rate-distortion performance, internal buffer size, performance, video coding, image quality, VLSI implementation, video codecs, DCT coefficients, picture quality, hardware cost
2	Maria Brielmann, Franz-Josef Rammig	Evaluating Hardware Design Principles for the Development of Computer Based Systems.	ECBS	1996	DBLP DOI BibTeX RDF	Petri nets, System Engineering, Development Process, Hardware Design, Abstraction Levels, Computer Based Systems
2	Michael J. Schulte, Earl E. Swartzlander Jr.	Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	arithmetic algorithms, computer arithmetic, hardware, Interval arithmetic, precision, coprocessor, numerical computations
2	Mark Genoe, Paul Vanoostende, Geert van Wauwe	On the use of VHDL-based behavioral synthesis for telecom ASIC design.	ISSS	1995	DBLP DOI BibTeX RDF	Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
2	Jay K. Adams, John Alan Miller, Donald E. Thomas	Execution-time profiling for multiple-process behavioral synthesis. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model
2	Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang	VLSI design of densely-connected array processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	densely-connected array processors, paralleled array processors, real-time signal processing, problem mapping, high potential computational bandwidth, local interconnection, synaptic operators, CNN processing engine, hardware design problems, CNN accelerator design, digital-programmable synapses, flexible digital interface, current-mode CMOS circuits, 2.0 /spl mu/m CMOS technology, edge detection operation, image processing, image processing, parallel processing, VLSI, edge detection, signal processing, VLSI design, heterogeneous computing, CMOS integrated circuits, cellular neural networks, cellular neural nets
2	Michael J. Schulte, Earl E. Swartzlander Jr.	A coprocessor for accurate and reliable numerical computations. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	reliable numerical computations, direct hardware support, logic design, digital arithmetic, interval arithmetic, hardware design, coprocessors, coprocessor, numerical computations
2	John Schewel, Michael Thornburg, Steve Casselman	Transformable computers & hardware object technology. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	transformable computers, hardware object technology, reconfigurable aspects, computationally intensive software algorithms, on-the-fly use, field programmable gate arrays, field programmable gate arrays, programming, reconfigurable architectures, programmable logic arrays, hardware design, performance gain
2	Alberto Broggi	Word parallelism vs spatial parallelism: a performance optimization technique on the PAPRICA system.	PDP	1995	DBLP DOI BibTeX RDF	word parallelism, spatial parallelism, performance optimization technique, PAPRICA system, hardware efficiency, SIMD systems, data bus efficiency, packed data sets, processing array, optimizing assembly-to-assembly translator, automatic conversion, binary data sets, thinning filter, performance evaluation, parallel architectures, optimisation, parallel machines, hardware design, data storage, program interpreters, external memory, dynamic mapping, assembly language
2	Marco Platzner, Bernhard Rinner, Reinhold Weiss	A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs.	PDP	1995	DBLP DOI BibTeX RDF	distributed computer architecture, multi-DSP, application-specific computer architecture, constraint-check-function, performance, FPGAs, parallel architectures, computer architecture, digital simulation, hardware design, special purpose computers, design strategies, qualitative simulation
2	Ganesh Gopalakrishnan, Richard Fujimoto	Design and Verification of the Rollback Chip Using HOP: A Case Study of Formal Methods Applied to Hardware design.	ACM Trans. Comput. Syst.	1993	DBLP DOI BibTeX RDF
2	Stefan Rüping, Ulrich Rückert, Karl Goser	Hardware Design for Self-Organizing Feature Maps with Binary Input Vectors.	IWANN	1993	DBLP DOI BibTeX RDF
2	T. C. Choinski, T. T. Tylaska	Generation of Digit Reversed Address Sequences for Fast Fourier Transforms.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	digit reversed address sequences generation, radix-4, binary counter, address sequences, fast Fourier transforms, fast Fourier transforms, hardware design, computerised signal processing, radix-2
2	Hiroto Yasuura, Nagisa Ishiura	Semantics of a Hardware Design Language for Japanese Standardization.	DAC	1989	DBLP DOI BibTeX RDF
2	Kenneth W. Neves	Growing discord: programming philosophy and hardware design.	SC	1988	DBLP BibTeX RDF
2	Paul J. Drongowski, Jwahar R. Bami, Ranganathan Ramaswamy, Sundar Iyengar, Tsu-Hua Wang	A Graphical Hardware Design Language.	DAC	1988	DBLP BibTeX RDF
1	Guoliang He, Naixue Xiong, Laurence Tianruo Yang, Tai-Hoon Kim, Ching-Hsien Hsu, Yuanxiang Li, Ting Hu	Evolvable hardware design based on a novel simulated annealing in an embedded system.	Concurrency and Computation: Practice and Experience	2012	DBLP DOI BibTeX RDF
1	Yo-Hsien Lin, Jong-Chen Chen	A Hardware Design of Neuromolecular Network with Enhanced Evolvability: A Bioinspired Approach.	J. Electrical and Computer Engineering	2012	DBLP DOI BibTeX RDF
1	Fatih Say, Cüneyt F. Bazlamaçci	A reconfigurable computing platform for real time embedded applications.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Girma S. Tewolde, Darrin M. Hanna, Richard E. Haskell	A modular and efficient hardware architecture for particle swarm optimization algorithm.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Nuno Sebastião, Nuno Roma, Paulo F. Flores	Hardware accelerator architecture for simultaneous short-read DNA sequences alignment with enhanced traceback phase.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	María José Canet, Javier Valls, Vicenc Almenar, José Marín-Roig	FPGA implementation of an OFDM-based WLAN receiver.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Gyu Sang Choi, Ingyu Lee, Mankyu Sung, Choongjae Im	A hybrid SSD with PRAM and NAND Flash memory.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Yusuf Adibelli, Mustafa Parlak, Ilker Hamzaoglu	Computation and power reduction techniques for H.264 intra prediction.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Rabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser	A fast MPSoC virtual prototyping for intensive signal processing applications.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Prodromos Chatziagorakis, Georgios Ch. Sirakoulis, John N. Lygouras	Design automation of cellular neural networks for data fusion applications.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Merve Peyic, Hakan Baba, Erdem Guleyuboglu, Ilker Hamzaoglu, Mehmet Keskinoz	A low power multi-rate decoder hardware for IEEE 802.11n LDPC codes.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Zheng Ding, Feng Zhao, Wei Shu, Min-You Wu	Face detection system for SVGA source with hecto-scale frame rate on FPGA board.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Po-Yueh Chen, Chao-Chin Wu, Ying-Jie Jiang	Bitmask-based code compression methods for balancing power consumption and code size for hard real-time embedded systems.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Tobias Schumacher, Christian Plessl, Marco Platzner	IMORC: An infrastructure and architecture template for implementing high-performance reconfigurable FPGA accelerators.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Paolo Zicari, Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo	Low-cost FPGA stereo vision system for real time disparity maps calculation.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Omesh Mutukuda, Andy Ye, Gul Khan	Utilizing multi-bit connections to improve the area efficiency of unidirectional routing resources for routing multi-bit signals on FPGAs.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Juan Carlos Pichel, Francisco F. Rivera, Marcos Fernández, Aurelio Rodriguez	Optimization of sparse matrix-vector multiplication using reordering techniques on GPUs.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar	Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Dongdong Chen, Seok-Bum Ko	A dynamic non-uniform segmentation method for first-order polynomial function evaluation.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Ruymán Reyes, Francisco de Sande	Optimization strategies in different CUDA architectures using llCoMP.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Robert Czerwinski, Dariusz Kania	Area and speed oriented synthesis of FSMs for PAL-based CPLDs.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Antony W. Savich, Medhat Moussa, Shawki Areibi	A scalable pipelined architecture for real-time computation of MLP-BP neural networks.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Jose Rodrigo Sanjurjo, Margarita Amor, Montserrat Bóo, Ramon Doallo	High-performance Monte Carlo radiosity on GPU based on scene partitioning.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Kishor Sarawadekar, Harihar Bharat Indana, Deep Bera, Swapna Banerjee	VLSI-DSP based real time solution of DSC-SRI for an ultrasound system.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF