Search results for "hardware functions"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Jean Paul Calvez, Olivier Pasquier	Performance assessment of embedded Hw/Sw systems. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	embedded Hw/Sw systems, VLSI components, heterogeneous multiprocessor architectures, complex real-time applications, performance indexes, real-time event occurrences, software tasks, hardware functions, real-time performance analyzer, MCSE methodology, performance evaluation, real-time systems, VLSI, systems analysis, application specific integrated circuits, ASIC, performance assessment, event trace
1	Jih-Ching Chiu, Ta-Li Yeh, Mun-Kit Leong	The Software and Hardware Integration Linker for Reconfigurable Embedded System.	CSE	2009	DBLP DOI BibTeX RDF
1	Colin J. Ihrig, Justin Stander, Alex K. Jones	Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Björn Osterloh, Harald Michalik, Björn Fiethe, F. Bubenhagen	Enhancements of reconfigurable System-on-Chip Data Processing Units for Space Application.	AHS	2007	DBLP DOI BibTeX RDF
1	Hak-Man Kim, Jong-Joo Lee, Dong-Joo Kang	A Platform for Smart Substations.	FGCN	2007	DBLP DOI BibTeX RDF
1	I-Hsuan Huang, Chih-Chun Wang, Shih-Min Chu, Cheng-Zen Yang	Function-Level Multitasking Interface Design in an Embedded Operating System with Reconfigurable Hardware.	EUC	2007	DBLP DOI BibTeX RDF	hardware function, FPGA-based computer, ?C/OS, Reconfigurable computing, multitasking
1	Raymond R. Hoare, Alex K. Jones, Dara Kusic, Joshua Fazekas, John Foster, Shen Chih Tung, Michael L. McCloud	Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions.	EURASIP J. Adv. Sig. Proc.	2006	DBLP DOI BibTeX RDF
1	T. Taher, Tarek A. El-Ghazawi	Exploiting processing locality through paging configurations in multitasked reconfigurable systems.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Kuniya Shinozaki, Yousuke Oda, Satoshi Tsuda, Ryohei Nakatsu, Akitsugu Iwatani	Study of Dance Entertainment Using Robots.	Edutainment	2006	DBLP DOI BibTeX RDF
1	Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster	An FPGA-based VLIW processor with custom hardware execution.	FPGA	2005	DBLP DOI BibTeX RDF	NIOS, parallelism, compiler, synthesis, kernels, VLIW
1	Hankook Jang, Sang-Hwa Chung, Soo-Cheol Oh	Implementation of a Hybrid TCP/IP Offload Engine Prototype.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
1	Eric J. Swankoski, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	A Parallel Architecture for Secure FPGA Symmetric Encryption.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Mark A. Franklin, Vinayak Joshi	SimplePipe: A Simulation Tool for Task Allocation and Design of Processor Pipelines with Application to Network Processors.	MASCOTS	2004	DBLP DOI BibTeX RDF
1	Carsten Reuter, Javier Martín-Langerwerf, Hans-Joachim Stolberg, Peter Pirsch	Performance Estimation of Streaming Media Applications for Reconfigurable Platforms.	SAMOS	2004	DBLP DOI BibTeX RDF
1	María Dolores Valdés, María José Moure, Camilo Quintáns, Enrique Mandado	A Data Acquisition Reconfigurable Coprocessor for Virtual Instrumentation Applications.	FPL	2003	DBLP DOI BibTeX RDF
1	Abhijit Chatterjee, Manuel A. d'Abreu	The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	fault-tolerant linear digital state variable systems, gain matrix, single faulty operators, hardware optimization, hardware functions, fault tolerant computing, error detection, error detection, error correction, error correction, error propagation
1	Mark Newsome, Cherri M. Pancake, Christopher Ward	Visual Execution of Assembly Language Programs.	ACM Conference on Computer Science	1993	DBLP DOI BibTeX RDF	Motorola 68000
1	Edward G. Okie, James D. Arthur	Implicit-Specification Errors and Automatic, Trace-Based Debugging.	ACM Conference on Computer Science	1993	DBLP DOI BibTeX RDF
1	Andreas Geyer-Schulz, Johann Mitlöhner, Alfred Taudes	An APL-Simulator of Non-Von Neumann Computer Architectures.	APL	1990	DBLP DOI BibTeX RDF	APL
1	Per Stenström, Lars Philipson	A Layered Emulator for Design Evaluation of MIMD Multiprocessors with Shared Memory.	PARLE	1987	DBLP DOI BibTeX RDF
1	Kenichiro Noguchi, Isao Ohnishi, Hiroshi Morita	Design considerations for a heterogeneous tightly-coupled multiprocessor system.	AFIPS National Computer Conference	1975	DBLP DOI BibTeX RDF