Search results for "hardware verification"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Darren Galpin, Cormac Driver, Siobhán Clarke	Modelling hardware verification concerns specified in the e language: an experience report.	AOSD	2009	DBLP DOI BibTeX RDF	theme/uml, hardware verification, aspect-oriented modelling, e
3	Gianpiero Cabodi, Marco Murciano	BDD-Based Hardware Verification.	SFM	2006	DBLP DOI BibTeX RDF
3	Mandayam K. Srivas, Harald Rueß, David Cyrluk	Hardware Verification Using PVS.	Formal Hardware Verification	1997	DBLP DOI BibTeX RDF
3	David Cyrluk, Mandayam K. Srivas	Theorem proving: not an esoteric diversion, but the unifying framework for industrial verification. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	industrial hardware verification, industrial verification, formal verification, logic testing, theorem proving, theorem prover, hardware verification
2	Sharad Malik	Hardware Verification: Techniques, Methodology and Solutions.	TACAS	2008	DBLP DOI BibTeX RDF
2	Aarti Gupta	From Hardware Verification to Software Verification: Re-use and Re-learn.	Haifa Verification Conference	2007	DBLP DOI BibTeX RDF
2	Husam Abu-Haimed, David L. Dill, Sergey Berezin	A Refinement Method for Validity Checking of Quantified First-Order Formulas in Hardware Verification.	FMCAD	2006	DBLP DOI BibTeX RDF
2	Aarti Gupta, Malay K. Ganai, Chao Wang	SAT-Based Verification Methods and Applications in Hardware Verification.	SFM	2006	DBLP DOI BibTeX RDF
2	Shmuel Ur	A Panel: Unpaved Road Between Hardware Verification and Software Testing Techniques.	Haifa Verification Conference	2006	DBLP DOI BibTeX RDF
2	Ghiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione	TheoSim: combining symbolic simulation and theorem proving for hardware verification.	SBCCI	2004	DBLP DOI BibTeX RDF	theorem proving, symbolic simulation, hardware verification
2	Solange Coupet-Grimal, Line Jakubiec	Certifying circuits in Type Theory.	Formal Asp. Comput.	2004	DBLP DOI BibTeX RDF	Co-induction, Formal methods, Type theory, Dependent types, Extraction, Hardware verification
2	Fabrice Baray, Philippe Codognet, Daniel Diaz, Henri Michel	Code-Based Test Generation for Validation of Functional Processor Descriptions.	TACAS	2003	DBLP DOI BibTeX RDF	Code-based test generation, functional hardware verification, constraint solving techniques
2	Armin Biere, Wolfgang Kunz	SAT and ATPG: Boolean engines for formal hardware verification.	ICCAD	2002	DBLP DOI BibTeX RDF
2	Haiyan Xiong, Paul Curzon, Sofiène Tahar, Ann Blandford	Formally Linking MDG and HOL Based on a Verified MDG System.	IFM	2002	DBLP DOI BibTeX RDF	hybrid verification systems, deductive theorem proving, symbolic state enumeration, usability verification, hardware verification
2	J. Strother Moore	A Grand Challenge Proposal for Formal Methods: A Verified Stack.	10th Anniversary Colloquium of UNU/IIST	2002	DBLP DOI BibTeX RDF	simulation, modeling, model checking, theorem proving, software verification, hardware verification
2	V. K. Pisini, Sofiène Tahar, Paul Curzon, Otmane Aït Mohamed, Xiaoyu Song	Formal hardware verification by integrating HOL and MDG.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
2	Deepak Kapur, Mahadevan Subramaniam	Using an induction prover for verifying arithmetic circuits.	STTT	2000	DBLP DOI BibTeX RDF	Induction, Automated reasoning, Decision procedures, Rewriting, Arithmetic circuits, Hardware verification
2	David L. Dill	Alternative Approaches to Hardware Verification (abstract).	CAV	1999	DBLP DOI BibTeX RDF
2	Steven D. Johnson, Yanhong A. Liu, Yuchen Zhang	A Systematic Incrementalization Technique and Its Application to Hardware Design.	CHARME	1999	DBLP DOI BibTeX RDF	design derivation, floating point operations, Formal methods, hardware verification, formal synthesis, transformational programming
2	Sofiène Tahar, Paul Curzon, Jianping Lu	Three Approaches to Hardware Verification: HOL, MDG and VIS Compared.	FMCAD	1998	DBLP DOI BibTeX RDF
2	Ralf Reetz, Klaus Schneider, Thomas Kropf	Formal Specification in VHDL for Hardware Verification.	DATE	1998	DBLP DOI BibTeX RDF
2	Thomas Kropf (eds.)	Formal Hardware Verification - Methods and Systems in Comparison	Formal Hardware Verification	1997	DBLP BibTeX RDF
2	Thomas Kropf	Appendix: The Common Book Examples.	Formal Hardware Verification	1997	DBLP DOI BibTeX RDF
2	Klaus Schneider, Thomas Kropf	The C@S System.	Formal Hardware Verification	1997	DBLP DOI BibTeX RDF
2	Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Zijian Zhou	Verification with Abstract State Machines Using MDGs.	Formal Hardware Verification	1997	DBLP DOI BibTeX RDF
2	Jørgen Staunstrup	Design Verification Using Synchronized Transitions.	Formal Hardware Verification	1997	DBLP DOI BibTeX RDF
2	Scott Hazelhurst, Carl-Johan H. Seger	Symbolic Trajectory Evaluation.	Formal Hardware Verification	1997	DBLP DOI BibTeX RDF
2	Kathi Fisler, Robert P. Kurshan	Verifying VHDL Designs with COSPAN.	Formal Hardware Verification	1997	DBLP DOI BibTeX RDF
2	Reinhard Bündgen, Wolfgang Küchlin, Werner Lauterbach	Verification of the Sparrow Processor.	ECBS	1996	DBLP DOI BibTeX RDF	symbolic hardware simulation, equational specifications, term rewriting, Hardware verification
2	Mark Aagaard, Carl-Johan H. Seger	The formal verification of a pipelined double-precision IEEE floating-point multiplier.	ICCAD	1995	DBLP DOI BibTeX RDF	ANSI/IEEE Std 754-1985, model checking, theorem proving, floating-point arithmetic, Hardware verification
2	David Cyrluk, Paliath Narendran	Ground Temporal Logic: A Logic for Hardware Verification.	CAV	1994	DBLP DOI BibTeX RDF
2	Kees G. W. Goossens	Stucture and Behaviour in Hardware Verification.	HUG	1993	DBLP DOI BibTeX RDF
2	Wei Si Jiang, William G. Wee	A frame-based approach to hardware verification (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
1	Bashir M. Al-Hashimi, Ronny Morad	Accelerators and emulators: Can they become the platform of choice for hardware verification?	DATE	2012	DBLP BibTeX RDF
1	Alexander Kamkin	Simulation-based hardware verification with time-abstract models.	EWDTS	2011	DBLP DOI BibTeX RDF
1	Leonid Ryzhyk, John Keys, Balachandra Mirla, Arun Raghunath, Mona Vij, Gernot Heiser	Improved device driver reliability through hardware verification reuse.	ASPLOS	2011	DBLP DOI BibTeX RDF
1	Christian Müller, Wolfgang Paul	Complete Formal Hardware Verification of Interfaces for a FlexRay-Like Bus.	CAV	2011	DBLP DOI BibTeX RDF
1	Robert H. Bell Jr., Matyas Sustik, David W. Cummings, Jonathan R. Jackson	Automatic performance model synthesis from hardware verification models.	ICPE	2011	DBLP DOI BibTeX RDF
1	Kiarash Amiri, Michael Wu, Melissa Duarte, Joseph R. Cavallaro	Physical layer algorithm and hardware verification of MIMO relays using cooperative partial detection.	ICASSP	2010	DBLP DOI BibTeX RDF
1	Moshe Emmer, Zurab Khasidashvili, Konstantin Korovin, Andrei Voronkov	Encoding industrial hardware verification problems into effectively propositional logic.	FMCAD	2010	DBLP BibTeX RDF
1	Eyal Bin, Alaa Ghanayim, Karen Holtz, Eitan Marcus, Ronny Morad, Ofer Peled, Michal Rimon, Gil Shurek, Elena Tsanko	Ontology-Based Tools in the Service of Hardware Verification.	SEKE	2010	DBLP BibTeX RDF
1	Lyes Benalycherif, Anthony McIsaac	A Semantic Condition for Data Independence and Applications in Hardware Verification.	Electr. Notes Theor. Comput. Sci.	2009	DBLP DOI BibTeX RDF
1	Kunio Miyamoto, Hidehiko Tanaka	Real Hardware Verification by Software for Bootstrap Using TSC.	DASC	2009	DBLP DOI BibTeX RDF
1	Shujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao	Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Natarajan Shankar	Automated deduction for verification.	ACM Comput. Surv.	2009	DBLP DOI BibTeX RDF
1	Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong	Random stimulus generation with self-tuning.	CSCWD	2009	DBLP DOI BibTeX RDF
1	Leonardo Mendonça de Moura, Nikolaj Bjørner	Generalized, efficient array decision procedures.	FMCAD	2009	DBLP DOI BibTeX RDF
1	Orna Grumberg	3-Valued Abstraction for (Bounded) Model Checking.	ATVA	2009	DBLP DOI BibTeX RDF
1	Nathan Kitchen, Andreas Kuehlmann	A Markov Chain Monte Carlo Sampler for Mixed Boolean/Integer Constraints.	CAV	2009	DBLP DOI BibTeX RDF
1	Mark H. Liffiton, Karem A. Sakallah	Generalizing Core-Guided Max-SAT.	SAT	2009	DBLP DOI BibTeX RDF
1	Alexander Heußner, Tristan Le Gall, Grégoire Sutre	Extrapolation-Based Path Invariants for Abstraction Refinement of Fifo Systems.	SPIN	2009	DBLP DOI BibTeX RDF
1	Sergey Tverdyshev, Eyad Alkassar	Efficient Bit-Level Model Reductions for Automated Hardware Verification.	TIME	2008	DBLP DOI BibTeX RDF
1	Tamarah Arons, Elad Elster, Shlomit Ozer, Jonathan Shalev, Eli Singerman	Efficient Symbolic Simulation of Low Level Software.	DATE	2008	DBLP DOI BibTeX RDF
1	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	A Mutation Model for the SystemC TLM 2.0 Communication Interfaces.	DATE	2008	DBLP DOI BibTeX RDF
1	Claude Helmstetter, Olivier Ponsini	A Comparison of Two SystemC/TLM Semantics for Formal Verification.	MEMOCODE	2008	DBLP DOI BibTeX RDF
1	Kenneth L. McMillan	Proofs, Interpolants, and Relevance Heuristics.	Haifa Verification Conference	2008	DBLP DOI BibTeX RDF
1	Limor Fix	Fifteen Years of Formal Property Verification in Intel.	25 Years of Model Checking	2008	DBLP DOI BibTeX RDF	formal property verification, Model checking, formal specification
1	Gaurav Singh, Sandeep K. Shukla	Verifying Compiler Based Refinement of BluespecTM.	SPIN	2008	DBLP DOI BibTeX RDF	Bluespec System Verilog (BSV), Formal Verification, Hardware Designs, SPIN Model Checker
1	Michal Moskal	Rocket-Fast Proof Checking for SMT Solvers.	TACAS	2008	DBLP DOI BibTeX RDF
1	Anubhav Gupta, Kenneth L. McMillan, Zhaohui Fu	Automated assumption generation for compositional verification.	Formal Methods in System Design	2008	DBLP DOI BibTeX RDF	L*, Model checking, Formal verification, Decision tree, SAT, Compositional verification, Assume-guarantee
1	Markus Behle	On threshold BDDs and the optimal variable ordering problem.	J. Comb. Optim.	2008	DBLP DOI BibTeX RDF	Threshold BDD, 0/1 integer programming, Optimal variable ordering, Variable ordering spectrum, Binary decision diagram, Knapsack
1	Yehuda Naveh, Michal Rimon, Itai Jaeger, Yoav Katz, Michael Vinov, Eitan s Marcu, Gil Shurek	Constraint-Based Random Stimuli Generation for Hardware Verification.	AI Magazine	2007	DBLP BibTeX RDF
1	Neil Evans, Wilson Ifill	Hardware Verification and Beyond: Using B at AWE.	B	2007	DBLP DOI BibTeX RDF
1	Haiyan Xiong, Paul Curzon, Sofiène Tahar, Ann Blandford	Providing a formal linkage between MDG and HOL.	Formal Methods in System Design	2007	DBLP DOI BibTeX RDF	Verification system correctness, Hybrid verification systems, Formal hardware verification, Usability verification
1	Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham	Improved verification of hardware designs through antecedent conditioned slicing.	STTT	2007	DBLP DOI BibTeX RDF	LTL property, Antecedent conditioned slicing, Verilog RTL, Model checking, Program slicing, Hardware description languages, Hardware verification
1	Nathan Kitchen, Andreas Kuehlmann	Stimulus generation for constrained random simulation.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Edward Smith	A Logic for GSTE.	FMCAD	2007	DBLP DOI BibTeX RDF
1	Praveen Tiwari, Raj S. Mitra, Manu Chopra, Alok Jain	Tutorial T4B: Formal Assertion-Based Verification in Industrial Setting.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Debdeep Mukhopadhyay, Gaurav Sengar, Dipanwita Roy Chowdhury	Hierarchical Verification of Galois Field Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Ilya Wagner, Valeria Bertacco, Todd M. Austin	Microprocessor Verification via Feedback-Adjusted Markov Models.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Anubhav Gupta, Kenneth L. McMillan, Zhaohui Fu	Automated Assumption Generation for Compositional Verification.	CAV	2007	DBLP DOI BibTeX RDF
1	David M. Russinoff	A Mathematical Approach to RTL Verification.	CAV	2007	DBLP DOI BibTeX RDF
1	Markus Behle	On Threshold BDDs and the Optimal Variable Ordering Problem.	COCOA	2007	DBLP DOI BibTeX RDF
1	Yunja Choi	From NuSMV to SPIN: Experiences with model checking flight guidance systems.	Formal Methods in System Design	2007	DBLP DOI BibTeX RDF	Flight guidance systems, Model checking, SPIN, NuSMV
1	Carsten Sinz	Visualizing SAT Instances and Runs of the DPLL Algorithm.	J. Autom. Reasoning	2007	DBLP DOI BibTeX RDF	SAT instance, DPLL procedure
1	Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya	Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Valeria Bertacco	Scalable Hardware Verification with Symbolic Simulation.		2006	DOI RDF
1	Marco Bernardo, Alessandro Cimatti (eds.)	Formal Methods for Hardware Verification, 6th International School on Formal Methods for the Design of Computer, Communication, and Software Systems, SFM 2006, Bertinoro, Italy, May 22-27, 2006, Advanced Lectures	SFM	2006	DBLP BibTeX RDF
1	Yehuda Naveh, Michal Rimon, Itai Jaeger, Yoav Katz, Michael Vinov, Eitan Marcus, Gil Shurek	Constraint-Based Random Stimuli Generation for Hardware Verification.	AAAI	2006	DBLP BibTeX RDF
1	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Hardware Design and Simulation for Verification.	SFM	2006	DBLP DOI BibTeX RDF
1	John Harrison	Floating-Point Verification Using Theorem Proving.	SFM	2006	DBLP DOI BibTeX RDF
1	Alessandro Cimatti, Roberto Sebastiani	Building Efficient Decision Procedures on Top of SAT Solvers.	SFM	2006	DBLP DOI BibTeX RDF
1	Koen Claessen, Jan-Willem Roorda	An Introduction to Symbolic Trajectory Evaluation.	SFM	2006	DBLP DOI BibTeX RDF
1	Panagiotis Manolios	Refinement and Theorem Proving.	SFM	2006	DBLP DOI BibTeX RDF
1	Rolf Drechsler, Görschwin Fey	Automatic Test Pattern Generation.	SFM	2006	DBLP DOI BibTeX RDF
1	Warren A. Hunt Jr., Erik Reeber	A SAT-based procedure for verifying finite state machines in ACL2.	ACL2	2006	DBLP DOI BibTeX RDF	satisfiability solving, theorem proving, hardware verification, ACL2
1	Erik Reeber, Jun Sawada	Combining ACL2 and an automated verification tool to verify a multiplier.	ACL2	2006	DBLP DOI BibTeX RDF	model checking, theorem proving, hardware verification
1	Hossein M. Sheini, Karem A. Sakallah	SMT(CLU): a step toward scalability in system verification.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Jianbin Tan, George S. Avrunin, Lori A. Clarke	Managing space for finite-state verification.	ICSE	2006	DBLP DOI BibTeX RDF	FLAVERS, ZDD, BDD, finite-state verification, LTSA
1	Smruti R. Sarangi, Brian Greskamp, Josep Torrellas	CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging.	DSN	2006	DBLP DOI BibTeX RDF
1	Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna	Post-reboot Equivalence and Compositional Verification of Hardware.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Jun Sawada, Erik Reeber	ACL2SIX: A Hint used to Integrate a Theorem Prover and an Automated Verification Tool.	FMCAD	2006	DBLP DOI BibTeX RDF
1	Lihua Yuan, Jianning Mai, Zhendong Su, Hao Chen, Chen-Nee Chuah, Prasant Mohapatra	FIREMAN: A Toolkit for FIREwall Modeling and ANalysis.	IEEE Symposium on Security and Privacy	2006	DBLP DOI BibTeX RDF
1	David W. Currie, Xiushan Feng, Masahiro Fujita, Alan J. Hu, Mark Kwan, Sreeranga P. Rajan	Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions.	International Journal of Parallel Programming	2006	DBLP DOI BibTeX RDF	Formal verification, DSP, embedded software, VLIW
1	Kathi Fisler	Toward diagrammability and efficiency in event-sequence languages.	STTT	2006	DBLP DOI BibTeX RDF	Weak automata, Timing diagrams, Property-specification languages
1	Kurt Jensen, Andreas Podelski	Tools and algorithms for the construction and analysis of systems.	STTT	2006	DBLP DOI BibTeX RDF	Error explanation, Model-checking, Verification, Program analysis, Tools, State spaces, Safety analysis
1	Carl-Johan H. Seger, Robert B. Jones, John W. O'Leary, Thomas F. Melham, Mark Aagaard, Clark Barrett, Don Syme	An industrially effective environment for formal hardware verification.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Yehuda Naveh, Roy Emek	Random Stimuli Generation for Functional Hardware Verification as a CP Application.	CP	2005	DBLP DOI BibTeX RDF
1	Grant Martin	Verification by the pound.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	complex ICs, verification methodologies, hardware verification languages, formal verification, functional verification, dynamic verification
1	Orna Grumberg, Tamir Heyman, Assaf Schuster	Distributed Symbolic Model Checking for µ-Calculus.	Formal Methods in System Design	2005	DBLP DOI BibTeX RDF	model checking, distributed, hardware verification, symbolic, Mu-calculus