Search results for "heterogeneous cores"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Houman Homayoun, Vasileios Kontorinis, Amirali Shayan, Ta-Wei Lin, Dean M. Tullsen	Dynamically heterogeneous cores through 3D resource pooling.	HPCA	2012	DBLP DOI BibTeX RDF
1	Debora Matos, Luigi Carro, Altamiro Amadeu Susin	Associating packets of heterogeneous cores using a synchronizer wrapper for NoCs.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Angela C. Sodan, Jacob Machina, Arash Deshmeh, Kevin Macnaughton, Bryan Esbaugh	Parallelism via Multithreaded and Multicore CPUs.	IEEE Computer	2010	DBLP DOI BibTeX RDF	Multithreaded cores, Heterogeneous cores, Application-level parallelism, Chip interconnects, GPUs, Multicore processors, Power efficiency
1	M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt	Accelerating Critical Section Execution with Asymmetric Multicore Architectures.	IEEE Micro	2010	DBLP DOI BibTeX RDF	heterogeneous cores, parallel programming, CMP, multicore, locks, critical sections, serialization
1	Nagarajan Venkateswaran, Ravindhiran Mukundrajan, Mrigank Sharma, Badrinarayanan Ravi	A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient.	ISVLSI	2009	DBLP DOI BibTeX RDF
1	M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt	Accelerating critical section execution with asymmetric multi-core architectures.	ASPLOS	2009	DBLP DOI BibTeX RDF	heterogeneous cores, parallel programming, cmp, multi-core, locks, critical sections
1	Antonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Peter D. Ungsunan, Chuang Lin, Yang Wang 0018, Yi Gai	Network processing performability evaluation on heterogeneous reliability multicore processors using SRN model.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Michael D. Linderman, Jamison D. Collins, Hong Wang 0003, Teresa H. Y. Meng	Merge: a programming model for heterogeneous multi-core systems.	ASPLOS	2008	DBLP DOI BibTeX RDF	GPGPU, predicate dispatch, heterogeneous multi-core
1	Ramesh Peri	Software development tools for multi-core/parallel programming.	PADTAD	2008	DBLP DOI BibTeX RDF
1	Allen C. Cheng	A Software-to-Hardware Self-Mapping Technique to Enhance Program Throughput for Portable Multimedia Workloads.	DELTA	2008	DBLP DOI BibTeX RDF	Instruction Fusion, Mobile Embedded SoC, Portable Multimedia, Energy Efficiency
1	Christian Hochberger, Alexander Weiss	A new methodology for debugging and validation of soft cores.	FPL	2008	DBLP DOI BibTeX RDF
1	Meilian Xu, Parimala Thulasiraman	Parallel Algorithm Design and Performance Evaluation of FDTD on 3 Different Architectures: Cluster, Homogeneous Multicore and Cell/B.E.	HPCC	2008	DBLP DOI BibTeX RDF
1	Christian Hochberger, Alexander Weiss	Acquiring an exhaustive, continuous and real-time trace from SoCs.	ICCD	2008	DBLP DOI BibTeX RDF
1	Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Tong Chen, Tao Zhang	Supporting OpenMP on Cell.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	OpenMP, Data transfer, Heterogeneous architecture, Thread synchronization
1	Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang 0003	EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system.	PLDI	2007	DBLP DOI BibTeX RDF	GPU, openMP, heterogeneous multi-cores
1	Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vetter	Balancing productivity and performance on the cell broadband engine.	CLUSTER	2007	DBLP DOI BibTeX RDF
1	Nan Wu 0003, Qianming Yang, Mei Wen, Yi He, Changqing Xun, Chunyuan Zhang	A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
1	Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Tong Chen, Tao Zhang	Supporting OpenMP on Cell.	IWOMP	2007	DBLP DOI BibTeX RDF
1	Michael Gschwind	The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor.	International Journal of Parallel Programming	2007	DBLP DOI BibTeX RDF	compute-transfer parallelism, multi-level application parallelism, Chip multiprocessor, Cell Broadband Engine, heterogeneous chip multiprocessor
1	Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen	IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Jaime H. Moreno	Chip-level integration: the new frontier for microprocessor architecture.	SPAA	2006	DBLP DOI BibTeX RDF	chip-level integration, microprocessor architecture
1	Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen	IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya	EuroSoC: towards a joint university/industry research infrastructure for system on chip and system in package.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu	Diagonal Test and Diagnostic Schemes for Flash Memorie.	ITC	2002	DBLP DOI BibTeX RDF	built-in self-diagnosis (BISD), memory diagnosis, built-in self-test (BIST), flash memory, memory testing, system-on-chip (SOC)
1	Bart Vermeulen, Tom Waayers, Sjaak Bakker	EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips.	ITC	2002	DBLP DOI BibTeX RDF
1	Ramesh V. Peri, Srinivas Doddapaneni	Compilers and Tools for Embedded Systems - Introduction. (PDF / PS)	HICSS	2000	DBLP DOI BibTeX RDF