Search results for "high level synthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Xiaowei Li, Toshimitsu Masuzawa, Hideo Fujiwara	Strong self-testability for data paths high-level synthesis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	self-testability, testability constraints, interconnection assignment, test resources reusability, high level synthesis, high-level synthesis, design for testability, register transfer level, data flow graphs, data paths, register assignment
4	Min Xu, Fadi J. Kurdahi	Layout-Driven RTL Binding Techniques for High-Level Synthesis. (PDF / PS)	ISSS	1996	DBLP DOI BibTeX RDF	layout-driven register-transfer-level, binding techniques, chip level implementation, high level synthesis, high-level synthesis, design process
4	Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer	Arithmetic built-in self test for high-level synthesis.	VTS	1995	DBLP DOI BibTeX RDF	arithmetic built-in self test, data path architectures, arithmetic blocks, compact test responses, testable circuit synthesis, logic testing, built-in self test, high level synthesis, high-level synthesis, integrated circuit testing, logic CAD, testability, abstract level, test vectors, state coverage
4	Preeti Ranjan Panda, Nikil D. Dutt	1995 high level synthesis design repository.	ISSS	1995	DBLP DOI BibTeX RDF	1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units
3	Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong	Bit-level optimization for high-level synthesis and FPGA-based acceleration.	FPGA	2010	DBLP DOI BibTeX RDF	bit-level optimization, fpga, high-level synthesis
3	Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin	Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Prototyping, Refinement, High-level synthesis, Design space exploration, System level design
3	Insup Shin, Seungwhun Paik, Youngsoo Shin	Register allocation for high-level synthesis using dual supply voltages.	DAC	2009	DBLP DOI BibTeX RDF	low power, high-level synthesis, register allocation, dual supply voltage
3	Fei Su, Krishnendu Chakrabarty	High-level synthesis of digital microfluidic biochips.	JETC	2008	DBLP DOI BibTeX RDF	scheduling, system-on-chip, High-level synthesis, microfluidics, biochips
3	Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade	Hand-in-hand verification of high-level synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FSMD model, formal verification, high-level synthesis, equivalence checking
3	Junhyung Um, Taewhan Kim	Resource Sharing Combined with Layout Effects in High-Level Synthesis.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	resource allocation, high-level synthesis, layout
3	Soumya Pandit, Chittaranjan A. Mandal, Amit Patra	A formal approach for high level synthesis of linear analog systems.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	L2 sensitivity, analog high level synthesis, linear systems, architecture exploration, state space model
3	Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh	A scheduling algorithm for optimization and early planning in high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Scheduling, high-level synthesis, data flow graph, bipartite matching
3	Rehab F. Abdel-Kader	Resource-constrained loop scheduling in high-level synthesis.	ACM Southeast Regional Conference	2005	DBLP DOI BibTeX RDF	scheduling, high-level synthesis, force-directed scheduling
3	Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee	Leakage power optimization with dual-Vth library in high-level synthesis.	DAC	2005	DBLP DOI BibTeX RDF	dual-Vth, optimization, high-level synthesis, leakage power
3	Hsueh-Chih Yang, Lan-Rong Dung	On multiple-voltage high-level synthesis using algorithmic transformations.	ASP-DAC	2005	DBLP DOI BibTeX RDF	loop shrinking, multiple voltage scheduling, high-level synthesis, retiming, unfolding, low power circuit
3	Sumit Gupta, Rajesh K. Gupta, Nikil D. Dutt, Alexandru Nicolau	Coordinated parallelizing compiler optimizations and high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	dynamic CSE, parallelizing transformations, presynthesis, embedded systems, high-level synthesis, Code motions, common subexpression elimination
3	Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha	A comprehensive high-level synthesis system for control-flow intensive behaviors.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	control-flow intensive behaviors, high-level synthesis, low power design
3	Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy	An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	lifecycle analysis, register optimization, high-level synthesis, hardware description languages, Behavioral synthesis, hierarchical specifications
3	Apostolos A. Kountouris, Christophe Wolinski	Efficient scheduling of conditional behaviors for high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	conditional behavior, scheduling, high level synthesis (HLS), Design automation
3	Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem	Coordinated transformations for high-level synthesis of high performance microprocessor blocks.	DAC	2002	DBLP DOI BibTeX RDF	high-level synthesis, microprocessor design
3	María C. Molina, José M. Mendías, Román Hermida	High-level synthesis of multiple-precision circuitsindependent of data-objects length.	DAC	2002	DBLP DOI BibTeX RDF	scheduling, high-level synthesis, allocation, multiple-precision
3	Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn	Controller Estimation for FPGA Target Architectures during High-Level Synthesis.	ISSS	2002	DBLP DOI BibTeX RDF	FPGA, controller, high-level synthesis, area estimation
3	Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta	Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis.	ISSS	2002	DBLP DOI BibTeX RDF	common sub-expression elimination, dynamic CSE, parallelizing transformations, high-level synthesis
3	Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac	High-Level Synthesis with SIMD Units.	VLSI Design	2002	DBLP DOI BibTeX RDF	SIMD functional units, High-level synthesis, high performance design
3	J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir	A Heuristic for Clock Selection in High-Level Synthesis.	VLSI Design	2002	DBLP DOI BibTeX RDF	clock selection, heuristics, high-level synthesis, design space exploration, graph structure
3	Andrew Stone, Elias S. Manolakos	Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis.	ASAP	2000	DBLP DOI BibTeX RDF	Optimal VHDL, DG2VHDL, Hierarchical CDFG, High Level Synthesis, Dependence Graph, Signal Flow Graph, Design Complexity
3	Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana	High-Level Synthesis with Variable-Latency Components.	VLSI Design	2000	DBLP DOI BibTeX RDF	variable latency units, data dependent computation, area-delay tradeoffs, High-level synthesis, performance optimization
3	Giri Tiruvuri, Moon Chung	Estimation of lower bounds in scheduling algorithms for high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	lower-bound estimated, scheduling, dynamic programming, high-level synthesis
3	Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer	Estimation of BIST Resources During High-Level Synthesis.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	built-in self-test, high-level synthesis, estimation
3	Pradeep Prabhakaran, Prithviraj Banerjee	Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis.	VLSI Design	1998	DBLP DOI BibTeX RDF	timing driven synthesis, High-level synthesis, floorplanning
3	José M. Mendías, Román Hermida	Correct High-Level Synthesis: a Formal Perspective.	DATE	1998	DBLP DOI BibTeX RDF	automatic formal synthesis, formal verification, high-level synthesis, streams
3	Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha	IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits.	DATE	1998	DBLP DOI BibTeX RDF	multiplexer re-structuring, low power, high-level synthesis, resource sharing, control-flow, module selection
3	Oliver Bringmann, Wolfgang Rosenstiel	Cross-Level Hierarchical High-Level Synthesis.	DATE	1998	DBLP DOI BibTeX RDF	Hierarchical Synthesis, Complex Components, High-Level Synthesis
3	Jie Gong, Chih-Tung Chen, Kayhan Küçükçakar	Architectural Rule Checking for High-level Synthesis.	DATE	1998	DBLP DOI BibTeX RDF	Rule Checking, Verification, High-level Synthesis
3	Anna Antola, Vincenzo Piuri, Mariagiovanna Sami	High-level Synthesis of Data Paths with Concurrent Error Detection. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	self-checking systems, high-level synthesis, concurrent error detection, data path
3	Youn-Long Lin	Recent developments in high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	high level synthesis, design methodology, VLSI design, design automation
3	Min Xu, Fadi J. Kurdahi	Layout-driven RTL binding techniques for high-level synthesis using accurate estimators.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	FPGAs, high-level synthesis, floorplan, binding
3	Wayne Wolf	Redundancy Removal during High-Level Synthesis Using Scheduling Don't-Cares.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	scheduling dont-care, high-level synthesis, redundancy
3	Giacomo Buonanno, M. Pugassi, Mariagiovanna Sami	A high-level synthesis approach to design of fault-tolerant systems.	VTS	1997	DBLP DOI BibTeX RDF	hardware-software system, design, embedded system, fault tolerant computing, high-level synthesis, reconfiguration, scheduling algorithm, cost, processor, fault-tolerant system
3	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Exploiting off-chip memory access modes in high-level synthesis.	ICCAD	1997	DBLP DOI BibTeX RDF	High Level Synthesis, DRAM, Memory Synthesis
3	Salil Raje, Reinaldo A. Bergamaschi	Generalized resource sharing.	ICCAD	1997	DBLP DOI BibTeX RDF	clique-partitioning-based algorithms, generalized resource sharing, global clique partitioning based framework, interconnect cost estimation, merging cost estimation, sharing possibilities, high level synthesis, high-level synthesis, functional unit, functional units
3	Minjoong Rim, Rajiv Jain	Valid Transformations: A New Class of Loop Transformations for High-Level Synthesis and Pipelined Scheduling Applications.	IEEE Trans. Parallel Distrib. Syst.	1996	DBLP DOI BibTeX RDF	super-scalar, loop compilation, High-level synthesis, VLIW, loop transformations, loop optimization, pipeline scheduling
3	Peter Grün, Petru Eles, Krzysztof Kuchcinski, Zebo Peng	Automatic Parallelization of a Petri Net-Based Design Representation for High-Level Synthesis.	EUROMICRO	1996	DBLP DOI BibTeX RDF	Petri net-based design representation, internal design representation, hardware structures, conflict freeness, hierarchical Petri net structure, CAMAD, complexity, parallelization process, Petri nets, high-level synthesis, automatic parallelization, design environment, safeness
3	Yung-Ming Fang, D. F. Wong	Multiplexor Network Generation in High Level Synthesis. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	High Level Synthesis
3	Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki	A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	high-level synthesis for testability, systematic flexible synthesis, testability methodology, industrial tools, pragmatic synthesis, AMICAL synthesis, programmable test pattern generation, BUS-based circuit, embedded test paths, high level synthesis, design for testability, BIST, automatic generation, data path, scan path
3	Hans-Georg Martin	Retiming for Circuits with Enable Registers.	EUROMICRO	1996	DBLP DOI BibTeX RDF	enable registers, circuit retiming, combinational paths, D-Flipflops, retiming algorithm, sequential elements, high level synthesis, high level synthesis, digital circuits
3	Alex Orailoglu	Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	microarchitectural synthesis, dynamically reconfigurable ASICs, fault-tolerance scheme, band reconfiguration, multiple permanent faults, associated high-level synthesis procedure, hardware rebinding, high-level synthesis, application specific integrated circuits, graceful degradation
3	Alan Su 0002, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee	Eliminating False Loops Caused by Sharing in Control Path. (PDF / PS)	ISSS	1996	DBLP DOI BibTeX RDF	false loops, control path sharing, timing validation, design sign-off phase, data path sharing, control logic sharing, removal algorithm, computation complexity, high level synthesis, high level synthesis, filter, resource sharing, logic minimization
3	Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen	A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts.	VLSI Design	1996	DBLP DOI BibTeX RDF	Application specific High-Level Synthesis, High-Level Synthesis for telecommunication, ATM
3	Seong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min Xu	A comprehensive estimation technique for high-level synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area
3	Santonu Sarkar, Anupam Basu, Arun K. Majumdar	Synchronization of communicating modules and processes in high level synthesis.	VLSI Design	1995	DBLP DOI BibTeX RDF	communicating modules, object oriented design framework, nonblocking channel, real life image processing, synchronization, high level synthesis, high level synthesis, application specific integrated circuits, synchronisation, object-oriented methods, component reuse, ASIC designs, image processing equipment
3	Balakrishnan Iyer, Ramesh Karri, Israel Koren	Phantom redundancy: a high-level synthesis approach for manufacturability.	ICCAD	1995	DBLP DOI BibTeX RDF	fabrication-time reconfigurability, functional unit failure, microarchitecture synthesis, phantom redundancy, genetic algorithm, high level synthesis, high-level synthesis, redundancy, logic design, reconfigurable architectures, manufacturability, microarchitecture, circuit CAD
3	Enric Musoll, Jordi Cortadella	Scheduling and resource binding for low power.	ISSS	1995	DBLP DOI BibTeX RDF	data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding
3	Ireneusz Karkowski	Architectural synthesis with possibilistic programming.	HICSS	1995	DBLP DOI BibTeX RDF	possibilistic programming, fuzzy mathematical programming, simultaneous scheduling, FOAS, computational complexity, computational complexity, fuzzy logic, high level synthesis, high-level synthesis, circuit CAD, mathematical programming, possibility theory
3	Jay K. Adams, John Alan Miller, Donald E. Thomas	Execution-time profiling for multiple-process behavioral synthesis. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model
3	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
3	Miodrag Potkonjak, Anantha Chandrakasan	Synthesis and selection of DCT algorithms using behavioral synthesis-based algorithm space exploration. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	DCT algorithms, behavioral synthesis-based algorithm space exploration, high level synthesis tools, behavioral design space, IC implementation, image processing, image processing, high level synthesis, discrete cosine transforms, discrete cosine transform, application specific integrated circuits, circuit layout CAD, video processing, fast algorithms, video signal processing, digital signal processing chips, design space
3	Ahmad Abualsamid, Raed Alqadi, Parameswaran Ramanathan	Distributed synthesis of real-time computer systems. (PDF / PS)	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	engineering workstations, distributed synthesis, design library, processor estimation, application constraints, suitable architecture identification, application task scheduling, runtime speedup, scheduling, real-time systems, computational complexity, parallelization, CAD, distributed processing, high level synthesis, high-level synthesis, software libraries, workstation network, real-time computer systems, resource estimation, component library
3	Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja	Incorporating testability considerations in high-level synthesis.	J. Electronic Testing	1994	DBLP DOI BibTeX RDF	Automatic synthesis of testable designs, loop breaking, high-level synthesis, binding, synthesis for testability
3	Mikael R. K. Patel	A design representation for high level synthesis.	EURO-DAC	1990	DBLP DOI BibTeX RDF	Data Structures, High Level Synthesis, Design Automation, Design Representation
2	Toshinobu Matsuba, Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada	Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis.	DELTA	2010	DBLP DOI BibTeX RDF	static single assignment transformation, high-level synthesis, multiplexer
2	Sumit Ahuja, Wei Zhang, Avinash Lakshminarayana, Sandeep K. Shukla	A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms.	VLSI Design	2010	DBLP DOI BibTeX RDF	C2R, Hardware Coprocessor, Software Algorithms, High Level Synthesis, Clock-gating, Power Reduction
2	Peter Lisherness, Kwang-Ting (Tim) Cheng	SCEMIT: a systemc error and mutation injection tool.	DAC	2010	DBLP DOI BibTeX RDF	high-level synthesis, coverage, SystemC, mutation
2	Jirí Simsa, Satnam Singh	Designing hardware with dynamic memory abstraction.	FPGA	2010	DBLP DOI BibTeX RDF	c to gates, high-level synthesis, parallel execution, dynamic memory, bluespec
2	Eunjoo Choi, Changsik Shin, Youngsoo Shin	ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
2	Sumit Ahuja, Deepak Mathaikutty, Gaurav Singh, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar	Power estimation methodology for a high-level synthesis framework.	ISQED	2009	DBLP DOI BibTeX RDF
2	Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee	A software pipelining algorithm in high-level synthesis for FPGA architectures.	ISQED	2009	DBLP DOI BibTeX RDF
2	Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo	Handling don't-care conditions in high-level synthesis and application for reducing initialized registers.	DAC	2009	DBLP DOI BibTeX RDF	RTL symbolic simulation, don't-care (DC), synthesis
2	Yibo Chen, Yuan Xie	Tolerating process variations in high-level synthesis using transparent latches.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Shih-Hsu Huang, Chun-Hua Cheng	Timing driven power gating in high-level synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol Mathur, Nikhil Sharma	Non-cycle-accurate sequential equivalence checking.	DAC	2009	DBLP DOI BibTeX RDF	unit product machine, model checking, formal verification, high level synthesis, sequential equivalence checking
2	Scott Cromar, Jaeho Lee, Deming Chen	FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation.	DAC	2009	DBLP DOI BibTeX RDF	glitch power, FPGA, high-level synthesis, power reduction
2	O. Sarbishei, Bijan Alizadeh, Masahiro Fujita	Polynomial datapath optimization using partitioning and compensation heuristics.	DAC	2009	DBLP DOI BibTeX RDF	modular HED, polynomial datapath, high-level synthesis
2	Taemin Kim, Xun Liu	Better than optimum?: register reduction using idle pipelined functional units.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	high level synthesis, register binding
2	Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu	High-performance CUDA kernel execution on FPGAs.	ICS	2009	DBLP DOI BibTeX RDF	cuda programming model, fpga, high level synthesis, high performance computing, gpu, coarse grained parallelism
2	Levent Aksoy, Diego Jaccottet, Eduardo Costa	Design of low complexity digital FIR filters.	SBCCI	2009	DBLP DOI BibTeX RDF	low-level synthesis, multiple constant multiplications, multiplierless filter design, high-level synthesis, array multipliers
2	Meikang Qiu, Edwin Hsing-Mean Sha	Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Embedded Systems, real-time, high-level synthesis, heterogeneous
2	Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar	An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet	Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Grant Martin	The two faces of high-level synthesis [review of High-Level Synthesis: From Algorithm to Digital Circuit (Coussy, P. and Morawiec, A., Eds., 2008)].	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF
2	Hariharan Sankaran, Srinivas Katkoori	Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis.	DELTA	2008	DBLP DOI BibTeX RDF	Simulated Annealing, HLS, Encoding, Crosstalk, Binding, Reordering
2	Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida	Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis.	DSD	2008	DBLP DOI BibTeX RDF
2	George Economakos, Sotirios Xydis	A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis.	DSD	2008	DBLP DOI BibTeX RDF
2	Pedro Garcia-Repetto, María C. Molina, Rafael Ruiz-Sautua, Guillermo Botella Juan	Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits.	DSD	2008	DBLP DOI BibTeX RDF
2	Vyas Krishnan, Srinivas Katkoori	Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Feng Wang 0004, Guangyu Sun, Yuan Xie	A Variation Aware High Level Synthesis Framework.	DATE	2008	DBLP DOI BibTeX RDF
2	Saeed Safari	Co-evolutionary reliability-oriented high-level synthesis.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii	CHStone: A benchmark program suite for practical C-based high-level synthesis.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Sudipta Kundu, Sorin Lerner, Rajesh Gupta	Validating High-Level Synthesis.	CAV	2008	DBLP DOI BibTeX RDF
2	Christoforos E. Economakos, George Economakos	Optimized FPGA implementations of demanding PLC programs based on hardware high-level synthesis.	ETFA	2008	DBLP DOI BibTeX RDF
2	Arash Ahmadi, Mark Zwolinski	Symbolic noise analysis approach to computational hardware optimization.	DAC	2008	DBLP DOI BibTeX RDF	word-length optimization, high level synthesis, computer arithmetic, computational error
2	Pascal Urard, Asma Maalej, Roberto Guizzetti, Nitin Chawla	Leveraging sequential equivalence checking to enable system-level to RTL flows.	DAC	2008	DBLP DOI BibTeX RDF	formal verification, high-level synthesis, equivalence checking, system-level models, RTL models
2	Youngsik Kim, Nazanin Mansouri	Automated formal verification of scheduling with speculative code motions.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	formal verification, high level synthesis, automated theorem-proving, speculation
2	Rosilde Corvino, Stéphane Mancini, Roberto Guizzetti	Automatic generation of a parallel tile processing unit for algorithms with non-affine array references.	IFMT	2008	DBLP DOI BibTeX RDF	computations scheduling, design space exploration (DSE), non-affine array references, super-tiling, mapping, high-level synthesis (HLS), tiling
2	Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou	Unified Incremental Physical-Level and High-Level Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Chen He, Margarida F. Jacome	Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Vyas Krishnan, Srinivas Katkoori	A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
2	David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee	Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs.	ISQED	2007	DBLP DOI BibTeX RDF
2	Zhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai	Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan.	ISVLSI	2007	DBLP DOI BibTeX RDF