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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6097 occurrences of 2986 keywords
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Results
Found 9042 publication records. Showing 9042 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 5 | Pi-Rong Sheu, Charng-Maw Lin |
A fast optimal slot reuse scheme for CRMA high speed networks. (PDF / PS)  |
LCN  |
1997 |
DBLP DOI BibTeX RDF |
CRMA high speed networks, cyclic-reservation multiple-access, fast optimal slot reuse scheme, high-speed local area networks, high-speed metropolitan area networks, folded-bus configurations, dual-bus configurations, reserve command generation, empty slots reservation, average cycle length, average throughput, average MAC delay, performance measurements, time complexity, computer simulations, NP-complete problem, metropolitan area networks, access delay |
| 4 | James P. G. Sterbenz |
Protocols for High-Speed Networks: A Brief Retrospective Survey of High-Speed Networking Research.  |
Protocols for High-Speed Networks  |
2002 |
DBLP DOI BibTeX RDF |
|
| 4 | Karl J. Schrodi |
High Speed Networks for Carriers.  |
Protocols for High-Speed Networks  |
2002 |
DBLP DOI BibTeX RDF |
|
| 4 | James P. G. Sterbenz |
High-Speed Mobile and Wireless Networks.  |
Protocols for High-Speed Networks  |
2002 |
DBLP DOI BibTeX RDF |
|
| 4 | Luigi Alfredo Grieco, Saverio Mascolo |
TCP Westwood and Easy RED to Improve Fairness in High-Speed Networks.  |
Protocols for High-Speed Networks  |
2002 |
DBLP DOI BibTeX RDF |
|
| 4 | Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu |
High-speed generation of LFSR signatures.  |
Asian Test Symposium  |
2000 |
DBLP DOI BibTeX RDF |
high-speed generation, LFSR signatures, compaction simulation, single-input signature register, equivalent multiple-input implementation, finite field theory, high-speed signature computations, lookahead technique, internal-XOR LFSR, external-XOR LFSR, performance evaluation, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, BIST, linear feedback shift register, binary sequences, subsequences |
| 4 | Jong-Arm Jun, Hyuncheol Kim, Kyou-Ho Lee |
High-Speed IP Forwarding Mechanism for an MPOA-Based Switched Router. (PDF / PS)  |
LCN  |
2000 |
DBLP DOI BibTeX RDF |
frame relay, high-speed IP forwarding mechanism, MPOA-based switched router, high speed router, multiprotocol over ATM, SR-10 system, frame relay, layer-3 transport capability, 10 Gbit/s, Internet, asynchronous transfer mode, local area networks, transport protocols, Ethernet, telecommunication network routing, telecommunication traffic, ATM switching, Internet traffic |
| 4 | Ridha Djemal, Guy Mazaré, Gérard Michel |
Toward reconfigurable associative architecture for high speed communication operators.  |
ECBS  |
1996 |
DBLP DOI BibTeX RDF |
reconfigurable associative architecture, high speed communication operators, associative organization, complex data structures, structured addressable associative memory, high speed communication protocols, CAM architectures, SYMOPSYS tool, architecture validation, FPGA, real-time systems, real-time, asynchronous transfer mode, asynchronous transfer mode, local area networks, local area network, reconfigurable architectures, memory architecture, LAN, content-addressable storage |
| 4 | Prasasth Palnati, Mario Gerla, Emilio Leonardi |
Deadlock-free routing in an optical interconnect for high-speed wormhole routing networks. (PDF / PS)  |
ICPADS  |
1996 |
DBLP DOI BibTeX RDF |
high-speed wormhole routing networks, Supercomputer SuperNet, two-level hierarchical high-speed network, electronic mesh fabric, WDM optical backbone network, metropolitan area, campus area, backpressure hop-by-hop flow control mechanism, shufflenet multihop virtual topology, physical channels, up/down deadlock free routing scheme, bidirectional shufflenet, optical backbone, multiprocessor interconnection networks, network routing, virtual channels, wavelength division multiplexing, optical interconnections, optical interconnect, deadlock-free routing, deadlock prevention |
| 4 | David W. Pritty, Duncan N. Smeed, Norman L. Lawrie |
A new class of high speed LAN access protocols based on the principle of timed packet release. (PDF / PS)  |
LCN  |
1995 |
DBLP DOI BibTeX RDF |
timed packet release, high speed local area network, bus structures, TPR, performance evaluation, performance, discrete event simulation, discrete event simulation, local area networks, access protocols, access protocols, comparative evaluation, high speed LAN |
| 4 | Shoujue Wang, Xunwei Wu, Hongjuan Feng |
The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors. (PDF / PS)  |
ISMVL  |
1995 |
DBLP DOI BibTeX RDF |
high speed ternary logic gates, multiple /spl beta/ transistors, multiple emitter transistor, current gain, linear AND/OR gates, multi valued literal circuits, high speed multi valued logic circuits, multivalued logic circuits, logic gates, ternary logic, transistors |
| 4 | S. Y. Kulkarni, K. D. Patil, K. V. V. Murthy |
Transmission line model parameters for very high speed VLSI interconnects in MCMs using FEM with special elements.  |
VLSI Design  |
1995 |
DBLP DOI BibTeX RDF |
very high speed integrated circuits, transmission line theory, integrated circuit packaging, transmission line model parameters, very high speed VLSI interconnects, higher order isoparametric elements, 2D interconnect/dielectric packaging structures, quadrilateral infinite elements, signal conductor boundaries, sharp corners, finite element method, finite element analysis, computation time, multichip modules, multichip modules, FEM, MCM, integrated circuit interconnections, VLSI interconnects |
| 4 | Akihiro Tsutsui, Toshiaki Miyazaki, Kazuhisa Yamada, Naohisa Ohta |
Special purpose FPGA for high-speed digital telecommunication systems. (PDF / PS)  |
ICCD  |
1995 |
DBLP DOI BibTeX RDF |
special purpose FPGA, high-speed digital telecommunication systems, high-speed transport data processing, inter-chip connection mechanism, dedicated CAD system, field programmable gate arrays, field programmable gate array, programmable logic arrays, digital communication |
| 4 | Fukiko Hidano |
Signalling on ATM testbeds: an example. (PDF / PS)  |
IEEE Real Time Technology and Applications Symposium  |
1995 |
DBLP DOI BibTeX RDF |
telecommunication signalling, telecommunication equipment testing, high-speed links, high-speed switches, ATM testbeds, XUNET testbed, vic, real-time systems, multimedia, protocols, asynchronous transfer mode, multimedia communication, real-time applications, high-speed networking, videoconferencing, signalling, teleconferencing, quality of service guarantees, ISDN, ISDN, virtual circuits, signalling protocols |
| 3 | Ruisi He, Zhangdui Zhong, Bo Ai |
Path loss measurements and analysis for high-speed railway viaduct scene.  |
IWCMC  |
2010 |
DBLP DOI BibTeX RDF |
high-speed railway, path loss exponent, path loss measurement, shadow fading, viaduct |
| 3 | Lorenzo De Carli, Yi Pan, Amit Kumar, Cristian Estan, Karthikeyan Sankaralingam |
PLUG: flexible lookup modules for rapid deployment of new protocols in high-speed routers.  |
SIGCOMM  |
2009 |
DBLP DOI BibTeX RDF |
high-speed routers, flexibility, dataflow, forwarding, lookup, tiled architectures |
| 3 | Yongheng Guo, Wei Cai, Tiejun Lu, Zongmin Wang |
A Novel 1GSPS Low Offset Comparator for High Speed ADC.  |
NCM  |
2009 |
DBLP DOI BibTeX RDF |
high speed ADC, high speed comparator, preamplifier latch comparator, low offset comparator |
| 3 | Charbel J. Akl, Magdy A. Bayoumi |
Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family.  |
ISQED  |
2008 |
DBLP DOI BibTeX RDF |
circuit family, low-power, high-speed |
| 3 | Levent Aksoy, Ece Olcay Günes |
Area optimization algorithms in high-speed digital FIR filter synthesis.  |
SBCCI  |
2008 |
DBLP DOI BibTeX RDF |
high-speed filter design, multiple constant multiplications, subexpression sharing, area optimization, carry-save adders |
| 3 | Kuei-Hsiang Chao |
Extension Robust Control of a Three-Level Converter for High-Speed Railway Tractions.  |
ISNN  |
2008 |
DBLP DOI BibTeX RDF |
Three-level converter, power factor correction, extension robust controller, high-speed railway tractions |
| 3 | Charbel J. Akl, Magdy A. Bayoumi |
Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count.  |
ACM Great Lakes Symposium on VLSI  |
2008 |
DBLP DOI BibTeX RDF |
high-speed signaling, repeater, wires |
| 3 | Romaric Guillier, Pascale Vicat-Blanc Primet |
Methodologies and Tools for Exploring Transport Protocols in the Context of High-Speed Networks.  |
CCGRID  |
2008 |
DBLP DOI BibTeX RDF |
Transport Protocol Evaluation, Methodologies, Tools, High Speed Networks |
| 3 | Junfeng Hu, Xianmin Zhang, Jinqing Zhan |
Trajectory Planning of a Novel 2-DoF High-Speed Planar Parallel Manipulator.  |
ICIRA  |
2008 |
DBLP DOI BibTeX RDF |
time optimum, trajectory planning, high speed, parallel manipulator |
| 3 | Yubo Liu, Can Zhao, Jinping Hu, Mingjun Feng |
Research on Cutting Parameters Optimization of High-Speed Milling Based on Orthogonal Experiment.  |
ICIRA  |
2008 |
DBLP DOI BibTeX RDF |
high-speed milling, aluminum alloy, cutting parameters, surface roughness |
| 3 | Qingqi Dou, Jacob A. Abraham |
Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems.  |
VTS  |
2008 |
DBLP DOI BibTeX RDF |
Time-Interleaved ADC, Timing Mismatch, Mixed-signal testing, Low-cost test, High speed testing |
| 3 | Tadashi Ikeuchi, Tszshing Cheung, Hiroshi Onaka |
The Latest Trend of Low Power High-Speed CMOS I/O Technology for Photonic Network.  |
SAINT  |
2008 |
DBLP DOI BibTeX RDF |
High-speed input/output interfaces, low power, CMOS |
| 3 | Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura |
A Secure High-Speed Identification Scheme for RFID Using Bloom Filters.  |
ARES  |
2008 |
DBLP DOI BibTeX RDF |
Hash-chain scheme, High-speed identification, Bloom pre-computation scheme, RFID, Bloom filter |
| 3 | Ben Lu, Xiaodong Wang, Mohammad Madihian |
Physical-layer air interface solutions for broadband high-speed wireless cellular systems.  |
Wireless Networks  |
2007 |
DBLP DOI BibTeX RDF |
Air interface, Multi-carrier(MC), OFDM, CDMA, MIMO, Broadband, High-speed, LDPC, Physical layer, Downlink, Uplink, High data rate, Wide-band |
| 3 | Hyun-Wook Jin, Chuck Yoo |
Impact of protocol overheads on network throughput over high-speed interconnects: measurement, analysis, and improvement.  |
The Journal of Supercomputing  |
2007 |
DBLP DOI BibTeX RDF |
Programmable Network interface cards, Clusters, Myrinet, High-speed interconnects, UDP/IP |
| 3 | Cato Alexander Bjørkli, Kjell Ivar Øvergård, Bjarte Knappen Røed, Thomas Hoff |
Control situations in high-speed craft operation.  |
Cognition, Technology & Work  |
2007 |
DBLP DOI BibTeX RDF |
Control situations, Human-technology systems, High-speed crafts, Maneuvering, Navigation, Dynamic adaptation |
| 3 | Nidal Nasser, Tarek Bejaoui |
User satisfaction based scheduling algorithm for high-speed wireless networks.  |
IWCMC  |
2007 |
DBLP DOI BibTeX RDF |
high speed downlink packet access, non-real time services, packet QoS provisioning, priority packet scheduling |
| 3 | Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert Cauwenberghs |
High-speed, model-free adaptive control using parallel synchronous detection.  |
SBCCI  |
2007 |
DBLP DOI BibTeX RDF |
VLSI optimization, high-speed control, model-free, multi-dithering, synchronous detection, translinear circuits, adaptive control |
| 3 | Cary Gunn |
CMOS Photonics for High-Speed Interconnects.  |
IEEE Micro  |
2006 |
DBLP DOI BibTeX RDF |
CMOS photonics, high-speed optical communications, Luxtera, 10-Gbps |
| 3 | Muhammet Mustafa Ozdal, Martin D. F. Wong |
Two-layer bus routing for high-speed printed circuit boards.  |
ACM Trans. Design Autom. Electr. Syst.  |
2006 |
DBLP DOI BibTeX RDF |
min-max length constraints, High-speed, bus routing, PCB |
| 3 | Elisabeth Brunet, Olivier Aumage, Raymond Namyst |
Short Paper : Dynamic Optimization of Communications over High Speed Networks.  |
HPDC  |
2006 |
DBLP DOI BibTeX RDF |
network cards, communication subsystem, packet optimization engine, network drivers, high speed network |
| 3 | Hung Tien Bui, Yvon Savaria |
High speed differential pulse-width control loop based on frequency-to-voltage converters.  |
ACM Great Lakes Symposium on VLSI  |
2006 |
DBLP DOI BibTeX RDF |
PWCL, frequency-to-voltage, high-speed, duty cycle |
| 3 | Xiaoyang Wang, Limin Li |
Study on Application of High Speed Milling in Dies Manufacturing for Plate Heat Exchangers.  |
PROLAMAT  |
2006 |
DBLP DOI BibTeX RDF |
High Speed Milling, HSM strategy, Dies for Plate Heat Exchangers, Technics |
| 3 | Michele C. Weigle, Pankaj Sharma, Jesse R. Freeman IV |
Performance of Competing High-Speed TCP Flows.  |
Networking  |
2006 |
DBLP DOI BibTeX RDF |
High-speed TCP, performance evaluation, congestion control, network simulation |
| 3 | Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei |
A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices.  |
J. Electronic Testing  |
2005 |
DBLP DOI BibTeX RDF |
timing specifications testing, test environment, tester OTA and yield, high-speed interconnect testing, yield analysis |
| 3 | Mariano Aguirre, Monico Linares |
An alternative logic approach to implement high-speed low-power full adder cells.  |
SBCCI  |
2005 |
DBLP DOI BibTeX RDF |
low-power, high-speed, full adder |
| 3 | Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije |
A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer.  |
SBCCI  |
2005 |
DBLP DOI BibTeX RDF |
high speed digital circuit, low power, prescaler, frequency synthesizer |
| 3 | Rodolfo E. Haber, José R. Alique, Salvador Ros, Rodolfo Haber-Haber |
Modeling and Simulation of High-Speed Machining Processes Based on Matlab/Simulink.  |
International Conference on Computational Science  |
2005 |
DBLP DOI BibTeX RDF |
high-speed machining, modeling, complex systems |
| 3 | Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi |
A high speed and leakage-tolerant domino logic for high fan-in gates.  |
ACM Great Lakes Symposium on VLSI  |
2005 |
DBLP DOI BibTeX RDF |
high speed, noise immunity, deep submicron, fan-in, domino |
| 3 | Rodolfo Haber-Guerra, Rodolfo Haber-Haber, José R. Alique |
Controlling Force Based on Radial Fuzzy Functions in High-Speed Machining Processes.  |
IWANN  |
2005 |
DBLP DOI BibTeX RDF |
Radial Fuzzy Functions, high-speed machining processes, Fuzzy control |
| 3 | Christian Theobalt, Irene Albrecht, Jörg Haber, Marcus A. Magnor, Hans-Peter Seidel |
Pitching a baseball: tracking high-speed motion with multi-exposure images.  |
ACM Trans. Graph.  |
2004 |
DBLP DOI BibTeX RDF |
high-speed motion capture, multi-exposure images, physically based validation, pitching and flight of baseball |
| 3 | Jan Coppens, Stijn De Smet, Steven Van den Berghe, Filip De Turck, Piet Demeester |
Performance Evaluation of a Probabilistic Packet Filter Optimization Algorithm for High-Speed Network Monitoring.  |
HSNMC  |
2004 |
DBLP DOI BibTeX RDF |
|
| 3 | Robert McGorman, Jalal Almhana, Vartan Choulakian, Zikuan Liu, W. Jedidi |
Similarities between Voice and High Speed Internet Traffic Provisioning.  |
CNSR  |
2004 |
DBLP DOI BibTeX RDF |
high speed internet traffic, voice over packet, peak load models, self-similarity, capacity planning, Hurst parameter, goodness-of-fit tests |
| 3 | Hesam Amir Aslanzadeh, Saeid Mehrmanesh, Mohammad B. Vahidfar, Amin Quasem Safarian, Reza Lotfi |
A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique.  |
ISLPED  |
2003 |
DBLP DOI BibTeX RDF |
CMOS analog circuit, Slew Boost technique, class AB, low power, high speed, operational amplifier, pipelined analog to digital converter, ultra low voltage |
| 3 | Woo Young Choi, Jong Duk Lee, Byung-Gook Park |
Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers.  |
ISLPED  |
2003 |
DBLP DOI BibTeX RDF |
RODOS, offset spacer, reverse-order, low-power, high-speed, low-noise, amplifier |
| 3 | Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov |
Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing.  |
Asian Test Symposium  |
2003 |
DBLP DOI BibTeX RDF |
Timing specifications testing, Test Environment, Tester OTA and yield, High-speed interconnect testing, Yield analysis |
| 3 | Payam Heydari |
Design issues in low-voltage high-speed current-mode logic buffers.  |
ACM Great Lakes Symposium on VLSI  |
2003 |
DBLP DOI BibTeX RDF |
VLSI, noise, integrated circuit, high-speed, current-mode logic |
| 3 | Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi |
CMOS flash analog-to-digital converter for high speed and low voltage applications.  |
ACM Great Lakes Symposium on VLSI  |
2003 |
DBLP DOI BibTeX RDF |
TIQ comparator, fat tree encoder, flash ADC, analog-to-digital converter, low voltage, high speed |
| 3 | Kohtaro Ohba, Jesus Carlos Pedraza Ortega, Kazuo Tanie, Masataka Tsuji, Shigeru Yamada |
Microscopic vision system with all-in-focus and depth images.  |
Mach. Vis. Appl.  |
2003 |
DBLP DOI BibTeX RDF |
All-in-focus image, High-speed image-processing system, FPGA high-speed camera, Depth from focus |
| 3 | Mehrdad Nourani, Amir Attarha |
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs.  |
J. Electronic Testing  |
2002 |
DBLP DOI BibTeX RDF |
integrity fault, integrity loss, transfer function matrix, built-in self-test, system-on-chip, test pattern generation, signal integrity, model order reduction, interconnect testing, skew detection, noise detection, high-speed interconnect |
| 3 | Christopher Krügel, Fredrik Valeur, Giovanni Vigna, Richard A. Kemmerer |
Stateful Intrusion Detection for High-Speed Networks. (PDF / PS)  |
IEEE Symposium on Security and Privacy  |
2002 |
DBLP DOI BibTeX RDF |
Intrusion Detection, High-Speed Networks, Security Analysis |
| 3 | Seung Hoon Choi, Kaushik Roy |
Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits.  |
DELTA  |
2002 |
DBLP DOI BibTeX RDF |
Crosstalk, Inductance, Capacitance, Noise Analysis, Noise Margin, High Speed Circuit |
| 3 | Henrik Abrahamsson, Olof Hagsand, Ian Marsh |
TCP over High Speed Variable Capacity Links: A Simulation Study for Bandwidth Allocation.  |
Protocols for High-Speed Networks  |
2002 |
DBLP DOI BibTeX RDF |
TCP, rate control, rate adaption, DTM |
| 3 | Joseph D. Touch |
Peer Networks - High-Speed Solution or Challenge?  |
Protocols for High-Speed Networks  |
2002 |
DBLP DOI BibTeX RDF |
|
| 3 | Evgueni Ossipov, Gunnar Karlsson |
A Simplified Guaranteed Service for the Internet.  |
Protocols for High-Speed Networks  |
2002 |
DBLP DOI BibTeX RDF |
|
| 3 | Cristel Pelsser, Stefaan De Cnodder |
Improvements to Core Stateless Fair Queueing.  |
Protocols for High-Speed Networks  |
2002 |
DBLP DOI BibTeX RDF |
|
| 3 | Pi-Chung Wang, Chia-Tai Chan, Wei-Chun Tseng, Yaw-Chung Chen |
A Fast Packet Classification by Using Enhanced Tuple Pruning.  |
Protocols for High-Speed Networks  |
2002 |
DBLP DOI BibTeX RDF |
|
| 3 | Hans G. Kerkhoff, Han Speek, M. Shashani, Manoj Sachdev |
Design for Delay Testability in High-Speed Digital ICs.  |
J. Electronic Testing  |
2001 |
DBLP DOI BibTeX RDF |
BIST, delay-fault testing, design for delay testability, high-speed testing |
| 3 | Iboun Taimiya Sylla, Mustapha Slamani, Bozena Kaminska |
A Unity Gain High Speed Buffer to Improve Signal Integrity in High Frequency Test Interface.  |
J. Electronic Testing  |
2001 |
DBLP DOI BibTeX RDF |
ATE interface, impedance matching, design for testability, high speed test |
| 3 | Toshihiko Wakahara, Mitsuji Matsumoto, Takao Shimizu, Hideyuki Ohara, S. Kayama, Tetsuji Yamato, I. Sono, Y. Nakatsuji |
New 60 GHz High-Speed Wide Campus Network.  |
ICME  |
2001 |
DBLP DOI BibTeX RDF |
60 GHz millimeter wave, Wireless LAN, High-speed network, Campus network |
| 3 | Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda |
High speed IDDQ test and its testability for process variation.  |
Asian Test Symposium  |
2000 |
DBLP DOI BibTeX RDF |
high speed IDDQ test, charge current, gate load capacitances, test input vector application, CMOS IC production, logic testing, integrated circuit testing, process variation, testability, CMOS logic circuits, production testing |
| 3 | Johann Großschädl |
The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip.  |
ACSAC  |
2000 |
DBLP DOI BibTeX RDF |
RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency |
| 3 | Tatsuya Hagiwara, Hiroki Doi, Hideki Tode, Hiromasa Ikeda |
High-Speed Calculation Method of the Hurst Parameter Based on Real Traffic. (PDF / PS)  |
LCN  |
2000 |
DBLP DOI BibTeX RDF |
high-speed calculation method, traffic measurement analysis, packet traffic, long range dependent properties, variance-time plot method, performance, packet switching, fractals, self-similarity, buffer overflow, telecommunication traffic, network performance, telecommunication congestion control, network control, Hurst parameter |
| 3 | Cesar Torres-Huitzil, Miguel Arias-Estrada |
An FPGA Architecture for High Speed Edge and Corner Detection.  |
CAMP  |
2000 |
DBLP DOI BibTeX RDF |
FPGA resources utilization, computer vision, computer vision, edge detection, architecture design, corner detection, high speed, FPGA architecture |
| 3 | Takashi Komuro, Idaku Ishii, Masatoshi Ishikawa, Atsushi Yoshida |
High Speed Target Tracking Vision Chip.  |
CAMP  |
2000 |
DBLP DOI BibTeX RDF |
vision chip, chip architecture, high speed target tracking, target tracking, target tracking |
| 3 | Sivaram Balasubramanian, Francisco P. Maturana, Dave Vasko |
An Autonomous Cooperative System for High Speed Sorting Systems. (PDF / PS)  |
DEXA Workshops  |
2000 |
DBLP DOI BibTeX RDF |
autonomous cooperative system, high speed sorting systems, flexible control, self-contained software entities, intelligent agent technology, software holons, multi-agent systems, distributed artificial intelligence, holonic manufacturing system |
| 3 | Patrick Fay, Gary H. Bernstein, David H. Chow, J. Schulman, Pinaki Mazumder, W. Williamson, B. K. Gilbert |
Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High-Speed Digital Circuit Applications.  |
Great Lakes Symposium on VLSI  |
1999 |
DBLP DOI BibTeX RDF |
resonant tunneling diode (RTD), resonant interband tunneling diode (RITD), heterostructure field-effect transistor (HFET), ultra-high-speed logic circuits |
| 3 | Carsten Benecke |
A Parallel Packet Screen for High Speed Networks.  |
ACSAC  |
1999 |
DBLP DOI BibTeX RDF |
Packet Screen, Parallel Processing, Firewall, High Speed Networks |
| 3 | Thierry Monteil, Jean-Marie Garcia, David Gauchard, Olivier Brun |
Communication Kernel for High Speed Networks in the Parallel Environment LANDA-HSN.  |
IWCC  |
1999 |
DBLP DOI BibTeX RDF |
communication kernel, message passing, high speed networks, parallel environment |
| 3 | Chunming Qiao |
The Optical Future of High-Speed Networks.  |
Protocols for High-Speed Networks  |
1999 |
DBLP BibTeX RDF |
|
| 3 | Yi Du, Gerald M. Masson |
Enhancing Accuracy of Probe Packet-based Congestion Detection in High Speed Networks.  |
ICCCN  |
1998 |
DBLP DOI BibTeX RDF |
Network congestion detection, probe packets, performance analysis, feedback control, high speed networks |
| 3 | Allen E. Sjogren, Chris J. Myers |
Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline.  |
ARVLSI  |
1997 |
DBLP DOI BibTeX RDF |
Mixed synchronous/asynchronous interfacing, stoppable clocks, high-speed pipelines, globally synchronous locally asynchronous, metastability, synchronization failure |
| 3 | William Perrizo, Zhili Zhang, Stephen Krebsbach |
Strategies for implementing distributed query algorithms over high-speed, bandwidth-on-demand, wide area networks. (PDF / PS)  |
COMPSAC  |
1997 |
DBLP DOI BibTeX RDF |
high-speed bandwidth-on-demand wide area networks, distributed query processing algorithms, latency delay reduction, multicast issue handling, transmission delay reduction, local processing delay reduction, distributed join algorithm, time cost, near optimal performance, distributed databases, analytical model, distributed database systems |
| 3 | Zbigniew Hulicki |
A Neural Controller for Transit Node in High Speed Communication Networks.  |
MASCOTS  |
1997 |
DBLP DOI BibTeX RDF |
transit node, high speed communication networks, multi-megabit communication services, cost effective communications, complex heterogeneous networks, interworking MAN segments, neural nets, traffic control, neural controller, controller design, neurocontrollers, network resource management |
| 3 | Yasuo Watanabe, Katsutoshi Takahashi, Masayuki Nakazawa |
Automated detection and matching of spots in autoradiogram images of two-dimensional electrophoresis for high-speed genome scanning. (PDF / PS)  |
ICIP  |
1997 |
DBLP DOI BibTeX RDF |
electrophoresis, automated detection, autoradiogram images, two-dimensional electrophoresis, high-speed genome scanning, restriction landmark genome scanning, genetic locus, copy number, restriction landmark, ring operators, RLGS patterns, differential state, Delaunay net, relative neighbourhood graphs, matching, pattern analysis, intensity, automated analysis, spots, gradient operators |
| 3 | Pertti Raatikainen, Juha Zidbeck |
A bridging solution for delivering multimedia services in CATV networks.  |
EUROMICRO  |
1997 |
DBLP DOI BibTeX RDF |
community antenna television, CATV networks, access platform, HFC technology, two-way communication, trunk network, bridging solution, FSR, high-speed applications, high-speed Internet application, Community Area TV, protocols, ATM, multimedia services, interactive services |
| 3 | Vijay Varadharajan |
Security in High-Speed Networks. (PDF / PS)  |
LCN  |
1996 |
DBLP DOI BibTeX RDF |
high speed networks security, broadband services, connectionless switched multimegabit data service, connection-oriented frame relay, USA, security services design, broadband network interfaces, TCP/IP networks, OSI networks, connectionless SMDS, local area networks, security protocols, wide area networks, wide area networks, broadband networks, Europe |
| 3 | Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska |
Design and performance of CMOS TSPC cells for high speed pseudo random testing.  |
VTS  |
1996 |
DBLP DOI BibTeX RDF |
CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists |
| 3 | Shriram Kulkarni, Pinaki Mazumder, George I. Haddad |
A high-speed 32-bit parallel correlator for spread spectrum communication.  |
VLSI Design  |
1996 |
DBLP DOI BibTeX RDF |
pseudonoise codes, radio equipment, high speed pipelined digital parallel correlator, lattice field programmable gate array, 87 MHz, 11.5 ns, field programmable gate arrays, parallel processing, data stream, correlators, CDMA, pipeline processing, CMOS integrated circuit, CMOS digital integrated circuits, transceiver, spread spectrum communication, spread spectrum communication, digital radio, 32 bit, PN sequence |
| 3 | Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin |
Design tradeoffs in high speed multipliers and FIR filters.  |
VLSI Design  |
1996 |
DBLP DOI BibTeX RDF |
high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed |
| 3 | Tapan J. Chakraborty, Vishwani D. Agrawal |
Design for high-speed testability of stuck-at faults.  |
VLSI Design  |
1996 |
DBLP DOI BibTeX RDF |
design for high-speed testability, stuck-at fault detection, signal transition, timing hazard, multivalue algebra, dh-robust test, sequential feedback, reconvergent fanout, cycle-free sequential circuit, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, partial scan, test generation algorithm, critical path delay |
| 3 | W. Melody Moh, Yu-Feng Chung, Teng-Sheng Moh, Joanna Wang |
Evaluation of high speed LAN protocols as multimedia carriers . (PDF / PS)  |
ICCD  |
1996 |
DBLP DOI BibTeX RDF |
high speed LAN protocols, multimedia carriers, full-motion video, 100 Base-T Fast Ethernet, Ethernet++, 100 VG-AnyLAN, protocols, animation, images, audio, graphics, voice |
| 3 | Thomas Wittenberg, Manfred Moser, Monika Tigges, Ulrich Eysholdt |
Recording, processing, and analysis of digital high-speed sequences in glottography.  |
Mach. Vis. Appl.  |
1995 |
DBLP DOI BibTeX RDF |
Vocal fold vibration, High-speed glottography, Semiautomatic motion analysis, Image segmentation, Medical imaging |
| 3 | H. Zhou, Howard C. Card, Gregory E. Bridges |
Parallel pseudorandom number generation in GaAs cellular automata for high speed circuit testing.  |
J. Electronic Testing  |
1995 |
DBLP DOI BibTeX RDF |
testing high-speed circuits, cellular automata, pseudorandom number generation, GaAs |
| 3 | Cameron Braun, V. Sirkay, H. Uriona, Srini W. Seetharam, E. Yousefi, David W. Petr, Douglas Niehaus, Victor Frost, Joseph B. Evans, Gary J. Minden |
A High Speed Implementation of Adaptive Shaping for Dynamic Bandwidth Allocation. (PDF / PS)  |
HPDC  |
1995 |
DBLP DOI BibTeX RDF |
high speed implementation, adaptive shaping, static control mechanisms, adaptive rate control algorithm, burst size, high performance distributed systems, performance evaluation, protocols, asynchronous transfer mode, local area networks, local area network, ATM networks, dynamic bandwidth allocation |
| 3 | Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews |
High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.  |
ARVLSI  |
1995 |
DBLP DOI BibTeX RDF |
counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television |
| 3 | Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III |
A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.  |
ARVLSI  |
1995 |
DBLP DOI BibTeX RDF |
high-speed fine-resolution pattern generation, data signals, edge placement, matched delays, MOSIS CMOS technology, 100 ps, 833 Mbit/s, architecture, delays, test pattern generators, network interfaces, CMOS digital integrated circuits, 1.2 micron |
| 3 | Peter Martini |
Real-time communication in shared-medium high speed lans.  |
High-Speed Networking for Multimedia Applications ![In: High-Speed Networking for Multimedia Applications [2nd Int. Workshop on Architecture and Protocols for High Performance Networks, Dagstuhl, June 19-23, 1995], pp. 267-284, 1995, Kluwer, 0-7923-9681-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP BibTeX RDF |
|
| 3 | Adam Wolisz, Morten Schläger, Jost Weinmiller, Hagen Woesner |
Wireless access to high speed networks.  |
High-Speed Networking for Multimedia Applications ![In: High-Speed Networking for Multimedia Applications [2nd Int. Workshop on Architecture and Protocols for High Performance Networks, Dagstuhl, June 19-23, 1995], pp. 361-381, 1995, Kluwer, 0-7923-9681-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP BibTeX RDF |
|
| 3 | Sanjeev Gupta, Carey L. Williamson |
A performance study of adaptive video coding algorithms for high speed networks. (PDF / PS)  |
LCN  |
1995 |
DBLP DOI BibTeX RDF |
adaptive video coding, 10 Mbit/s, performance evaluation, performance, data compression, video coding, video coding, image coding, video compression, high speed networks, network congestion, Available Bit Rate, network load, 100 Mbit/s |
| 3 | Gun Seo, Sun-Moo Kang, Dae Young Kim, Hong-Bum Jeon |
A distributed cycle reset protocol for the high-speed LAN/MAN. (PDF / PS)  |
LCN  |
1995 |
DBLP DOI BibTeX RDF |
shared medium access protocol, distributed cycle reset protocol, high-speed LAN/MAN, distributed cycle reset function, token reset, distributed cycle reset, access control, local area networks, access protocols, metropolitan area networks |
| 3 | Mohsen Guizani |
A new protocol for optical high-speed packet-switched networks. (PDF / PS)  |
LCN  |
1995 |
DBLP DOI BibTeX RDF |
optical high-speed packet-switched networks, broadcast passive optical star coupler topology, tunable transmitters, tunable receivers, data channel, signalling channel, data channel wavelength, station, connection-oriented traffic, datagram traffic, LAN applications, MAN applications, packet switching, network architecture, wavelength division multiplexing, access protocols, optical communication, metropolitan area networks, media access protocol, optical fibre networks, optical fibre LAN, control channel |
| 3 | W. Melody Moh, Yu-Jen Chien, Irene Zhang, Teng-Sheng Moh |
Delay performance evaluation of high speed protocols for multimedia communications.  |
ICCCN  |
1995 |
DBLP DOI BibTeX RDF |
delay performance evaluation, high speed protocols, delay fairness, worst-case delay performance, distributed queue dual bus, CRMA, cyclic reservation multiple access, DQMA, distributed queue multiple access, FDQ, fair distributed queue, heavy network load, reservation-based protocols, throughput, multimedia communication, multimedia communication, multimedia traffic, quality of service requirements, DQDB, access delay, message delay, heterogeneous traffic |
| 3 | Jens Kargaard Madsen, Stephen I. Long |
A High-Speed Interconnect Network Using Ternary Logic. (PDF / PS)  |
ISMVL  |
1995 |
DBLP DOI BibTeX RDF |
high-speed interconnect network, STARI, delay differences, crossbar topology, LSI GaAs chips, MESFET process, multiprocessor interconnection networks, multiprocessor system, buffers, clock skew, ternary logic, ternary logic, point-to-point communication |
| 3 | Mario Kovac, N. Ranganathan |
JAGUAR: a high speed VLSI chip for JPEG image compression standard.  |
VLSI Design  |
1995 |
DBLP DOI BibTeX RDF |
JAGUAR, high speed VLSI chip, JPEG image compression standard, pipelined single chip VLSI architecture, entropy encoder, clock rate, input rate, CMOS VLSI chip, Huffman entropy coding, 1024 pixel, 1048576 pixel, VLSI, parallel architectures, data compression, image coding, discrete cosine transforms, discrete cosine transform, pipeline processing, color images, image colour analysis, digital signal processing chips, Huffman codes, high throughput, CMOS digital integrated circuits, entropy codes, 100 MHz |
| 3 | V. K. Jain, L. Lin |
High-speed double precision computation of nonlinear functions.  |
IEEE Symposium on Computer Arithmetic  |
1995 |
DBLP DOI BibTeX RDF |
high-speed double precision computation, interpolative approach, third degree polynomial, image processing, interpolation, interpolation, scientific computing, digital arithmetic, multiplications, coprocessors, coprocessors, real-time image processing, nonlinear functions, silicon area |
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