Search results for "instruction cache"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Han-Xin Sun, Kun-Peng Yang, Yulai Zhao, Dong Tong, Xu Cheng	CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	instruction TLB, instruction fetch unit, power-efficient design, computer architecture, dynamic voltage scaling, instruction cache
3	Yen-Jen Chang	Exploiting frequent opcode locality for power efficient instruction cache.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	frequent opcode locality, instruction cache, power-efficient
3	Maziar Goudarzi, Tohru Ishihara	Instruction cache leakage reduction by changing register operands and using asymmetric sram cells.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	asymmetric sram, leakage, instruction cache, register renaming
3	Onur Aciiçmez, Werner Schindler	A Vulnerability in RSA Implementations Due to Instruction Cache Analysis and Its Demonstration on OpenSSL.	CT-RSA	2008	DBLP DOI BibTeX RDF	Instruction-Cache Attack, MicroArchitectural Analysis, RSA, Stochastic Process, Side Channel Analysis, Montgomery Multiplication
3	Ahmad Zmily, Christos Kozyrakis	A low power front-end for embedded processors using a block-aware instruction set.	CASES	2007	DBLP DOI BibTeX RDF	instruction re-ordering, low power front-end, software hints, tagless instruction cache, unified instruction cache and BTB, instruction prefetching
3	Stavros Harizopoulos, Anastassia Ailamaki	Improving instruction cache performance in OLTP.	ACM Trans. Database Syst.	2006	DBLP DOI BibTeX RDF	Instruction cache, cache misses
3	Soong Hyun Shin, Cheol Hong Kim, Chu Shik Jhon	An Effective Instruction Cache Prefetch Policy by Exploiting Cache History Information.	EUC	2005	DBLP DOI BibTeX RDF	Computer architecture, embedded processor, instruction cache, cache prefetching
3	Chuanjun Zhang	An efficient direct mapped instruction cache for application-specific embedded systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	efficient cache design, instruction cache, low power cache
3	Bramha Allu, Wei Zhang 0002	Static next sub-bank prediction for drowsy instruction cache.	CASES	2004	DBLP DOI BibTeX RDF	compiler, instruction cache, leakage energy
3	Frank Mueller, David B. Whalley	Fast instruction cache analysis via static cache simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	instruction cache analysis, static cache simulation, cache configuration, instruction reference, cache hit, counter incrementation, code execution frequency, local state information updating, frequency counters, program exit, virtual machines, cache storage, program diagnostics, dynamic simulation, cache miss
2	Juan Castillo, Hector Posadas, Eugenio Villar, Marcos Martínez	Fast instruction cache modeling for approximate timed HW/SW co-simulation.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	performance estimation, cache modeling, electronic system level
2	Yun Liang, Tulika Mitra	Instruction cache locking using temporal reuse profile.	DAC	2010	DBLP DOI BibTeX RDF	cache locking, temporal reuse profile, cache
2	Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, Víctor Viñals	Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems.	RTCSA	2010	DBLP DOI BibTeX RDF	prefetch, WCET, instruction cache
2		Instruction Cache.	Encyclopedia of Database Systems	2009	DBLP DOI BibTeX RDF
2	Chun-Hung Lai, Fu-Ching Yang, Chung-Fu Kao, Ing-Jer Huang	A trace-capable instruction cache for cost efficient real-time program trace compression in SoC.	DAC	2009	DBLP DOI BibTeX RDF	real time, cache, compression, program trace
2	Kapil Anand, Rajeev Barua	Instruction cache locking inside a binary rewriter.	CASES	2009	DBLP DOI BibTeX RDF	cache locking, embedded systems, caches, binary rewriting
2	Weili Li, Lixin Yu	Efficient line buffer instruction cache scheme with prefetch.	Int. Conf. Interaction Sciences	2009	DBLP DOI BibTeX RDF	line buffer, cache, prefetch
2	Cuiping Xu, Ge Zhang, Shouqing Hao	Fast Way-Prediction Instruction Cache for Energy Efficiency and High Performance.	NAS	2009	DBLP DOI BibTeX RDF
2	Zhiguo Ge, Tulika Mitra, Weng-Fai Wong	A DVS-based pipelined reconfigurable instruction memory.	DAC	2009	DBLP DOI BibTeX RDF	reconfigurable memory, low power, instruction cache
2	Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson	Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE).	LCTES	2009	DBLP DOI BibTeX RDF	l0/filter cache, lookahead instruction fetch engine (life), tagless hit instruction cache (th-ic)
2	Samarjit Chakraborty, Tulika Mitra, Abhik Roychoudhury, Lothar Thiele	Cache-aware timing analysis of streaming applications.	Real-Time Systems	2009	DBLP DOI BibTeX RDF	Timing analysis, Instruction cache, Streaming applications
2	Roberto Giorgi, Paolo Bennati	Filtering drowsy instruction cache to achieve better efficiency.	SAC	2008	DBLP DOI BibTeX RDF	low-power, leakage, drowsy cache, filter cache
2	Clément Ballabriga, Hugues Cassé, Pascal Sainrat	An improved approach for set-associative instruction cache partial analysis.	SAC	2008	DBLP DOI BibTeX RDF	WCET computation, partial cache analysis, partial static analysis, abstract interpretation, COTS, instruction cache
2	Santanu Kumar Dash, Thambipillai Srikanthan	Rapid estimation of instruction cache hit rates using loop profiling.	ASAP	2008	DBLP DOI BibTeX RDF
2	Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, J. L. Villarroel, Víctor Viñals	Avoiding the WCET Overestimation on LRU Instruction Cache.	RTCSA	2008	DBLP DOI BibTeX RDF
2	Timothy M. Jones, Sandro Bartolini, Bruno De Bus, John Cavazos, Michael F. P. O'Boyle	Instruction Cache Energy Saving Through Compiler Way-Placement.	DATE	2008	DBLP DOI BibTeX RDF
2	Yosi Ben-Asher, Omer Boehm, Daniel Citron, Gadi Haber, Moshe Klausner, Roy Levin, Yousef Shajrawi	Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache.	HiPEAC	2008	DBLP DOI BibTeX RDF
2	Yu Sun, Wei Zhang 0002	Efficient code caching to improve performance and energy consumption for java applications.	CASES	2008	DBLP DOI BibTeX RDF	code caching, code generation, java virtual machine, instruction cache, JIT compiler
2	Eui-Young Chung, Cheol Hong Kim, Sung Woo Chung	An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching.	DELTA	2008	DBLP DOI BibTeX RDF	way predictioin, low power, Instruction cache
2	Nikolas Kroupis, Dimitrios Soudris	Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate.	PATMOS	2007	DBLP DOI BibTeX RDF
2	Stephen Hines, David B. Whalley, Gary S. Tyson	Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache.	MICRO	2007	DBLP DOI BibTeX RDF
2	Fadia Nemer, Hugues Cassé, Pascal Sainrat, Ali Awada	Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache Analysis.	SIES	2007	DBLP DOI BibTeX RDF
2	Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel	Instruction trace compression for rapid instruction cache simulation.	DATE	2007	DBLP DOI BibTeX RDF
2	Onur Aciiçmez	Yet another MicroArchitectural Attack: : exploiting I-Cache.	CSAW	2007	DBLP DOI BibTeX RDF	MicroArchitectural analysis, RSA, side channel analysis, instruction cache, Montgomery Multiplication, modular exponentiation
2	Jun Yan, Wei Zhang 0002	WCET analysis of instruction caches with prefetching.	LCTES	2007	DBLP DOI BibTeX RDF	instruction cache, hard real-time, worst-case execution time analysis, instruction prefetching
2	Yuying Wang, Xingshe Zhou	Mutual Effect of Instruction Layout Optimization and Instruction Memory Hierarchy.	ICPP Workshops	2007	DBLP DOI BibTeX RDF	Instruction Layout Optimization, Instruction Cache Miss Rate, Cache Memory Hierarchy
2	Yefim Shuf, Ian M. Steiner	Characterizing a Complex J2EE Workload: A Comprehensive Analysis and Opportunities for Optimizations.	ISPASS	2007	DBLP DOI BibTeX RDF	J2EE workload, Java benchmarks, SPECjvm98, SPECjbb2000, Java 2 Enterprise Edition, SPECjAppServer2004, systems research, software research, cache-to-cache modified data transfers, intelligent thread co-scheduling, Java heap, bursty data cache, Java virtual method calls, optimizations, performance analysis, garbage collection, instruction cache, data prefetching, commercial workload
2	Tao Li, Lizy K. John	OS-aware tuning: improving instruction cache energy efficiency on system workloads.	IPCCC	2006	DBLP DOI BibTeX RDF
2	Kugan Vivekanandarajah, Thambipillai Srikanthan, Christopher T. Clarke	Profile Directed Instruction Cache Tuning for Embedded Systems.	ISVLSI	2006	DBLP DOI BibTeX RDF
2	Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing	An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Periodically Drowsy Speculative Recover, Adaptive, Leakage Power, Drowsy cache
2	Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa	Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Nikolas Kroupis, Stylianos Mamagkakis, Dimitrios Soudris	An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems.	ESTImedia	2006	DBLP DOI BibTeX RDF
2	Ken W. Batcher, Robert A. Walker	Interrupt Triggered Software Prefetching for Embedded CPU Instruction Cache.	IEEE Real Time Technology and Applications Symposium	2006	DBLP DOI BibTeX RDF
2	Jason E. Miller, Anant Agarwal	Software-based instruction caching for embedded processors.	ASPLOS	2006	DBLP DOI BibTeX RDF	instruction cache, chaining, software caching
2	Sung Woo Chung, Kevin Skadron	Using Branch Prediction Information for Near-Optimal I-Cache Leakage.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Low Power, Branch Prediction, Leakage, Instruction Cache, Drowsy Cache
2	Xianfeng Li, Abhik Roychoudhury, Tulika Mitra	Modeling out-of-order processors for WCET analysis.	Real-Time Systems	2006	DBLP DOI BibTeX RDF	Worst-case execution time (WCET) analysis, Out-of-order superscalar processor, Branch prediction, Instruction cache
2	Cheol Hong Kim, Sung-Hoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon	First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption.	SAMOS	2005	DBLP DOI BibTeX RDF
2	Cheol Kim, Sung Chung, Chu Shik Jhon	An Innovative Instruction Cache for Embedded Processors.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
2	Xin Lu, Yuzhuo Fu	Reducing leakage power in instruction cache using WDC for embedded processors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Xianfeng Li, Tulika Mitra, Abhik Roychoudhury	Modeling Control Speculation for Timing Analysis.	Real-Time Systems	2005	DBLP DOI BibTeX RDF	micro-architectural modeling, worst case execution time, branch prediction, schedulability analysis, instruction cache
2	Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Reducing instruction cache energy consumption using a compiler-based strategy.	TACO	2004	DBLP DOI BibTeX RDF	compiler optimizations, Leakage power, cache design
2	Ravi V. Batchu, Daniel A. Jiménez	Exploiting Procedure Level Locality to Reduce Instruction Cache Misses.	Interaction between Compilers and Computer Architectures	2004	DBLP DOI BibTeX RDF
2	Abdur Rakib, Oleg Parshin, Stephan Thesing, Reinhard Wilhelm	Component-Wise Instruction-Cache Behavior Prediction.	ATVA	2004	DBLP DOI BibTeX RDF
2	Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya	Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Jingren Zhou, Kenneth A. Ross	Buffering Database Operations for Enhanced Instruction Cache Performance.	SIGMOD Conference	2004	DBLP DOI BibTeX RDF
2	Guowei Wu, Lin Yao	A New WCET Estimation Algorithm Based on Instruction Cache and Prefetching Combined Model.	ICESS	2004	DBLP DOI BibTeX RDF
2	Christophe Guillon, Fabrice Rastello, Thierry Bidault, Florent Bouchez	Procedure placement using temporal-ordering information: dealing with code size expansion.	CASES	2004	DBLP DOI BibTeX RDF	min-matching, profiling, instruction cache, Hamiltonian-path, cache miss, code size, code placement
2	Chia-Lin Yang, Chien-Hao Lee	HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction.	ISLPED	2004	DBLP DOI BibTeX RDF	embedded systems, low power design, instruction cache
2	Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir	Exploiting program hotspots and code sequentiality for instruction cache leakage management.	ISLPED	2003	DBLP DOI BibTeX RDF	leakage power, cache design
2	Youtao Zhang, Jun Yang 0002	Low cost instruction cache designs for tag comparison elimination.	ISLPED	2003	DBLP DOI BibTeX RDF	low-power instruction cache, tag comparison elimination
2	Marco Garatti	FICO: A Fast Instruction Cache Optimizer.	SCOPES	2003	DBLP DOI BibTeX RDF
2	Ann Gordon-Ross, Susan Cotterell, Frank Vahid	Tiny instruction caches for low power embedded systems.	ACM Trans. Embedded Comput. Syst.	2003	DBLP DOI BibTeX RDF	embedded systems., fixed program, low power, instruction cache, low energy, architecture tuning, Loop cache, filter cache
2	Murali Annavaram, Jignesh M. Patel, Edward S. Davidson	Call graph prefetching for database applications.	ACM Trans. Comput. Syst.	2003	DBLP DOI BibTeX RDF	Instruction cache prefetching, database, call graph
2	Rakesh Kumar, Dean M. Tullsen	Compiling for instruction cache performance on a multithreaded architecture.	MICRO	2002	DBLP DOI BibTeX RDF
2	Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Compiler-directed instruction cache leakage optimization.	MICRO	2002	DBLP DOI BibTeX RDF
2	Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Energy-efficient instruction cache using page-based placement.	CASES	2001	DBLP DOI BibTeX RDF
2	Yul Chu, Mabo Robert Ito	A 2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented Languages. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
2	Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe	Performance estimation of embedded software with instruction cache modeling.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF
2	John Kalamatianos, Alireza Khalafi, David R. Kaeli, Waleed Meleis	Analysis of Temporal-Based Program Behavior for Improved Instruction Cache Performance.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	program reordering, graph pruning, graph coloring, Instruction caches, temporal locality, conflict misses
2	Christopher A. Healy, Robert D. Arnold, Frank Mueller, David B. Whalley, Marion G. Harmon	Bounding Pipeline and Instruction Cache Performance.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	best case execution time, Real-time systems, pipelining, timing analysis, worst case execution time, instruction cache
2	Chi-Hung Chi, Jun-Li Yuan	Load-Balancing Branch Target Cache and Prefetch Buffer.	ICCD	1999	DBLP DOI BibTeX RDF	branch target cache, load-balancing, Memory, prefetching, instruction cache
2	Jared Stark, Paul Racunas, Yale N. Patt	Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order.	MICRO	1997	DBLP BibTeX RDF	instruction supply, superscalar processors, out-of-order execution
2	Shyh-An Chi, R.-Ming Shiu, Jih-Ching Chiu, Si-En Chang, Chung-Ping Chung	Instruction Cache Prefetching with Extended BTB. (PDF / PS)	ICPADS	1997	DBLP DOI BibTeX RDF
2	W. Lynn Gallagher, Chuan-lin Wu	Evaluation of a memory hierarchy for the MTS multithreaded processor. (PDF / PS)	ICPADS	1997	DBLP DOI BibTeX RDF	memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache
2	Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye	Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings.	MICRO	1996	DBLP BibTeX RDF	TINKER experimental testbed, compressed encodings, compressed instruction encoding, i-fetch hardware, instruction fetch mechanisms, instruction words, multiple instruction issue, silo cache, parallel architectures, trace-driven simulations, instruction cache, VLIW architectures
2	Eric Rotenberg, Steve Bennett, James E. Smith	Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching.	MICRO	1996	DBLP BibTeX RDF	multiple branch prediction, superscalar processors, instruction cache, trace cache, instruction fetching
2	Tai-Yi Huang, Jane W.-S. Liu, David Hull	A Method for Bounding the Effect of DMA I/O Interference on Program Execution Time. (PDF / PS)	IEEE Real-Time Systems Symposium	1996	DBLP DOI BibTeX RDF	DMA I/O operation, program execution time, DMA controller, cycle-stealing mode, bus cycles, cycle stealing operation, executing program, machine instruction, instruction-cache architectures, input output operation, simulations, real-time systems, worst-case execution time, data transfer
2	Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grunwald	Instruction Cache Fetch Policies for Speculative Execution.	ISCA	1995	DBLP DOI BibTeX RDF	C++
2	Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe	Performance estimation of embedded software with instruction cache modeling.	ICCAD	1995	DBLP DOI BibTeX RDF
2	Ching-Long Su, Alvin M. Despain	Cache designs for energy efficiency.	HICSS	1995	DBLP DOI BibTeX RDF	cache design techniques, superpipelined processors, cache energy consumption estimation, block buffering, cache sub-banking, Gray code addressing, instruction cache designs, consecutive accessing, energy efficiency, microprocessors, power consumption, energy conservation, data caches, cache storage, superscalar processors, Gray codes, energy reduction, CMOS memory circuits
2	Gideon D. Intrater, Ilan Y. Spillinger	Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	decoded instruction cache, variable instruction length computers, instruction decoder, instruction pipeline stages, instruction length distribution, UNIX applications, performance evaluation, performance evaluation, computer architecture, trace driven simulations, buffer storage
2	Todd E. Rockoff	SIMD Instruction Cache.	SPAA	1994	DBLP DOI BibTeX RDF
2	Abraham Mendlson, Shlomit S. Pinter, Ruth Shtokhamer	Compile Time Instruction Cache Optimizations.	CC	1994	DBLP DOI BibTeX RDF
2	William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu	The Effect of Code Expanding Optimizations on Instruction Cache Design.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	code expanding optimizations, instruction placement, function inline expansion, superscalar optimizations, small caches, medium caches, load forwarding, large caches, C compiler, code expansion, optimisation, cache memory, memory architecture, buffer storage, instruction cache, code optimization, cache design, miss ratio
2	David B. Whalley	Fast Instruction Cache Performance Evaluation Using Compile-Time Analysis.	SIGMETRICS	1992	DBLP DOI BibTeX RDF	instruction cache, trace analysis, cache simulation, trace generation
2	Rajiv Gupta, Chi-Hung Chi	Improving instruction cache behavior by reducing cache pollution.	SC	1990	DBLP BibTeX RDF
2	Peter Steenkiste	The Impact of Code Density on Instruction Cache Performance.	ISCA	1989	DBLP DOI BibTeX RDF
2	Wen-mei W. Hwu, Pohua P. Chang	Achieving High Instruction Cache Performance with an Optimizing Compiler.	ISCA	1989	DBLP DOI BibTeX RDF
1	Tiantian Liu, Minming Li, Chun Jason Xue	Instruction cache locking for multi-task real-time embedded systems.	Real-Time Systems	2012	DBLP DOI BibTeX RDF
1	Ji Gu, Hui Guo, Patrick Li	An on-chip instruction cache design with one-bit tag for low-power embedded systems.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Maziar Goudarzi, Tohru Ishihara, Hamid Noori	Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Chun-Hung Lai, Fu-Ching Yang, Ing-Jer Huang	A Trace-Capable Instruction Cache for Cost-Efficient Real-Time Program Trace Compression in SoC.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Chen Cai-Sen, Wang Tao, Chen Xiao-Cen, Zhou Ping	An Improved Trace Driven Instruction Cache Timing Attack on RSA.	IACR Cryptology ePrint Archive	2011	DBLP BibTeX RDF
1	Damien Hardy, Isabelle Puaut	WCET analysis of instruction cache hierarchies.	Journal of Systems Architecture - Embedded Systems Design	2011	DBLP DOI BibTeX RDF
1	Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, Víctor Viñals	Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems.	Journal of Systems Architecture - Embedded Systems Design	2011	DBLP DOI BibTeX RDF
1	Timothy M. Jones, Sandro Bartolini, Jonas Maebe, Dominique Chanet	Link-time optimization for power efficiency in a tagless instruction cache.	CGO	2011	DBLP DOI BibTeX RDF
1	Yu Liu, Wei Zhang 0002	Stack distance based worst-case instruction cache performance analysis.	SAC	2011	DBLP DOI BibTeX RDF
1	Mark Bartlett, Iain Bate, James Cussens, Dimitar Kazakov	Probabilistic Instruction Cache Analysis Using Bayesian Networks.	RTCSA	2011	DBLP DOI BibTeX RDF
1	Damien Hardy, Benjamin Lesage, Isabelle Puaut	Scalable Fixed-Point Free Instruction Cache Analysis.	RTSS	2011	DBLP DOI BibTeX RDF
1	Santanu Kumar Dash, Thambipillai Srikanthan	Instruction cache tuning for embedded multitasking applications.	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF