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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 93 occurrences of 65 keywords
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Results
Found 77 publication records. Showing 77 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 3 | Hoonmo Yang, Moonkey Lee |
Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator.  |
The Journal of Supercomputing  |
2005 |
DBLP DOI BibTeX RDF |
cycle-accurate, validation, system-on-chip (SoC), architecture description language (ADL), retargetable, instruction-set simulator |
| 2 | Hideaki Yanagisawa, Minoru Uehara, Hideki Mori |
Evaluation of Automatic Generation of an Instruction Set Simulator for Educational Use. |
ICDCS Workshops |
2006 |
DBLP DOI BibTeX RDF |
|
| 2 | Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger |
A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software Design. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
| 2 | Hoonmo Yang, Moonkey Lee |
Design of a Cycle-Accurate User-Retargetable Instruction-Set Simulator Using Process-Based Scheduling Scheme. |
CIS |
2004 |
DBLP DOI BibTeX RDF |
|
| 2 | G. D. Nagendra, V. G. Prem Kumar, B. S. Sheshadri Chakravarthy |
Simulation bridge: a framework for multi-processor simulation. |
CODES |
2002 |
DBLP DOI BibTeX RDF |
simulation framework, instruction set simulator, multiprocessor simulation |
| 1 | Xiang-Dong Hu, Yong Guo, Ying Zhu, Xin Guo, Peng Wang |
Design and Application of Instruction Set Simulator on Multi-Core Verification. |
J. Comput. Sci. Technol. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Igor Böhm, Björn Franke, Nigel P. Topham |
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator. |
ICSAMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shivani Raghav, Martino Ruggiero, David Atienza, Christian Pinto, Andrea Marongiu, Luca Benini |
Scalable instruction set simulator for thousand-core architectures running on GPGPUs. |
HPCS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Aparna Mandke Dani, Keshavan Varadarajan, Bharadwaj Amrutur, Y. N. Srikant |
Accelerating multi-core simulators. |
SAC |
2010 |
DBLP DOI BibTeX RDF |
chip multi-core, multi-core platform, timed petri-nets, instruction set simulator, cache simulator |
| 1 | Nicolas Pouillon, Alexandre Becoulet, Aline Vieira de Mello, François Pêcheux, Alain Greiner |
A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCs. |
IEEE International Workshop on Rapid System Prototyping |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ulrich Kühne, Sven Beyer, Christian Pichler |
Generating an Efficient Instruction Set Simulator from a Complete Property Suite. |
IEEE International Workshop on Rapid System Prototyping |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton |
Instruction set simulator generation using HARMLESS, a new hardware architecture description language. |
SimuTools |
2009 |
DBLP DOI BibTeX RDF |
hardware architecture description language, instruction set simulation |
| 1 | Daniel Christopher Powell, Björn Franke |
Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
continuous statistical machine learning, performance prediction, instruction set simulator |
| 1 | Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay |
An effective synchronization approach for fast and accurate multi-core instruction-set simulation. |
EMSOFT |
2009 |
DBLP DOI BibTeX RDF |
synchronization, multi-core, binary translation, instruction-set simulator |
| 1 | Amol Vasudeva, Arvind Kumar Sharma, Ashish Kumar |
Saksham: Customizable x86 Based Multi-Core Microprocessor Simulator. |
CICSyN |
2009 |
DBLP DOI BibTeX RDF |
Microprocessor Simulator, x86 Architecture Simulator, Register/Instruction Set Simulator, Object oriented, Assembler |
| 1 | Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Toshio Isomura, Kazuo Satou |
Trace-driven workload simulation method for Multiprocessor System-On-Chips. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
MPSoC architecture exploration, simulation, performance estimation, workload model |
| 1 | Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt |
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation. |
ACM Trans. Embedded Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
interpretive simulation, partial evaluation, instruction set architecture, Compiled simulation |
| 1 | Franco Fummi, Mirko Loghi, Massimo Poncino, Graziano Pravadelli |
A cosimulation methodology for HW/SW validation and performance estimation. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
HW/SW co-simulation, HW/SW validation, Embedded Systems |
| 1 | Hideaki Yanagisawa, Minoru Uehara, Hideki Mori |
Interface Implementation Using Ajax for Web-Based Instruction Set Simulator. |
AINA Workshops |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Murale, S. Hildebrandt, P. Bojsen, A. Urzua |
AMD64 Processor Front-End Verification (at Unit-Level Testbench) with Instruction Set Simulator. |
MTV |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mingsong Lv, Qingxu Deng, Nan Guan, Yaming Xie, Ge Yu |
ARMISS: An Instruction Set Simulator for the ARM Architecture. |
ICESS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Multiprocessor performance estimation using hybrid simulation. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
HySim, address recovery, cross replay, MPSoC, performance estimation, cache simulation, hybrid simulation |
| 1 | Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid |
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
ASIP architecture exploration for efficient IPSec encryption: A case study. |
ACM Trans. Embedded Comput. Syst. |
2007 |
DBLP DOI BibTeX RDF |
computer-aided design, ADL, ASIP, IPSec |
| 1 | Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Qin, Asa Ben-Tzur, Boris Gutkovich |
An ADL for Functional Specification of IA32. |
MTV |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jungsoo Kim, Kyungsu Kang, Heejun Shim, Woong Hwangbo, Chong-Min Kyung |
Fast estimation of software energy consumption using IPI(Inter-Prefetch Interval) energy model. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
Hybrid Simulation for Energy Estimation of Embedded Software. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hideaki Yanagisawa, Minoru Uehara, Hideki Mori |
Automatic Generation of an Instruction Set Simulator for Educational Use. |
DEXA Workshops |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Qin, Joseph D'Errico, Xinping Zhu |
A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
retargetable, instruction set simulator, compiled simulation |
| 1 | Franco Fummi, Giovanni Perbellini, Mirko Loghi, Massimo Poncino |
ISS-centric modular HW/SW co-simulation. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
systemc, co-simulation, instruction set simulator |
| 1 | Franco Fummi, Davide Quaglia, Fabio Ricciato, Maura Turolla |
Modeling and simulation of mobile gateways interacting with wireless sensor networks. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Wolfgang Mueller, Alberto Rosti, Sara Bocchio, Elvinia Riccobene, Patrizia Scandurra, Wim Dehaene, Yves Vanderperren |
UML for ESL design: basic principles, tools, and applications. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
simulation, UML, SoC, tools, profiles, SystemC, ESL design |
| 1 | Mehrdad Reshadi, Nikil Dutt, Prabhat Mishra |
A retargetable framework for instruction-set architecture simulation. |
ACM Trans. Embedded Comput. Syst. |
2006 |
DBLP DOI BibTeX RDF |
Retargetable instruction-set simulation, generic instruction model, instruction binary encoding, architecture description language, decode algorithm |
| 1 | Abdelaziz Ammari, Régis Leveugle, B. Nicolescu, Yvon Savaria |
Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection. |
DELTA |
2006 |
DBLP DOI BibTeX RDF |
software hardening, fault detection, fault injection, dependability evaluation |
| 1 | Yongfang Liang, Ishfaq Ahmad, Xiaohui Wei |
Adaptive Techniques for Simultaneous Optimization of Visual Quality and Battery Power in Video Encoding Sensors. |
ICIP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Lars Albertsson |
Holistic Debugging -- Enabling Instruction Set Simulation for Software Quality Assurance. |
MASCOTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsunori Kubo |
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster. |
Asia-Pacific Computer Systems Architecture Conference |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun |
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. |
VLSI Signal Processing |
2006 |
DBLP DOI BibTeX RDF |
C compiler retargeting, embedded processor design, architecture description language, processor model, electronic system level |
| 1 | Mehrdad Reshadi, Prabhat Mishra |
Memory access optimizations in instruction-set simulators. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
memory address-space mapping, instruction-set simulator |
| 1 | Claudio Mucci, Fabio Campi, Antonio Deledda, Alberto Fazzi, Mirco Ferri, Massimo Bocchi |
A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Haihua Shen, Lin Ma, Heng Zhang |
CRPG: a configurable random test-program generator for microprocessors. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhijit Ray, Thambipillai Srikanthan, Wu Jigang |
Practical Techniques for Performance Estimation of Processors. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhengting He, Aloysius K. Mok, Cheng Peng |
Timed RTOS Modeling for Embedded System Design. |
IEEE Real-Time and Embedded Technology and Applications Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Brett H. Meyer, Joshua J. Pieper, JoAnn M. Paul, Jeffrey E. Nelson, Sean M. Pieper, Anthony G. Rowe |
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
performance analysis, low-power design, power management, System architectures, energy-aware systems, integration and modeling, design aids |
| 1 | Youhui Zhang, Liu Dong, Yu Gu 0005, Dongsheng Wang |
Exploring Design Space Using Transaction Level Models. |
Asia-Pacific Computer Systems Architecture Conference |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ivano Barbieri, Massimo Bariani, Alberto Cabitto, Marco Raggio |
A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures. |
VLSI Signal Processing |
2005 |
DBLP DOI BibTeX RDF |
Hw-Sw co-design, simulation speed, simulation accuracy, simulation, multimedia, system on chip, DSP, flexibility, VLIW, architecture exploration, ISA |
| 1 | Moo-Kyoung Chung, Chong-Min Kyung |
Improvement of Compiled Instruction Set Simulator by Increasing Flexibility a. |
IEEE International Workshop on Rapid System Prototyping |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Poncino, Jianwen Zhu |
DynamoSim: a trace-based dynamically compiled instruction set simulator. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya |
Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Formaggio, Franco Fummi, Graziano Pravadelli |
A timing-accurate HW/SW co-simulation of an ISS with SystemC. |
CODES+ISSS |
2004 |
DBLP DOI BibTeX RDF |
co-simulation, system level modeling |
| 1 | Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr |
A novel approach for flexible and consistent ADL-driven ASIP design. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
ADL, embedded processors, ASIP |
| 1 | Franco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino |
Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Guido Post, P. K. Venkataraghavan, Tapan Ray, D. R. Seetharaman |
A SystemC-Based Verification Methodology for Complex Wireless Software IP. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jens Bieger, Sorin A. Huss, Michael Jung, Stephan Klaus, Thomas Steininger |
Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun |
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. |
SAMOS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. |
SCOPES |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Qin, Sharad Malik |
Automated synthesis of efficient binary decoders for retargetable software toolkits. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
binary decoder, decoding tree, decision tree, instruction set simulator |
| 1 | Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, Nikil D. Dutt |
An efficient retargetable framework for instruction-set simulation. |
CODES+ISSS |
2003 |
DBLP DOI BibTeX RDF |
generic instruction model, instruction binary encoding, retargetable instruction-set simulation, architecture description language, decode algorithm |
| 1 | Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt |
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
instruction abstraction, interpretive simulation, instruction set architectures, compiled simulation |
| 1 | Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt |
Profiling tools for hardware/software partitioning of embedded applications. |
LCTES |
2003 |
DBLP DOI BibTeX RDF |
loop analysis, compiler optimization, hardware/software partitioning |
| 1 | Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas |
Layered, Multi-Threaded, High-Level Performance Design. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Sayinta, Gorkem Canverdi, Marc Pauwels, Amer Alshawa, Wim Dehaene |
A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jürgen Schnerr, Gunter Haug, Wolfgang Rosenstiel |
Instruction Set Emulation for Rapid Prototyping of SoCs . |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Pedro Mindlin, José R. Brunheroto, Luiz De Rose, José E. Moreira |
Obtaining Hardware Performance Metrics for the BlueGene/L Supercomputer. |
Euro-Par |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianwen Zhu, Daniel D. Gajski |
An ultra-fast instruction set simulator. |
IEEE Trans. VLSI Syst. |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | A. Abbas, A. Ahmed, Waheed Uz Zaman Bajwa, A. Anwar, S. Abbasi |
A retargetable tool-suite for the design of application specific instruction set processors using a machine description language. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajiv A. Ravindran, Rajat Moona |
Retargetable Cache Simulation Using High Level Processor Models. |
ACSAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Joshua Redstone, Susan J. Eggers, Henry M. Levy |
An Analysis of Operating System Behavior on a Simultaneous Multithreaded Architecture. |
ASPLOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Johan Cockx |
Efficient Modeling of Preemption in a Virtual Prototype. (PDF / PS) |
IEEE International Workshop on Rapid System Prototyping |
2000 |
DBLP DOI BibTeX RDF |
Modeling, C++, Virtual Prototype, Real-Time Operating System, Preemption |
| 1 | Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong-Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung |
MetaCore: an application-specific programmable DSP development system. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-Vincentelli |
Software timing analysis using HW/SW cosimulation and instruction set simulator. |
CODES |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong-Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung |
MetaCore: An Application Specific DSP Development System. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
high-level synthesis, telecommunication |
| 1 | Clifford Liem, Marco Cornero, Miguel Santana, Pierre G. Paulin, Ahmed Amine Jerraya, Jean-Marc Gentit, Jean Lopez, Xavier Figari, Laurent Bergher |
Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio Processor. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Bengt Werner, Peter S. Magnusson |
A Hybrid Simulation Approach Enabling Performance Characterization of Large Software Systems. |
MASCOTS |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark G. Stoodley, Corinna G. Lee |
Software Pipelining Loops with Conditional Branches. |
MICRO |
1996 |
DBLP BibTeX RDF |
|
| 1 | Robert F. Cmelik, David Keppel |
Shade: A Fast Instruction-Set Simulator for Execution Profiling. |
SIGMETRICS |
1994 |
DBLP DOI BibTeX RDF |
SPARC |
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