Search results for "instruction sets"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Junichi Hirase, Shinichi Yoshimura	Faster processing for microprocessor functional ATPG.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	microprocessor functional ATPG, fault coverage improvement, short test pattern, processing speed increase, logic testing, integrated circuit testing, automatic test pattern generation, identification, test pattern generation, functional testing, microprocessor chips, instruction sets, instruction sets, microprocessor tests
2	Nathan T. Slingerland, Alan Jay Smith	Measuring the Performance of Multimedia Instruction Sets.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	VIS, MVI, multimedia, benchmarking, performance measurement, SIMD, subword parallel, MMX, SSE, AltiVec
2	Gianni Conte, Stefano Tommesani, Francesco Zanichelli	The Long And Winding Road to High-Performance Image Processing with MMX/SSE.	CAMP	2000	DBLP DOI BibTeX RDF	SIMD on registers, high-performance image processing, image processing, image processing, instruction sets, real-time image processing, multimedia processing
2	Ing-Jer Huang, Alvin M. Despain	Synthesis of application specific instruction sets.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	A. P. Wim Böhm, John R. Gurd	Iterative Instructions in the Manchester Dataflow Computer.	IEEE Trans. Parallel Distrib. Syst.	1990	DBLP DOI BibTeX RDF	Manchester Dataflow Computer, iterative instructions, program execution times, function unit array, hardware speedup curves, fine-grain instructions, parallel programming, parallel architectures, iterative methods, parallel machines, tokens, instruction sets, instruction sets, hardware configuration
2	James Leslie Keedy	An Instruction Set for Evaluating Expressions.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	stack-based instruction sets, instruction set optimization, memory-to-memory instruction sets, Code compactness, expression evaluation, instruction set design
2	Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker	Systematically derived instruction sets for high-level language support.	ACM Southeast Regional Conference	1982	DBLP DOI BibTeX RDF	directly interpretable languages, space-time efficiency, syntax and semantics, compilation, interpretation, high-level languages, semantic gap, instruction set design
1	Chen Su, Haining Fan	Impact of Intel's new instruction sets on software implementation of GF(2)[x] multiplication.	Inf. Process. Lett.	2012	DBLP DOI BibTeX RDF
1	Chen Su, Haining Fan	Impact of Intel's New Instruction Sets on Software Implementation of GF(2)[x] Multiplication.	IACR Cryptology ePrint Archive	2011	DBLP BibTeX RDF
1	Andrey Mokhov, Arseniy Alekseyev, Alex Yakovlev	Encoding of processor instruction sets with explicit concurrency control.	IET Computers & Digital Techniques	2011	DBLP DOI BibTeX RDF
1	Andrey Mokhov, Danil Sokolov, Maxim Rykunov, Alex Yakovlev	Formal modelling and transformations of processor instruction sets.	MEMOCODE	2011	DBLP DOI BibTeX RDF
1	Serge Guelton, Adrien Guinet, Ronan Keryell	Building Retargetable and Efficient Compilers for Multimedia Instruction Sets.	PACT	2011	DBLP DOI BibTeX RDF
1	Daniel McFarlin, Volodymyr Arbatov, Franz Franchetti, Markus Püschel	Automatic SIMD vectorization of fast fourier transforms for the larrabee and AVX instruction sets.	ICS	2011	DBLP DOI BibTeX RDF
1	Diego F. Aranha, Julio López, Darrel Hankerson	Efficient Software Implementation of Binary Field Arithmetic Using Vector Instruction Sets.	LATINCRYPT	2010	DBLP DOI BibTeX RDF
1	Jian Li, David Dickin, Lesley Shannon	Customizing controller instruction sets for application-specific architectures.	ASAP	2010	DBLP DOI BibTeX RDF
1	Karl Rehrl, Elisabeth Häusler, Sven Leitinger	Comparing the Effectiveness of GPS-Enhanced Voice Guidance for Pedestrians with Metric- and Landmark-Based Instruction Sets.	GIScience	2010	DBLP DOI BibTeX RDF
1	Håkon Kvale Stensland, Håvard Espeland, Carsten Griwodz, Pål Halvorsen	Tips, tricks and troubles: optimizing for cell and GPU.	NOSSDAV	2010	DBLP DOI BibTeX RDF	heterogeneous processing architectures, mjpeg, optimizations, performance, gpgpu, cell
1	Angelos D. Keromytis	Randomized Instruction Sets and Runtime Environments Past Research and Future Directions.	IEEE Security & Privacy	2009	DBLP DOI BibTeX RDF
1	Chander Sudanthi, Mrinmoy Ghosh, Kevin Welton, Nigel C. Paver	Performance analysis of compressed instruction sets on workloads targeted at mobile internet devices.	SoCC	2009	DBLP DOI BibTeX RDF
1	Hao Shen, Frédéric Pétrot	Novel task migration framework on configurable heterogeneous MPSoC platforms.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Robert D. Cameron, Dan Lin	Architectural support for SWAR text processing with parallel bit streams: the inductive doubling principle.	ASPLOS	2009	DBLP DOI BibTeX RDF	inductive doubling, parallel bit streams, swar
1	Drew Mellor, Steven P. Nicklin	A population-based approach to finding the matchset of a learning classifier system efficiently.	GECCO	2009	DBLP DOI BibTeX RDF	efficient matching, learning classifier systems, xcs, lcs
1	Jade Alglave, Anthony C. J. Fox, Samin Ishtiaq, Magnus O. Myreen, Susmit Sarkar, Peter Sewell, Francesco Zappa Nardelli	The semantics of power and ARM multiprocessor machine code.	DAMP	2009	DBLP DOI BibTeX RDF	semantics, powerpc, arm, relaxed memory models
1	Matthew D. Allen, Srinath Sridharan, Gurindar S. Sohi	Serialization sets: a dynamic dependence-based parallel execution model.	PPOPP	2009	DBLP DOI BibTeX RDF	serialization sets, parallel computing, runtime system, serializer
1	Andrew Brownfield, Cindy Norris	LC3uArch: a graphical simulator of the LC-3 microarchitecture.	SIGCSE	2009	DBLP DOI BibTeX RDF	computer architecture, computer organization
1	Andrew Baumann, Paul Barham, Pierre-Évariste Dagand, Timothy L. Harris, Rebecca Isaacs, Simon Peter, Timothy Roscoe, Adrian Schüpbach, Akhilesh Singhania	The multikernel: a new OS architecture for scalable multicore systems.	SOSP	2009	DBLP DOI BibTeX RDF	scalability, message passing, multicore processors
1	Peter Djeu, Michael Quinlan, Peter Stone	Improving particle filter performance using SSE instructions.	IROS	2009	DBLP DOI BibTeX RDF
1	Willian dos Santos Lima, Renata Spolon Lobato, Aleardo Manacero, Roberta Spolon Ulson	Towards a Java bytecodes compiler for Nios II soft-core processor.	ISCC	2009	DBLP DOI BibTeX RDF
1	Monirul I. Sharif, Andrea Lanzi, Jonathon T. Giffin, Wenke Lee	Automatic Reverse Engineering of Malware Emulators.	IEEE Symposium on Security and Privacy	2009	DBLP DOI BibTeX RDF
1	George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units.	IEEE Trans. Dependable Sec. Comput.	2009	DBLP DOI BibTeX RDF
1	Anna Inn-Tung Chen, Ming-Shing Chen, Tien-Ren Chen, Chen-Mou Cheng, Jintai Ding, Eric Li-Hsiang Kuo, Frost Yu-Shuang Lee, Bo-Yin Yang	SSE Implementation of Multivariate PKCs on Modern x86 CPUs.	CHES	2009	DBLP DOI BibTeX RDF	multivariate public key cryptosystem (MPKC), ?IC, vector instructions, SSSE3, Wiedemann, TTS, rainbow, SSE2
1	Maya B. Gokhale, Judith D. Schlesinger	Instruction Sets.	Wiley Encyclopedia of Computer Science and Engineering	2008	DBLP DOI BibTeX RDF
1	Ryan Wood, Joseph C. Libby, Kenneth B. Kent	Application Specific Instruction Sets and their Impact on the Design Space Requirements of a Hardware Java Virtual Machine.	IEEE International Workshop on Rapid System Prototyping	2008	DBLP DOI BibTeX RDF
1	Li Han, Huan-yan Qian	Parallelized Network Coding with SIMD Instruction Sets.	ISCSCT	2008	DBLP DOI BibTeX RDF
1	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	VESPA: portable, scalable, and flexible FPGA-based vector processors.	CASES	2008	DBLP DOI BibTeX RDF	SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor
1	David Ryan Koes, Seth Copen Goldstein	Near-optimal instruction selection on dags.	CGO	2008	DBLP DOI BibTeX RDF	instruction selection
1	Dietmar Ebner, Florian Brandner, Bernhard Scholz, Andreas Krall, Peter Wiedermann, Albrecht Kadlec	Generalized instruction selection using SSA-graphs.	LCTES	2008	DBLP DOI BibTeX RDF	pbqp, compiler, code generation, instruction selection
1	Alexander Yermolovich, Andreas Gal, Michael Franz	Portable execution of legacy binaries on the Java virtual machine.	PPPJ	2008	DBLP DOI BibTeX RDF	system emulation, legacy software
1	Matthias Jacob, Mariusz H. Jakubowski, Prasad Naldurg, Chit Wei Saw, Ramarathnam Venkatesan	The Superdiversifier: Peephole Individualization for Software Protection.	IWSEC	2008	DBLP DOI BibTeX RDF
1	Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Tong Chen, Tao Zhang	Supporting OpenMP on Cell.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	OpenMP, Data transfer, Heterogeneous architecture, Thread synchronization
1	Jiho Chu, Youngsun Han, Seon Wook Kim	A Dataflow Analysis for Mode Set Optimization in DSP Instruction Sets.	CIT	2007	DBLP DOI BibTeX RDF
1	Huynh Phung Huynh, Joon Edward Sim, Tulika Mitra	An efficient framework for dynamic reconfiguration of instruction-set customization.	CASES	2007	DBLP DOI BibTeX RDF	dynamic reconfiguration, instruction-set extensions, temporal partitioning, customizable processors
1	Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang 0003	EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system.	PLDI	2007	DBLP DOI BibTeX RDF	GPU, openMP, heterogeneous multi-cores
1	Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min	Selective code transformation for dual instruction set processors.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	Dual instruction set processors, mixed-width instruction set architecture, reduced bid-width instruction set architecture
1	Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsunori Kubo	Multiprocessor Simulator System Based on Multi-way Cluster Using Double-buffered Model.	AINA	2007	DBLP DOI BibTeX RDF
1	David Montgomery, Ali Akoglu	Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications.	ASAP	2007	DBLP DOI BibTeX RDF
1	Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat	FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators.	MICRO	2007	DBLP DOI BibTeX RDF
1	Holger Bock Axelsen, Robert Glück, Tetsuo Yokoyama	Reversible Machine Code and Its Abstract Processor Architecture.	CSR	2007	DBLP DOI BibTeX RDF
1	Virginia Escuder, Raúl Durán, Rafael Rico	Analysis of x86 ISA Condition Codes Influence on Superscalar Execution.	HiPC	2007	DBLP DOI BibTeX RDF	Condition codes, Graph theory, Instruction level parallelism, Instruction set architecture
1	Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Tong Chen, Tao Zhang	Supporting OpenMP on Cell.	IWOMP	2007	DBLP DOI BibTeX RDF
1	Nicolas Fritz, Philipp Lucas, Reinhard Wilhelm	Exploiting SIMD Parallelism with the CGiSCompiler Framework.	LCPC	2007	DBLP DOI BibTeX RDF
1	Peng Wu, Yuehui Chen	Grammar Guided Genetic Programming for Flexible Neural Trees Optimization.	PAKDD	2007	DBLP DOI BibTeX RDF
1	Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen	Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks.	SAMOS	2007	DBLP DOI BibTeX RDF
1	Laura Pozzi, Kubilay Atasu, Paolo Ienne	Exact and approximate algorithms for the extension of embedded processor instruction sets.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Rainer Buchty	Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
1	Robert L. Bocchino Jr., Vikram S. Adve	Vector LLVA: a virtual vector instruction set for media processing.	VEE	2006	DBLP DOI BibTeX RDF	virtual instruction sets, multimedia, SIMD, vector
1	Ahmad Zmily, Christos Kozyrakis	Simultaneously improving code size, performance, and energy in embedded processors.	DATE	2006	DBLP DOI BibTeX RDF
1	Xavier Llorà, Kumara Sastry	Fast rule matching for learning classifier systems via vector instructions.	GECCO	2006	DBLP DOI BibTeX RDF	fast rule matching, learning classifier systems, Altivec, vector operations, SSE2
1	Qingda Lu, Sriram Krishnamoorthy, P. Sadayappan	Combining analytical and empirical approaches in tuning matrix transposition.	PACT	2006	DBLP DOI BibTeX RDF	bandwidth-limited, empirical search, SIMD, tiling, spatial locality, conflict misses, matrix transposition
1	Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau	Compilation framework for code size reduction using reduced bit-width ISAs (rISAs).	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	codesize reduction, dual instruction set, narrow bit-width instruction set, rISA, register pressure-based code generation, thumb, optimization, compilers, Code generation, code compression, retargetable compilers
1	Toshio Ueshiba	An Efficient Implementation Technique of Bidirectional Matching for Real-time Trinocular Stereo Vision.	ICPR	2006	DBLP DOI BibTeX RDF
1	Kuo-Chuan Chao, Kuan-Hung Chen, Yuan-Sun Chu, Jiun-In Guo	Low-power mechanism with power block management.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Stephen Warrington, Hassan Shojania, Subramania Sudharsanan, Wai-Yip Chan	Performance improvement of the H.264/AVC deblocking filter using SIMD instructions.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Miroslav N. Velev	Formal Verification of Pipelined Microprocessors with Delayed Branches.	ISQED	2006	DBLP DOI BibTeX RDF
1	Adam J. Elbirt, Christof Paar	Efficient Implementation of Galois Field Fixed Field Constant Multiplication.	ITNG	2006	DBLP DOI BibTeX RDF	embedded systems, cryptography, block cipher, galois field
1	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	A Scalable Synthesis Methodology for Application-Specific Processors.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsunori Kubo	A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
1	Deok Jin Kim, Tae Hyung Kim, Jong Kim, Sung Je Hong	Return Address Randomization Scheme for Annuling Data-Injection Buffer Overflow Attacks.	Inscrypt	2006	DBLP DOI BibTeX RDF	Return Address, return-into-libc Attack, Data Injection Buffer Overflow Attack, Security, Randomization, Buffer Overflow, Instruction Set
1	Shengning Wu, Sikun Li	Instruction Selection for ARM/Thumb Processors Based on a Multi-objective Ant Algorithm.	CSR	2006	DBLP DOI BibTeX RDF
1	Dmitri Boulytchev	BURS-Based Instruction Set Selection.	Ershov Memorial Conference	2006	DBLP DOI BibTeX RDF
1	Angela Yun Zhu, Xi Li, Laurence Tianruo Yang, Jun Yang	A Fast Instruction Set Evaluation Method for ASIP Designs.	EUC	2006	DBLP DOI BibTeX RDF
1	Gi-Ho Park, Sung Woo Chung, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park, Shin-Dug Kim, Sung-Bae Park	Practice and Experience of an Embedded Processor Core Modeling.	HPCC	2006	DBLP DOI BibTeX RDF
1	Yuehui Chen, Lizhi Peng, Ajith Abraham	Exchange Rate Forecasting Using Flexible Neural Trees.	ISNN	2006	DBLP DOI BibTeX RDF
1	Yuehui Chen, Lizhi Peng, Ajith Abraham	Stock Index Modeling Using Hierarchical Radial Basis Function Networks.	KES	2006	DBLP DOI BibTeX RDF
1	Elena Gabriela Barrantes, David H. Ackley, Stephanie Forrest, Darko Stefanovic	Randomized instruction set emulation.	ACM Trans. Inf. Syst. Secur.	2005	DBLP DOI BibTeX RDF	Automated diversity, randomized instruction sets, software diversity
1	Xin Li, Jan Lukoschus, Marian Boldt, Michael Harder, Reinhard von Hanxleden	An Esterel processor with full preemption support and its worst case reaction time analysis.	CASES	2005	DBLP DOI BibTeX RDF	reaction time analysis, reactive processing, WCET, synchronous languages, Esterel
1	Christian Tenllado, Luis Piñuel, Manuel Prieto, Francisco Tirado, Francky Catthoor	Improving superword level parallelism support in modern compilers.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	superword level parallelism, FIR, automatic vectorization
1	Roman Bartosinski, Martin Danek, Petr Honzík, Rudolf Matousek	Dynamic reconfiguration in FPGA-based SoC designs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
1	Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers	Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.	ASAP	2005	DBLP DOI BibTeX RDF
1	Lorenz Huelsbergen	Fast evolution of custom machine representations.	Congress on Evolutionary Computation	2005	DBLP DOI BibTeX RDF
1	David Koes, Seth Copen Goldstein	A Progressive Register Allocator for Irregular Architectures.	CGO	2005	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno	Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.	DATE	2005	DBLP DOI BibTeX RDF
1	Yeong-Kang Lai, Lien-Fei Chen, Jian-Chou Chen, Chun-Wei Chiu	A two-way SIMD-based reconfigurable computing architecture for multimedia applications.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Masayuki Masuda, Kazuhito Ito	Rapid and precise instruction set evaluation for application specific processor design.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Allen C. Cheng, Gary S. Tyson	An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Low-power design, reconfigurable hardware, real-time and embedded systems, energy-aware systems, instruction set design
1	Mitsuru Matsui, Sayaka Fukuda	How to Maximize Software Performance of Symmetric Primitives on Pentium III and 4 Processors.	FSE	2005	DBLP DOI BibTeX RDF
1	Ruby B. Lee, A. Murat Fiskiran	PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	multimedia, processor architecture, instruction set architecture, media processing, ISA
1	Ben Stephenson, Wade Holst	A quantitative analysis of the performance impact of specialized bytecodes in java.	CASCON	2004	DBLP DOI BibTeX RDF	Java
1	Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran	Dual-pipeline heterogeneous ASIP design.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	dual-pipeline, instruction set generation, ASIP, superscalar
1	Daniel Citron, Gadi Haber, Roy Levin	Reducing program image size by extracting frozen code and data.	EMSOFT	2004	DBLP DOI BibTeX RDF	feedback directed, frozen code, frozen data, image size
1	Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael Thies	Feedback driven instruction-set extension.	LCTES	2004	DBLP DOI BibTeX RDF	simulator generation, encryption, network processor, codesign, instruction-set extensions, compiler generation
1	Doug Burger, Todd M. Austin, Stephen W. Keckler	Recent extensions to the SimpleScalar tool suite.	SIGMETRICS Performance Evaluation Review	2004	DBLP DOI BibTeX RDF
1	Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore	TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP.	TACO	2004	DBLP DOI BibTeX RDF	scalable and high-performance computing, Computer architecture, configurable computing
1	Vikram S. Adve, Michael Brukman, Alkis Evlogimenos, Brian Gaeke	Software Implications of Virtual Instruction Set Computers.	IPDPS Next Generation Software Program - NSFNGS - PI Workshop	2004	DBLP DOI BibTeX RDF
1	Jens Krüger, Thomas Schiwietz, Peter Kipfer, Rüdiger Westermann	Numerical Simulations on PC Graphics Hardware.	PVM/MPI	2004	DBLP DOI BibTeX RDF
1	Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min	A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor.	SCOPES	2004	DBLP DOI BibTeX RDF
1	Arvind Krishnaswamy, Rajiv Gupta	Mixed-width instruction sets.	Commun. ACM	2003	DBLP DOI BibTeX RDF
1	Gaurav S. Kc, Angelos D. Keromytis, Vassilis Prevelakis	Countering code-injection attacks with instruction-set randomization.	ACM Conference on Computer and Communications Security	2003	DBLP DOI BibTeX RDF	interpreters, emulators, buffer overflows
1	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	A Scalable Application-Specific Processor Synthesis Methodology.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Vikram S. Adve, Chris Lattner, Michael Brukman, Anand Shukla, Brian Gaeke	LLVA: A Low-level Virtual Instruction Set Architecture.	MICRO	2003	DBLP DOI BibTeX RDF