Search results for "instruction-level parallelism"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, Sarita V. Adve	The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	performance evaluation, instruction-level parallelism, Shared-memory multiprocessors, software prefetching
3	Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen	Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading.	ACM Trans. Comput. Syst.	1997	DBLP DOI BibTeX RDF	multiprocessors, multithreading, instruction-level parallelism, thread-level parallelism, simultaneous multithreading, cache interference
3	H. Tanaka	Toward more advanced usage of instruction level parallelism by a very large data path processor architecture.	ISPAN	1997	DBLP DOI BibTeX RDF	very large data path processor, instruction analysis, parallel gain, parallel architectures, microprocessor, instruction level parallelism, processor architecture, performance gain
3	Siamak Arya, Howard Sachs, Sreeram Duvvuru	An architecture for high instruction level parallelism.	HICSS	1995	DBLP DOI BibTeX RDF	high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, branches, program control structures, registers, functional units, multiple instructions, conditional execution
2	Ghassan Shobaki, Kent D. Wilken, Mark Heffernan	Optimal trace scheduling using enumeration.	TACO	2009	DBLP DOI BibTeX RDF	branch-and-bound enumeration, global instruction scheduling, optimal instruction scheduling, compiler optimizations, instruction-level parallelism, Instruction scheduling, trace scheduling
2	Weifeng Xu, Russell Tessier	Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors.	TACO	2009	DBLP DOI BibTeX RDF	Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure
2	Vladimír Guzma, Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala	Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic.	SAMOS	2008	DBLP DOI BibTeX RDF
2	Evangelia Athanasaki, Nikos Anastopoulos, Kornilios Kourtis, Nectarios Koziris	Exploring the performance limits of simultaneous multithreading for memory intensive applications.	The Journal of Supercomputing	2008	DBLP DOI BibTeX RDF	Speculative precomputation, Performance analysis, Instruction-level parallelism, Thread-level parallelism, Simultaneous multithreading, Software prefetching
2	Timothy Furtak, José Nelson Amaral, Robert Niewiadomski	Using SIMD registers and instructions to enable instruction-level parallelism in sorting algorithms.	SPAA	2007	DBLP DOI BibTeX RDF	sorting, instruction-level parallelism, SIMD, vectorization, sorting networks, quicksort
2	Weifeng Xu, Russell Tessier	Tetris: a new register pressure control technique for VLIW processors.	LCTES	2007	DBLP DOI BibTeX RDF	register pressure control, very long instruction word (VLIW) processor, instruction level parallelism
2	Philip Machanick	Design principles for a virtual multiprocessor.	SAICSIT Conf.	2007	DBLP DOI BibTeX RDF	chip multiprocessor, instruction-level parallelism
2	Andrei Terechko, Henk Corporaal	Inter-cluster communication in VLIW architectures.	TACO	2007	DBLP DOI BibTeX RDF	intercluster communication, pipelining, Instruction-level parallelism, register allocation, VLIW, instruction scheduler, optimizing compiler, clock frequency, cluster assignment
2	Eduard Ayguadé, Wolfgang Karl, Koen De Bosschere, Jean-Francois Collard	Topic 7: Parallel Computer Architecture and Instruction Level Parallelism.	Euro-Par	2006	DBLP DOI BibTeX RDF
2	Hai-Chen Wang, Chung-Kwong Yuen	Exploiting dataflow to extract Java instruction level parallelism on a tag-based multi-issue semi in-order (TMSI) processor.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Jonathan Barre, Cédric Landet, Christine Rochange, Pascal Sainrat	Modeling Instruction-Level Parallelism for WCET Evaluation.	RTCSA	2006	DBLP DOI BibTeX RDF
2	Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Superscalar Coprocessor for High-Speed Curve-Based Cryptography.	CHES	2006	DBLP DOI BibTeX RDF	curve-based cryptography, HECC, ECC, instruction-level parallelism, scalar multiplication, Superscalar, coprocessor
2	Sid Ahmed Ali Touati	Register Saturation in Instruction Level Parallelism.	International Journal of Parallel Programming	2005	DBLP DOI BibTeX RDF	Register requirement, instruction level parallelism, integer linear programming, optimizing compilation, register pressure
2	Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster	Extracting Speedup From C-Code With Poor Instruction-Level Parallelism.	IPDPS	2005	DBLP DOI BibTeX RDF
2	Kemal Ebcioglu, Wolfgang Karl, André Seznec, Marco Aldinucci	Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism.	Euro-Par	2004	DBLP DOI BibTeX RDF
2	Jan Müller, Dirk Fimmel, Renate Merker	Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling.	Interaction between Compilers and Computer Architectures	2004	DBLP DOI BibTeX RDF
2	Huibin Shi, Chris Bailey	Investigating Available Instruction Level Parallelism for Stack Based Machine Architectures.	DSD	2004	DBLP DOI BibTeX RDF
2	Noureddine Chabini, Wayne Wolf	An approach for integrating basic retiming and software pipelining.	EMSOFT	2004	DBLP DOI BibTeX RDF	embedded systems, system-on-chip, timings, instruction-level parallelism, software pipelining, VLIW, retiming, superscalar processor, peak power, code size
2	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Register Constrained Modulo Scheduling.	IEEE Trans. Parallel Distrib. Syst.	2004	DBLP DOI BibTeX RDF	Instruction level parallelism, register allocation, instruction scheduling, modulo scheduling, spill code
2	Georgi Gaydadjiev, Stamatis Vassiliadis	SCISM vs IA-64 Tagging: Differences/Code Density Effects.	Euro-Par	2004	DBLP DOI BibTeX RDF	Instruction Tagging, SCISM, Instruction Level Parallelism, IA-64
2	Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Adapting instruction level parallelism for optimizing leakage in VLIW architectures.	LCTES	2003	DBLP DOI BibTeX RDF	power supply gating, instruction level parallelism, instruction scheduling, VLIW architecture, leakage energy, functional units
2	Oleg Bessonov, Dominique Fougère, Bernard Roux	Analysis of Architecture and Design of Linear Algebra Kernels for Superscalar Processors.	PaCT	2003	DBLP DOI BibTeX RDF	linear algebra kernels, LINPACK benchmark, performance measurements, instruction level parallelism, cache memories, microarchitecture, out-of-order processors
2	Han-Saem Yun, Jihong Kim, Soo-Mook Moon	Time Optimal Software Pipelining of Loops with Control Flows.	International Journal of Parallel Programming	2003	DBLP DOI BibTeX RDF	compiler optimization, instruction-level parallelism, software pipelining, VLIW
2	Peter M. W. Knijnenburg, Toru Kisuki, Michael F. P. O'Boyle	Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation.	The Journal of Supercomputing	2003	DBLP DOI BibTeX RDF	program transformation, instruction level parallelism, program optimization, locality optimization, adaptive compilation
2	Jean-Luc Gaudiot	Parallel Computer Architecture and Instruction-Level Parallelism.	Euro-Par	2002	DBLP DOI BibTeX RDF
2	Sebastian Unger, Frank Mueller	Handling irreducible loops: optimized node splitting versus DJ-graphs.	ACM Trans. Program. Lang. Syst.	2002	DBLP DOI BibTeX RDF	irreducible flowgraphs, reducible flowgraphs, compilation, instruction-level parallelism, Code optimization, loops, control flow graphs, node splitting
2	Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec	Topic 08+13: Instruction-Level Parallelism and Computer Architecture.	Euro-Par	2001	DBLP DOI BibTeX RDF
2	Tony Werner, Venkatesh Akella	An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism.	ASYNC	2001	DBLP DOI BibTeX RDF
2	Kemal Ebcioglu, Erik R. Altman, Michael Gschwind, Sumedh W. Sathaye	Dynamic Binary Translation and Optimization.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	adaptive code generation, profile-directed feedback, very long instruction word architectures, instruction set layering, virtual machines, instruction-level parallelism, dynamic optimization, just-in-time compilation, binary translation, Dynamic compilation, instruction set architectures
2	Shyh-Kwei Chen, W. Kent Fuchs	Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures.	IEEE Trans. Parallel Distrib. Syst.	2001	DBLP DOI BibTeX RDF	compilers, Fault-tolerant computing, instruction level parallelism, VLIW architectures, instruction retry
2	Toshinori Sato, Akihiko Hamano, Kiichi Sugitani, Itsujiro Arita	Influence of Compiler Optimizations on Value Prediction.	HPCN	2001	DBLP DOI BibTeX RDF	optimization level, high-performance compilers, instruction level parallelism, value prediction, data speculation
2	Nicola Zingirian, Massimo Maresca	Selective Register Renaming: A Compiler-Driven Approach to Dynamic Register Renaming.	HPCN	2001	DBLP DOI BibTeX RDF	Dynamic Register Renaming, Instruction Level Parallelism, Register Allocation, Loop Parallelization
2	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	MIRS: Modulo Scheduling with Integrated Register Spilling.	LCPC	2001	DBLP DOI BibTeX RDF	Instruction-Level Parallelism, Register Allocation, Software Pipelining, Spill Code
2	Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith	Exploring Hypermedia Processor Design Space.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	hypermedia processor, synthesis framework, instruction-level parallelism, workload characterization
2	Toshinori Sato, Itsujiro Arita	Table size reduction for data value predictors by exploiting narrow width values.	ICS	2000	DBLP DOI BibTeX RDF	narrow width operands, instruction level parallelism, hardware implementation, value prediction, data speculation
2	Dean Batten, Sanjay Jinturkar, C. John Glossner, Michael J. Schulte, Paul D'Arcy	A New Approach to DSP Intrinsic Functions. (PDF / PS)	HICSS	2000	DBLP DOI BibTeX RDF	Speech coders, intrinsic functions, profile-directed function inlining, performance analysis, instruction-level parallelism, software pipelining, speedup, modulo scheduling, loop optimization, code growth
2	Toshinori Sato, Itsujiro Arita	Partial Resolution in Data Value Predictors. (PDF / PS)	ICPP	2000	DBLP DOI BibTeX RDF	partial resolution, tag bitwidth, instruction level parallelism, value prediction, data speculation
2	Nicola Zingirian, Massimo Maresca	Run-Time Support to Register Allocation for Loop Parallelization of Image Processing Programs.	HPCN	2000	DBLP DOI BibTeX RDF	Dynamic Register Renaming, Image Processing, Instruction Level Parallelism, Register Allocation, Loop Parallelization
2	Pierre Michaud, André Seznec, Stéphan Jourdan	Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	instruction-level parallelism, branch prediction, superscalar processors, instruction fetch
2	Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind	Execution-Based Scheduling for VLIW Architectures.	Euro-Par	1999	DBLP DOI BibTeX RDF	INSTRUCTION-LEVEL PARALLELISM, SUPERSCALAR, BINARY TRANSLATION, DYNAMIC COMPILATION
2	Timothy J. Callahan, John Wawrzynek	Instruction-Level Parallelism for Reconfigurable Computing.	FPL	1998	DBLP DOI BibTeX RDF
2	Walter Lee, Rajeev Barua, Matthew Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman P. Amarasinghe	Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine.	ASPLOS	1998	DBLP DOI BibTeX RDF
2	Narayan Ranganathan, Manoj Franklin	An Empirical Study of Decentralized ILP Execution Models.	ASPLOS	1998	DBLP DOI BibTeX RDF	execution unit dependence, hardware window, instruction-level parallelism, data dependence, dynamic scheduling, speculative execution, control dependence, decentralization
2	Allen Leung, Krishna V. Palem, Amir Pnueli	A Fast Algorithm for Scheduling Time-Constrained Instructions on Processors with ILP.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Compiler-optimizations, instruction level parallelism, instruction scheduling, embedded applications
2	Julien Zory, Fabien Coelho	Using Algebraic Transformations to Optimize Expression Evaluation in Scientific Codes.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Algebraic transformation, Fused multiply-add operation, Instruction-Level Parallelism, Expression evaluation
2	Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve	The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology.	HPCA	1997	DBLP DOI BibTeX RDF
2	Kemal Ebcioglu, Erik R. Altman	DAISY: Dynamic Compilation for 100% Architectural Compatibility.	ISCA	1997	DBLP DOI BibTeX RDF	object code compatible VLIW, instruction-level parallelism, superscalar, binary translation, dynamic compilation
2	David I. August, Wen-mei W. Hwu, Scott A. Mahlke	A Framework for Balancing Control Flow and Predication.	MICRO	1997	DBLP BibTeX RDF	conditional instructions, if-conversion, predicated instructions, program control flow, schedule time, scheduling decisions, compiler, parallel architecture, instruction-level parallelism, optimising compilers, predicated execution
2	Steve Carr, Yiping Guan	Unroll-and-Jam Using Uniformly Generated Sets.	MICRO	1997	DBLP BibTeX RDF	Instruction-Level Parallelism, Loop Optimization
2	Freddy Gabbay, Avi Mendelson	Can Program Profiling Support Value Prediction?	MICRO	1997	DBLP BibTeX RDF	instruction-level parallelism, speculative execution, Value-prediction
2	Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith	MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems.	MICRO	1997	DBLP BibTeX RDF	MediaBench, SPEC benchmark suite, benchmark suite, compilation technology, experimental measurement, general-purpose computing, general-purpose systems, inner-loops, optimization, multimedia systems, instruction-level parallelism, SIMD, VLIW, communications systems, embedded applications, microprocessor architectures
2	Heng Liao, Andrew Wolfe	Available Parallelism in Video Applications.	MICRO	1997	DBLP BibTeX RDF	MPEG1, MPEG2, SPEC benchmarks, audio applications, general-purpose applications, linear complexity global scheduling algorithm, video coding, encoders, instruction-level parallelism, decoders, optimization techniques, MPEG4, H.263, media processors, video applications, graphics applications
2	Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen	Tuning Compiler Optimizations for Simultaneous Multithreading.	MICRO	1997	DBLP BibTeX RDF	cyclic algorithm, fine-grained sharing, inter-thread instruction-level parallelism, loop-iteration scheduling, memory system resources, software speculative execution, performance, parallel programs, parallel architecture, compiler optimizations, shared-memory multiprocessors, processor architecture, instructions, simultaneous multithreading, latency hiding, loop tiling, optimising compilers, inter-processor communication, cache size
2	Gary S. Tyson, Todd M. Austin	Improving the Accuracy and Performance of Memory Communication Through Renaming.	MICRO	1997	DBLP BibTeX RDF	data fetching, data value speculation, heap segment, instruction loading, memory access latency, memory communication, memory references, memory renaming, memory segments, processor pipeline, register access techniques, stores, performance, delays, accuracy, instruction-level parallelism, execution time, storage allocation, data dependence speculation, address calculation
2	Johan Janssen, Henk Corporaal	Making Graphs Reducible with Controlled Node Splitting.	ACM Trans. Program. Lang. Syst.	1997	DBLP DOI BibTeX RDF	compilation, instruction-level parallelism, reducibility, control flow graphs, node splitting, irreducibility
2	Soo-Mook Moon, Kemal Ebcioglu	Parallelizing Nonnumerical Code with Selective Scheduling and Software Pipelining.	ACM Trans. Program. Lang. Syst.	1997	DBLP DOI BibTeX RDF	global instruction scheduling, speculative code motion, instruction-level parallelism, software pipelining, VLIW, superscalar
2	Michael J. Flynn	What's ahead in computer design?	EUROMICRO	1997	DBLP DOI BibTeX RDF	die area improvement, very high level superscalar processors, very large cache, pin bandwidth, processor complexity, scalability, multiprocessors, logic design, instruction level parallelism, VLIW, CMOS technology, lithography, cycle time, computer design, silicon area, cache size
2	Akira Koseki, Yoshiaki Fukazawa, Hideaki Komatsu	A Register Allocation Technique Using Register Existence Graph. (PDF / PS)	ICPP	1997	DBLP DOI BibTeX RDF	Instruction-Level Parallelism, Register Allocation, Program Dependence Graph, Code Scheduling
2	Krishna K. Sundararaman, Manoj Franklin	Multiscalar Execution along a Single Flow of Control. (PDF / PS)	ICPP	1997	DBLP DOI BibTeX RDF	multiple control flows, branch prediction, control dependence, instruction-level parallelism (ILP)
2	Ireneusz Karkowski, Henk Corporaal	Design of Heterogenous Multi-Processor Embedded Systems: Applying Functional Pipelining.	IEEE PACT	1997	DBLP DOI BibTeX RDF	heterogenous multiprocessor embedded system design, functional pipelining, embedded program mapping, ANSI C program, application specific processor pipeline, frequency tracking system, two-processor system, highly optimized single core solution, architecture, multiprocessing systems, instruction level parallelism, speedup, efficient algorithm, loops
2	Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte	Path Prediction for High Issue-Rate Processors.	IEEE PACT	1997	DBLP DOI BibTeX RDF	high issue-rate processors, path prediction, issue bandwidth, multiple branches, path prediction automaton, arbitrary subgraphs, scalability single access prediction, low hardware cost, instruction-level parallelism, pipeline processing, speculative execution, cycle, performance improvement
2	Antoon Bosselaers, René Govaerts, Joos Vandewalle	SHA: A Design for Parallel Architectures?	EUROCRYPT	1997	DBLP DOI BibTeX RDF	multiple-issue architectures, instruction-level parallelism, Cryptographic hash functions, critical path analysis
2	Meng-chou Chang, Feipei Lai	Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	multilevel boosting, shadow register file, conjugate register file, scheduling-conflict graph, Instruction-level parallelism, speculative execution, superscalar processors
2	Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park	Eliminating Conditional Branches for Enhancing Instruction Level Parallelism in VLIW Compiler.	ISPAN	1996	DBLP DOI BibTeX RDF	Compiler, Instruction Level Parallelism, VLIW, Superscalar, Conditional Branches
2	Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch	Accurate and Practical Profile-driven Compilation Using the Profile Buffer.	MICRO	1996	DBLP BibTeX RDF	profile buffer, superblock scheduling, profiling, compiler optimization, instruction-level parallelism
2	Richard Johnson, Michael S. Schlansker	Analysis Techniques for Predicated Code.	MICRO	1996	DBLP BibTeX RDF	boolean operand, graph-based data structure, predicated code, program analysis tools, run-time value, compiler optimization, instruction-level parallelism, data flow analysis, compiler analysis
2	Shlomit S. Pinter, Adi Yoaz	Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors.	MICRO	1996	DBLP BibTeX RDF	LRU mechanism, SPEC92 benchmark, Tango, base line architecture, hardware-based data prefetching technique, memory reference instructions, program progress graph, performance, parallel processing, instruction level parallelism, simulation results, superscalar processors, branch target buffer, instruction prefetching, hardware resources, slack time
2	Eliseu M. Chaves Filho, Edil S. Tavares Fernandes, Andrew Wolfe	Load Balancing in Superscalar Architectures.	EUROMICRO	1996	DBLP DOI BibTeX RDF	multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources
2	Manu Gulati, Nader Bagherzadeh	Performance Study of a Multithreaded Superscalar Microprocessor.	HPCA	1996	DBLP DOI BibTeX RDF	multithreading, instruction-level parallelism, Superscalars, out-of-order execution
2	Chang-Chung Liu, R.-Ming Shiu, Chung-Ping Chung	Register renaming for x86 superscalar design. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	Intel x86 superscalar design, storage conflicts, data lengths, register write, register read, hardware renaming schemes, aggressive superscalar machine model, parallel architectures, instruction level parallelism, simulation results, microprocessor chips, register renaming
2	Johan Janssen, Henk Corporaal	Controlled Node Splitting.	CC	1996	DBLP DOI BibTeX RDF	compilation, instruction level parallelism, reducibility, control flow graphs, node splitting, irreducibility
2	Jian Wang, Guang R. Gao	Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops.	CC	1996	DBLP DOI BibTeX RDF	Very Long Instruction Word(VLIW), Instruction-Level Parallelism, Software Pipelining, Superscalar, Nested Loop, Loop Scheduling, Fine-Grain Parallelism
2	Jack L. Lo, Susan J. Eggers	Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism.	PLDI	1995	DBLP DOI BibTeX RDF
2	Rainer Leupers, Peter Marwedel	Time-constrained code compaction for DSPs.	ISSS	1995	DBLP DOI BibTeX RDF	code generation techniques, digital signal processing algorithms, encoding restrictions, exact timing behavior, hard real-time constraints, integer programming model, local code compaction, programmable DSP, rigid heuristics, time-constrained code compaction, real-time systems, timing, integer programming, instruction-level parallelism, source coding, automatic programming, digital signal processing chips, side-effects
2	Roger A. Bringmann, Scott A. Mahlke, Wen-mei W. Hwu	A study of the effects of compiler-controlled speculation on instruction and data caches.	HICSS	1995	DBLP DOI BibTeX RDF	compiler-controlled speculation, nonnumeric programs, speculatively scheduled code, aggressive speculation models, scheduling, performance evaluation, parallel programming, time, instruction level parallelism, program compilers, data caches, cache storage, instruction cache, cache misses, performance results
2	William F. Richardson, Erik Brunvand	Precise exception handling for a self-timed processor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	precise exception handling, self-timed processor, multiple concurrent processes, self-timed queues, decoupled computer architectures, micropipelined processor, Fred, pipelined computer architecture, out-of-order instruction completion, parallel architectures, exception handling, instruction level parallelism, self-adjusting systems, self-timed systems
2	Michael A. Schuette, John Paul Shen	Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	control-flow monitoring, machine parallelism, idle resources, Multiflow TRACE 14/300 processor, TRACE 14/300, available resource-driven control-flow monitoring, parallel architectures, fault tolerant computing, error detection, instruction-level parallelism, concurrent error detection
2	M. Anton Ertl, Andreas Krall	Delayed Exceptions - Speculative Execution of Trapping Instructions.	CC	1994	DBLP DOI BibTeX RDF	instruction-level parallelism, software pipelining, exception, speculative execution, superscalar
2	Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker	Sentinel Scheduling for VLIW and Superscalar Processors.	ACM Trans. Comput. Syst.	1993	DBLP DOI BibTeX RDF	exception detection, exception recovery, instruction-level parallelism, instruction scheduling, speculative execution, superscalar processor, VlIW processor
2	Toshio Nakatani, Kemal Ebcioglu	Making Compaction-Based Parallelization Affordable.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	compaction-based parallelization, code explosion problem, software lookahead heuristic, VLIW parallelizing compiler, branch-intensive code, AIX utilities, fgrep, sed, parallel programming, parallel architectures, compress, program, sort, instruction-level parallelism, software pipelining, pipeline processing, instruction sets, loop parallelization, yacc
2	Norman P. Jouppi, David W. Wall	Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines.	ASPLOS	1989	DBLP DOI BibTeX RDF
1	Martin J. Johnson, Ken A. Hawick	Empirical measurement of instruction level parallelism for four generations of ARM CPUs.	PMAM	2013	DBLP DOI BibTeX RDF
1	Ping Xiang, Yi Yang, Mike Mantor, Norm Rubin, Huiyang Zhou	Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing.	PACT	2012	DBLP DOI BibTeX RDF
1	Kiyeon Lee, Moo-Kyoung Chung, Soojung Ryu, Yeon-Gon Cho, Sangyeun Cho	Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors.	ICCD	2012	DBLP DOI BibTeX RDF
1	Ben Abdallah Abderazek, Masashi Masuda, Arquimedes Canedo, Kenichi Kuroda	Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture.	The Journal of Supercomputing	2011	DBLP DOI BibTeX RDF
1		Instruction-Level Parallelism.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Stephen Somogyi, Thomas F. Wenisch, Michael Ferdman, Babak Falsafi	Spatial Memory Streaming.	J. Instruction-Level Parallelism	2011	DBLP BibTeX RDF
1	Santhosh Verma, David M. Koppelman, Lu Peng	Efficient Prefetching with Hybrid Schemes and Use of Program Feedback to Adjust Prefetcher Aggressiveness.	J. Instruction-Level Parallelism	2011	DBLP BibTeX RDF
1	Gang Liu, Zhuo Huang, Jih-Kwon Peir, Xudong Shi, Lu Peng	Enhancements for Accurate and Timely Streaming Prefetcher.	J. Instruction-Level Parallelism	2011	DBLP BibTeX RDF
1	Ahmad Sharif, Hsien-Hsin S. Lee	Data Prefetching by Exploiting Global and Local Access Patterns.	J. Instruction-Level Parallelism	2011	DBLP BibTeX RDF
1	Marius Grannæs, Magnus Jahre, Lasse Natvig	Storage Efficient Hardware Prefetching using Delta-Correlating Prediction Tables.	J. Instruction-Level Parallelism	2011	DBLP BibTeX RDF
1	Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals	Multi-level Adaptive Prefetching based on Performance Gradient Tracking.	J. Instruction-Level Parallelism	2011	DBLP BibTeX RDF
1	Martin Dimitrov, Huiyang Zhou	Combining Local and Global History for High Performance Data Prefetching.	J. Instruction-Level Parallelism	2011	DBLP BibTeX RDF
1	R. Manikantan, R. Govindarajan	Performance Oriented Prefetching Enhancements Using Commit Stalls.	J. Instruction-Level Parallelism	2011	DBLP BibTeX RDF
1	Yasuo Ishii, Mary Inaba, Kei Hiraki	Access Map Pattern Matching for High Performance Data Cache Prefetch.	J. Instruction-Level Parallelism	2011	DBLP BibTeX RDF
1	Alaa R. Alameldeen	Guest Editor's Introduction.	J. Instruction-Level Parallelism	2011	DBLP BibTeX RDF