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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 29 occurrences of 25 keywords
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Results
Found 4 publication records. Showing 4 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | C. H. Tong, Juan C. Meza, C. D. Moen |
Simulation of equipment design optimisation in microelectronics manufacturing.  |
Annual Simulation Symposium  |
1997 |
DBLP DOI BibTeX RDF |
equipment design optimisation simulation, microelectronics manufacturing, mathematical formulations, object oriented simulation environment, parametric study, short cycle time chemical vapor deposition reactor, numerical optimization problems, heat conduction, species transport simulation codes, modern optimization software, object oriented optimization environment, software architecture, optimization problems, integrated circuit manufacture |
| 1 | Prathima Agrawal, B. Narendran, Narayanan Shivakumar |
Multi-way partitioning of VLSI circuits.  |
VLSI Design  |
1996 |
DBLP DOI BibTeX RDF |
multi-way partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric |
| 1 | L. F. Fuller, C. Kraaijenvanger |
Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT.  |
Great Lakes Symposium on VLSI  |
1995 |
DBLP DOI BibTeX RDF |
educational aids, p-well CMOS gate array, student run factory, microelectronic engineering program, wafer fabrication, logic design, integrated circuit design, integrated circuit design, CMOS logic circuits, logic arrays, teaching tool, integrated circuit manufacture, integrated circuit manufacturing, electronic engineering education |
| 1 | Claude Thibeault, Yvon Savaria, Jean-Louis Houle |
A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits.  |
IEEE Trans. Computers  |
1994 |
DBLP DOI BibTeX RDF |
defect-tolerant integrated circuits, optimum number of spares, reconfiguration strategies, optimum redundancy, VLSI, logic testing, redundancy, defect tolerance, circuit reliability, yield models, integrated circuit manufacture |
Displaying result #1 - #4 of 4 (100 per page; Change: )
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