Search results for "integrated circuit testing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jason G. Brown, R. D. (Shawn) Blanton	A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	fault diagnostic accuracy, nanofabrication, regular architectures, nanoFabric, fault diagnosis, logic testing, reconfigurability, integrated circuit testing, fault coverage, nanoelectronics, high defect densities
1	Erik Larsson, Jon Persson	An Architecture for Combined Test Data Compression and Abort-on-Fail Test.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Dominik Kasprowicz, Witold A. Pleskacz	Improvement of integrated circuit testing reliability by using the defect based approach.	Microelectronics Reliability	2003	DBLP DOI BibTeX RDF
1	Laurent Bréhélin, Olivier Gascuel, Gilles Caraux	Hidden Markov Models with Patterns and Their Application to Integrated Circuit Testing.	ECML	2000	DBLP DOI BibTeX RDF
1	Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita	A high-speed IDDQ sensor implementation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit feedback, high-speed IDDQ sensor implementation, submicron CMOS process, feedback scheme, floppy-disk controller IDDQ test, current sensor, built-in sensor, 0.35 micron, 50 MHz, integrated circuit testing, CMOS digital integrated circuits, BICS, electric current measurement, electric sensing devices
1	Ameet Bagwe, Rubin A. Parekhji	Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fault coverage enhancement, embedded core based systems, test constraints, Texas Instruments TMS320C27xx, memory wrapper logic, fault diagnosis, logic testing, integrated circuit testing, application specific integrated circuits, functional testing, digital signal processing chips, fault analysis
1	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate
1	Paul Chang, Brion L. Keller, Sarala Paliwal	Effective parallel processing techniques for the generation of test data for a logic built-in self test system.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data
1	Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer	Test generation for crosstalk-induced faults: framework and computational result.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	2-vector test generation, crosstalk-induced faults, noise effects, design effort, debugging effort, pulses, signal speedup, signal slowdown, digital combinational circuits, mixed-signal test generator, XGEN, static values, dynamic signals, signal arrival times, rise times, fall times, integrated circuit testing, automatic test pattern generation, combinational circuits, accuracy, vectors, circuit analysis computing, crosstalk, transitions, integrated logic circuits, technology scaling, SPICE simulations, gate delay, circuit performance, timing information, clock frequency
1	Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer	A new framework for static timing analysis, incremental timing refinement, and timing simulation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	incremental timing refinement, signal arrival, target fault, test generation efficiency, logic testing, delays, timing, test generation, integrated circuit testing, computation, automatic test pattern generation, ATPG, static timing analysis, delay model, timing simulation
1	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
1	Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer	On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	DO-RE-ME technique, MPG-D model, defective part level prediction, benchmark circuit simulations, stuck-at fault detection tests, bridging surrogate detection, stuck-at fault coverage, predictor accuracy, industrial circuit, test pattern sequences, integrated circuit testing, automatic test pattern generation, ATPG, fault simulation, logic circuit, circuit simulation, integrated logic circuits, correlation coefficient
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
1	Said Hamdioui, A. J. van de Goor	An experimental analysis of spot defects in SRAMs: realistic fault models and tests.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	integrated circuit testing, fault models, fault coverage, SRAMs, functional fault models, SRAM chips, spot defects
1	Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda	High speed IDDQ test and its testability for process variation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	high speed IDDQ test, charge current, gate load capacitances, test input vector application, CMOS IC production, logic testing, integrated circuit testing, process variation, testability, CMOS logic circuits, production testing
1	F. Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu	DFT closure.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	area requirement, power requirement, timing closure flow, logic testing, SoC, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, ASIC, testability
1	Junichi Hirase, Shinichi Yoshimura	Faster processing for microprocessor functional ATPG.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	microprocessor functional ATPG, fault coverage improvement, short test pattern, processing speed increase, logic testing, integrated circuit testing, automatic test pattern generation, identification, test pattern generation, functional testing, microprocessor chips, instruction sets, instruction sets, microprocessor tests
1	Andrzej Hlawiczka, Michal Kopec	Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	serial seeding, linear hybrid cellular automata, n-cell CA register, p CdSR registers, cellular automata quasi shift register, PCASR, n-bit input sequence, logic testing, cellular automata, integrated circuit testing, automatic test pattern generation, application specific integrated circuits, polynomials, polynomial, logic CAD, cost, TPG, flip-flops, flip-flops, shift registers, pattern generators, integrated circuit economics
1	Der-Cheng Huang, Wen-Ben Jone	An efficient parallel transparent diagnostic BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	parallel transparent diagnostic BIST, built-in self-diagnosis method, multiple embedded memory arrays, transparent diagnostic interface, redundant read/write/shift operations, march algorithm, TDiagRSMarch algorithm, low hardware overhead, test time reduction, diagnostic efficiency, parallel algorithms, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic testing, test coverage, integrated memory circuits
1	Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu	An FPGA-based re-configurable functional tester for memory chips.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	re-configurable tester, memory chips, re-configurable hardware platform, prototype tester, compiler, integrated circuit testing, reconfigurable architectures, integrated memory circuits
1	Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José L. Huertas	Testing mixed-signal cores: practical oscillation-based test in an analog macrocell.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	analog macrocell, mixed signal integrated circuit, OBT, mixed-signal macrocell, integrated circuit testing, mixed analogue-digital integrated circuits, oscillation-based test
1	Chin-Te Kao, Sam Wu, Jwu E. Chen	A case study of failure analysis and guardband determination for a 64M-bit DRAM.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	guardband determination, prevention strategy, test derivation, test cost, 64 Mbit, integrated circuit testing, yield, DRAM, failure analysis, failure analysis, test selection, DRAM chips, product quality, integrated circuit yield, integrated circuit economics
1	Arabi Keshk, Yukiya Miura, Kozo Kinoshita	Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit oscillations, transistor level networks, feedback oscillation, Byzantine General's problems, logic threshold, logic testing, logic testing, integrated circuit testing, fault coverage, fault location, bridging fault, CMOS circuits, CMOS digital integrated circuits, test vector
1	Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou	etection of SRAM cell stability by lowering array supply voltage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cell stability detection, array supply voltage reduction, design-for-test technique, static random access memory, memory array, test mode, detection capability, logic testing, integrated circuit testing, design for testability, CMOS technology, SRAM chips, CMOS memory circuits, DFT technique, circuit stability, 0.18 micron
1	Kuen-Jong Lee, Cheng-I. Huang	A hierarchical test control architecture for core based design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	hierarchical test control architecture, SOC design, IEEE P1500 Working Group, test standard, IEEE 1149.1 cores, parallel testing capabilities, hierarchical test control mechanism, deeply embedded cores, hierarchical test access, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, IEEE standards, test architecture, core based design
1	Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen	Peak-power reduction for multiple-scan circuits during test application.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
1	Michael J. Liebelt, Cheng-Chew Lim	A method for determining whether asynchronous circuits are self-checking.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise
1	S. L. Lin, S. Mourad, S. Krishnan	A BIST methodology for at-speed testing of data communications transceivers.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	data communication equipment, telecommunication equipment testing, BIST methodology, data communications transceivers, data communications chip, 3-port IEEE 1394a system, CMOS implementation, 0.35 micron, 400 Mbit/s, built-in self test, integrated circuit testing, automatic testing, functional testing, CMOS integrated circuits, at-speed testing, transceivers
1	Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen	Is IDDQ testing not applicable for deep submicron VLSI in year 2011?	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	deep submicron VLSI, IDDQ current estimation, random process deviations, IDDQ distributions, VLSI, statistical analysis, integrated circuit testing, CMOS integrated circuits, leakage currents, IDDQ testing, statistical approach, standard deviation, input vectors, circuit size
1	Eric MacDonald, Nur A. Touba	Testing domino circuits in SOI technology.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	silicon-on-insulator, SOI technology, dynamic circuit styles, fault modeling analysis, overall fault coverage, parasitic bipolar leakage, CMOS logic, logic testing, integrated circuit testing, automatic testing, fault simulation, CMOS logic circuits, leakage currents, domino circuits
1	Toshiyuki Maeda, Kozo Kinoshita	Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
1	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
1	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	distribution-graph based approach, extended tree growing technique, power-constrained block-test scheduling, unequal-length block-test scheduling, power dissipation constraints, test concurrency, assigned power dissipation limits, balanced test power dissipation, least mean square error function, global priority function, system-level test scheduling algorithm, scheduling, VLSI, fault diagnosis, logic testing, high level synthesis, integrated circuit testing, automatic test pattern generation, trees (mathematics), least mean squares methods
1	Stanislav Polonsky, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Pia Sanda	Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	imaging circuit analysis, IBM G6 microprocessor, non-invasive backside timing, Picosecond Imaging Circuit Analysis, waveform extraction, integrated circuit testing, timing analysis, race condition, circuit switching, integrated memory circuits, hazards and race conditions, L1 cache
1	Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	TOF: a tool for test pattern generation optimization of an FPGA application oriented test.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG
1	Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu	High-speed generation of LFSR signatures.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	high-speed generation, LFSR signatures, compaction simulation, single-input signature register, equivalent multiple-input implementation, finite field theory, high-speed signature computations, lookahead technique, internal-XOR LFSR, external-XOR LFSR, performance evaluation, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, BIST, linear feedback shift register, binary sequences, subsequences
1	Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi	Cyclic greedy generation method for limited number of IDDQ tests.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	cyclic greedy generation method, undetected faults, ISCAS85Y circuits, short circuit faults, fault diagnosis, integrated circuit testing, iterative methods, iterative method, CMOS integrated circuits, IDDQ tests, test patterns, CMOS IC, electric current measurement, cyclic, random patterns
1	Wei-Lun Wang, Kuen-Jong Lee	Accelerated test pattern generators for mixed-mode BIST environments.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
1	Wen-Jer Wu, Chuan Yi Tang	Memory test time reduction by interconnecting test items.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	memory test time reduction, test items interconnection, initialization sequences, verification sequences, signal settling time, interconnection problem, rural Chinese postman problem, integer linear programming model, successive ILP models, graph theory, constraints, linear programming, integrated circuit testing, integer programming, iterations, NP-hard problem, integrated memory circuits
1	Shiyi Xu, Wei Cen	Forecasting the efficiency of test generation algorithms for digital circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
1	Abdelhakim Khouas, Anne Derieux	Fault Simulation for Analog Circuits Under Parameter Variations.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	test optimisation, fault simulation, analog testing
1	Sreejit Chakravarty	On the capability of delay tests to detect bridges and opens.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	defective IC, faulty dynamic logic behavior, transition tests, simulation, integrated circuit testing, delay tests, bridges, opens, at-speed testing, path delay tests
1	Vinay Dabholkar, Sreejit Chakravarty	Computing stress tests for interconnect defects.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	interconnect defects, reliability screens, infant mortality, gate-oxide defects, integrated circuit testing, stress tests
1	Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault	Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	defect-tolerant circuit, contamination, wafer test, silicon chip, reconfiguration, redundancy, integrated circuit testing, manufacturing, yield, cost model, integrated circuit, figure of merit, fault tolerant circuit
1	Vladimir Székely, Márta Rencz, Bernard Courtois	Integrating on-chip temperature sensors into DfT schemes and BIST architectures.	VTS	1997	DBLP DOI BibTeX RDF	on-chip low-power small-area CMOS temperature sensor, DfTT, design for thermal testability, safety-critical circuit, integrated circuit testing, BIST, CMOS integrated circuits
1	Ulrich Rembold, Sergej Fatikow	Autonomous Microrobots.	Journal of Intelligent and Robotic Systems	1997	DBLP DOI BibTeX RDF	autonomous microrobots, microassembly station, robot control, piezoelectric actuators, micromanipulator
1	James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan	Digital Integrated Circuit Testing using Transient Signal Analysis.	ITC	1996	DBLP DOI BibTeX RDF
1	Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi	Low-cost DC built-in self-test of linear analog circuits using checksums.	VLSI Design	1996	DBLP DOI BibTeX RDF	DC built-in self-test, catastrophic failures, line opens, DC transfer function, on-chip fault detection, BIST circuitry, fault diagnosis, built-in self test, integrated circuit testing, transfer functions, analogue integrated circuits, checksums, linear analog circuits, matrix representations, fault classes
1	Sunil R. Das, N. Goel, Wen-Ben Jone, Amiya R. Nayak	Syndrome signature in output compaction for VLSI BIST.	VLSI Design	1996	DBLP DOI BibTeX RDF	syndrome signature, output compaction, VLSI BIST, input patterns, n-input combinational circuit, primary syndrome, subsyndromes, subfunctions, single-output circuit, multiple output, VLSI, logic testing, data compression, built-in self test, integrated circuit testing, combinational circuits, switching functions, exhaustive testing
1	S. Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri	Programmable cellular automata based testbed for fault diagnosis in VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	programmable cellular automata, polynomial algebraic tools, faulty signatures, multiple attractor, fault dictionary size, cascadable structure, VLSI, fault diagnosis, fault diagnosis, logic testing, partitions, cellular automata, integrated circuit testing, automatic testing, VLSI circuits, logic partitioning, signature analyzer
1	Rajesh Ramadoss, Michael L. Bushnell	Test generation for mixed-signal devices using signal flow graphs.	VLSI Design	1996	DBLP DOI BibTeX RDF	mixed-signal devices, reverse simulation approach, component tolerances, analog input sinusoids, test generation results, analog backtrace method, high-order analog circuits, fault diagnosis, test generation, integrated circuit testing, automatic testing, circuit analysis computing, mixed analogue-digital integrated circuits, signal flow graphs, signal flow graphs, nonlinear circuits
1	Mukund Sivaraman, Andrzej J. Strojwas	Diagnosis of parametric path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing
1	Karim Arabi, Bozena Kaminska	Oscillation-test strategy for analog and mixed-signal integrated circuits.	VTS	1996	DBLP DOI BibTeX RDF	circuit oscillations, oscillation test strategy, analog ICs, low-cost test method, oscillation frequency deviation, wafer-probe testing, final production testing, ASIC testing, integrated circuit testing, operational amplifiers, analogue integrated circuits, mixed analogue-digital integrated circuits, production testing, analogue-digital conversion, mixed-signal ICs
1	Stephan P. Athan, David L. Landis, Sami A. Al-Arian	A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs.	VTS	1996	DBLP DOI BibTeX RDF	deep submicron CMOS ICs, fault diagnosability, ULSI CMOS, fault diagnosis, integrated circuit testing, fault detectability, CMOS integrated circuits, leakage currents, built-in current sensor, I/sub DDQ/ testing, electric current measurement, ULSI, electric sensing devices
1	Hari Balachandran, D. M. H. Walker	Improvement of SRAM-based failure analysis using calibrated Iddq testing.	VTS	1996	DBLP DOI BibTeX RDF	defect-bitmap dictionary, voltage testing, microprocessor cache memory, integrated circuit testing, calibration, calibration, SRAM, cache storage, failure analysis, failure analysis, IDDQ testing, current testing, defect classification, SRAM chips, integrated circuit yield, integrated circuit yield
1	Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Scan insertion criteria for low design impact.	VTS	1996	DBLP DOI BibTeX RDF	scan insertion criteria, design impact, flip-flop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flip-flops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan
1	Subhrajit Bhattacharya, Sujit Dey	H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads.	VTS	1996	DBLP DOI BibTeX RDF	H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology
1	R. D. (Shawn) Blanton, John P. Hayes	Design of a fast, easily testable ALU.	VTS	1996	DBLP DOI BibTeX RDF	ALU, adder design, L-testable design, level-testable, carry-lookahead addition, fault diagnosis, logic testing, integrated circuit testing, automatic testing, digital arithmetic, integrated circuit design, adders, logic arrays, test patterns, area overhead, functional faults, carry logic, arithmetic-logic unit, 8 bit
1	Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs	Full fault dictionary storage based on labeled tree encoding.	VTS	1996	DBLP DOI BibTeX RDF	digital storage, full fault dictionary storage, labeled tree encoding, fault dictionary compaction, binary string code, implicit storage, VLSI, fault diagnosis, logic testing, integrated circuit testing, encoding, automatic testing, circuit analysis computing, fault trees
1	Sreejit Chakravarty	A sampling technique for diagnostic fault simulation.	VTS	1996	DBLP DOI BibTeX RDF	diagnostic fault simulation, diagnostic test sets, EC/IC Sampling, indistinguishable classes, approximation algorithm, fault diagnosis, integrated circuit testing, circuit analysis computing, set theory, equivalence classes, equivalence classes, sampling technique
1	Jonathan T.-Y. Chang, Edward J. McCluskey	Quantitative analysis of very-low-voltage testing.	VTS	1996	DBLP DOI BibTeX RDF	very-low-voltage testing, static CMOS chips, supply voltage, rated conditions, early-life failures, test conditions, test speed, VLSI, VLSI, integrated circuit testing, CMOS integrated circuits, failure analysis, quantitative analysis, threshold voltage, integrated circuit noise
1	Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham	Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages.	VTS	1996	DBLP DOI BibTeX RDF	waveform analysis, nonrobust tests, stuck-fault detection, signal waveform analysis, signal waveform integration, directed random test generation techniques, fault diagnosis, logic testing, redundancy, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, detectability, fault coverage, test application time, redundant faults
1	S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	A new test pattern generation method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits
1	T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael	Faulty chip identification in a multi chip module system.	VTS	1996	DBLP DOI BibTeX RDF	faulty chip identification, multi chip module, linear space compressor, field programmable gate array, fault diagnosis, data compression, data compression, built-in self test, built-in self test, integrated circuit testing, fault detection, comparator, multichip modules
1	Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya	Isomorph-redundancy in sequential circuits.	VTS	1996	DBLP DOI BibTeX RDF	isomorph-redundancy, reduced sequential machine, infinite family, VLSI, logic testing, redundancy, integrated circuit testing, design for testability, logic design, sequential circuits, sequential circuits, DFT, state diagram
1	Jean-Luis Dufour	Safety computations in integrated circuits.	VTS	1996	DBLP DOI BibTeX RDF	safety computations, software-based railway control systems, MATRA TRANSPORT, signature checking, coded processor, reliability, fault tolerant computing, logic testing, redundancy, integrated circuit testing, error correction codes, automatic testing, application specific integrated circuits, ASICs, integrated circuits, coprocessors, arithmetic coding, integrated circuit reliability
1	Mehdi Ehsanian, Bozena Kaminska, Karim Arabi	A new digital test approach for analog-to-digital converter testing.	VTS	1996	DBLP DOI BibTeX RDF	digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion
1	Eric Felt, Alberto L. Sangiovanni-Vincentelli	Optimization of analog IC test structures.	VTS	1996	DBLP DOI BibTeX RDF	integrated circuit measurement, analog IC test structures, circuit parameters, statistical analysis, integrated circuit testing, accuracy, circuit optimisation, design of experiments, design of experiments, analogue integrated circuits, statistical techniques, network parameters, integrated circuit noise, measurement noise
1	Antoni Ferré, Joan Figueras	On estimating bounds of the quiescent current for I/sub DDQ/ testin.	VTS	1996	DBLP DOI BibTeX RDF	quiescent current bounds, sensing circuitry design, VLSI, logic testing, integrated circuit testing, ATPG, automatic testing, CMOS integrated circuits, leakage currents, I/sub DDQ/ testing, CMOS ICs, hierarchical approach
1	Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis	An asynchronous totally self-checking two-rail code error indicator.	VTS	1996	DBLP DOI BibTeX RDF	asynchronous TSC error indicator, totally self-checking error indicator, concurrent detection, two-rail code error indicator, CMOS implementation, VLSI, logic testing, delays, integrated circuit testing, error detection, automatic testing, asynchronous circuits, CMOS logic circuits, delay faults
1	Anne E. Gattiker, Wojciech Maly	Current signatures [VLSI circuit testing].	VTS	1996	DBLP DOI BibTeX RDF	VLSI circuit testing, current signature, passive defects, active defects, VLSI, integrated circuit testing, CMOS integrated circuits, I/sub DDQ/ testing
1	A. J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik	March LR: a test for realistic linked faults. (PDF / PS)	VTS	1996	DBLP DOI BibTeX RDF	disturb faults, March LR, March LRD, March LRDD, fault diagnosis, integrated circuit testing, fault models, fault coverage, march tests, integrated memory circuits, semiconductor memories, linked faults
1	Steven S. Gorshe, Bella Bose	A self-checking ALU design with efficient codes.	VTS	1996	DBLP DOI BibTeX RDF	self-checking ALU design, self-testing ALU, VLSI, logic testing, built-in self test, integrated circuit testing, logic design, error detection codes, error detecting codes, integrated logic circuits, unidirectional errors
1	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Segment delay faults: a new fault model.	VTS	1996	DBLP DOI BibTeX RDF	segment delay faults, delay defect, distributed defect, rising transitions, falling transitions, transition tests, nonrobust tests, VLSI, fault diagnosis, logic testing, delays, integrated circuit testing, fault model, automatic testing, circuit analysis computing, robust tests, integrated circuit modelling, production testing, spot defect, manufacturing defects
1	Wei-Kang Huang, Fabrizio Lombardi	An approach for testing programmable/configurable field programmable gate arrays.	VTS	1996	DBLP DOI BibTeX RDF	behavioral characterization, single fault detection, disjoint one-dimensional arrays, unilateral horizontal connections, common vertical input lines, array testing, logic blocks, field programmable gate arrays, field programmable gate arrays, VLSI, logic testing, integrated circuit testing, stuck-at fault, FPGA testing, functional fault, hybrid fault model
1	Dimitrios Kagaris, Spyros Tragoudas	Generating deterministic unordered test patterns with counters.	VTS	1996	DBLP DOI BibTeX RDF	counting circuits, deterministic unordered test patterns, counter-based schemes, built-in mechanisms, test pattern generation session, ISCAS'85 benchmarks, logic testing, built-in self test, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, hardware overhead
1	Jitendra Khare, Wojciech Maly, Nathan Tiday	Fault characterization of standard cell libraries using inductive contamination.	VTS	1996	DBLP DOI BibTeX RDF	surface contamination, fault characterization, standard cell libraries, inductive contamination analysis, contamination diagnosis, gate-level delay characterization, fault diagnosis, test generation, integrated circuit testing, cellular arrays, defect coverage
1	Bruce C. Kim, Abhijit Chatterjee, Madhavan Swaminathan	Low-cost diagnosis of defects in MCM substrate interconnections.	VTS	1996	DBLP DOI BibTeX RDF	low-cost diagnosis, MCM substrate interconnections, substrate interconnect defects, defect location, defect size, fault diagnosis, integrated circuit testing, fault location, multichip modules, integrated circuit interconnections, fault-dictionary, substrates
1	Robert H. Klenke, James H. Aylor, Joseph M. Wolf	An analysis of fault partitioning algorithms for fault partitioned ATPG.	VTS	1996	DBLP DOI BibTeX RDF	fault partitioning algorithm, VLSI device, detected fault broadcasting, preprocessing time, parallel processing, parallel processing, VLSI, fault diagnosis, integrated circuit testing, ATPG, automatic testing, dynamic load balancing, NP complete problem, digital system, test vector generation
1	M. P. Kluth, François Simon, Jean-Yves Le Gall, E. Müller	Design of a fault tolerant 100 Gbits solid-state mass memory for satellite.	VTS	1996	DBLP DOI BibTeX RDF	semiconductor storage, fault tolerant solid-state mass memory, satellite applications, VLSI components, 100 Gbit, VLSI, testing, fault tolerant computing, integrated circuit testing, error detection, error detection, special purpose computers, aerospace computing, space applications
1	Haluk Konuk, F. Joel Ferguson	An unexpected factor in testing for CMOS opens: the die surface.	VTS	1996	DBLP DOI BibTeX RDF	surface phenomena, electric charge, CMOS opens, die surface, RC interconnect, HSPICE simulations, trapped charge, floating gates, VLSI, integrated circuit testing, CMOS integrated circuits, integrated circuit modelling, circuit model
1	Vladimir A. Koval, Dmytro V. Fedasyuk	The MCM's thermal testing.	VTS	1996	DBLP DOI BibTeX RDF	thermal field, heat exchange, multilevel rectangular parallelepiped, MONSTR-M system, simulation, model, design, testing, integrated circuit testing, multichip modules, integrated circuit modelling, MCM, heat transfer, structure decomposition
1	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.	VTS	1996	DBLP DOI BibTeX RDF	GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm
1	Yuyun Liao, D. M. H. Walker	Optimal voltage testing for physically-based faults.	VTS	1996	DBLP DOI BibTeX RDF	optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise
1	Cecilia Metra, Michele Favalli, Bruno Riccò	Embedded two-rail checkers with on-line testing ability.	VTS	1996	DBLP DOI BibTeX RDF	embedded two-rail checkers, online testing ability, self-testing ability, compact structure, VLSI, logic testing, integrated circuit testing, design for testability, error detection, automatic testing, integrated logic circuits, two-rail code
1	M. Miegler, Werner Wolz	Development of test programs in a virtual test environment.	VTS	1996	DBLP DOI BibTeX RDF	test programs development, virtual test environment, quality-assured mixed-signal test programs, standard test description language, VTML, Virtual Test Modelling Language, standardized description models, test system resources, equivalent simulation models, VLSI, integrated circuit testing, design for testability, integrated circuit design, circuit CAD, automatic test software
1	F. Mohamed, M. Manzouki, Anton Biasizzo, Franc Novak	Analog circuit simulation and troubleshooting with FLAMES.	VTS	1996	DBLP DOI BibTeX RDF	analog circuit simulation, model-based expert system, VLSI, fuzzy logic, fuzzy logic, integrated circuit testing, circuit analysis computing, analogue integrated circuits, troubleshooting, FLAMES, diagnostic expert systems
1	Fidel Muradali, Janusz Rajski	A self-driven test structure for pseudorandom testing of non-scan sequential circuits.	VTS	1996	DBLP DOI BibTeX RDF	self-driven test structure, primary inputs, nonscan sequential circuits, test point structure, parallel pseudorandom test patterns, test mode flag, stuck-at fault coverage, ISCAS-89 benchmarks, logic testing, built-in self test, integrated circuit testing, design for testability, sequential circuits, BIST, automatic testing, circuit under test
1	Robert B. Norwood, Edward J. McCluskey	Synthesis-for-scan and scan chain ordering.	VTS	1996	DBLP DOI BibTeX RDF	synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
1	Chen-Yang Pan, Kwang-Ting Cheng	Implicit functional testing for analog circuits.	VTS	1996	DBLP DOI BibTeX RDF	implicit functional testing, linear time-invariant circuits, impulse response samples, pseudo-random technique, production testing time, yield coverages, VLSI, integrated circuit testing, fault coverage, analog circuits, analogue integrated circuits, mixed analogue-digital integrated circuits, transient response
1	Theo J. Powell	Consistently dominant fault model for tristate buffer nets.	VTS	1996	DBLP DOI BibTeX RDF	buffer circuits, consistently dominant fault model, tristate buffer nets, floating type faults, contention type faults, MISR signature loss, test pattern compression, VLSI, fault diagnosis, logic testing, integrated circuit testing, fault detection, fault location, integrated logic circuits, multivalued logic circuits, ternary logic, stuck faults
1	Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara	On the effects of test compaction on defect coverage.	VTS	1996	DBLP DOI BibTeX RDF	surrogate faults, fault diagnosis, test generation, integrated circuit testing, fault modeling, test sets, test compaction, defect coverage
1	Michel Renovell, Florence Azaïs, Yves Bertrand	The multi-configuration: A DFT technique for analog circuits.	VTS	1996	DBLP DOI BibTeX RDF	multi-configuration technique, diagnosis facilities, 8/sup th/ order band pass filter, integrated circuit testing, design for testability, integrated circuit design, analog circuits, analogue integrated circuits, band-pass filters, DFT technique
1	Michel Renovell, P. Huc, Yves Bertrand	Bridging fault coverage improvement by power supply control.	VTS	1996	DBLP DOI BibTeX RDF	bridging fault coverage, power supply control, resistance interval, faulty value, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, logic circuits, parametric model, benchmark circuits
1	Masaru Sanada	A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq.	VTS	1996	DBLP DOI BibTeX RDF	CAD-based failure diagnosis technology, CMOS LSI, abnormal Iddq phenomenon, physical damage detection, faulty blocks, failure point localization, Iddq test patterns, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, circuit CAD, large scale integration
1	Vl. V. Saposhnikov, Alexej Dmitriev, Michael Gössel, V. V. Saposhnikov	Self-dual parity checking-A new method for on-line testing.	VTS	1996	DBLP DOI BibTeX RDF	self-dual parity checking, self-dual complement, VLSI, logic testing, Boolean functions, Boolean function, integrated circuit testing, automatic testing, fault coverage, integrated logic circuits, online testing, error checking
1	John W. Sheppard, William R. Simpson	Improving the accuracy of diagnostics provided by fault dictionaries.	VTS	1996	DBLP DOI BibTeX RDF	diagnostics accuracy improvement, digital circuit diagnosis, information flow model, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, circuit analysis computing, digital integrated circuits, fault dictionaries, nearest neighbor classification
1	Mukund Sivaraman, Andrzej J. Strojwas	A diagnosability metric for parametric path delay faults.	VTS	1996	DBLP DOI BibTeX RDF	diagnosability metric, parametric path delay faults, test vector pairs, chip failure, fabrication process parameter variations, diagnosis framework, ISCAS'89 benchmark circuits, VLSI, fault diagnosis, logic testing, delays, timing, integrated circuit testing, failure analysis, diagnosability, delay fault testing, test set
1	Egor S. Sogomonyan, Michael Gössel	Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems.	VTS	1996	DBLP DOI BibTeX RDF	circuit feedback, concurrently self-testing embedded checker, ultra-reliable fault-tolerant system, parity codes, design, monitoring, built-in self test, integrated circuit testing, linear feedback shift register, error detection codes, error detection code, shift registers, arithmetic codes, Berger codes, duplication codes, integrated circuit reliability, corrector
1	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists