Search results for "inter-processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Hea-Sook Park, Sung-Jin Moon, Man-Sik Park, Boseob Kwon, Kwang-Suk Song	Design of inter processor communication controller using ATM switch and analysis of its optimal message length considering retransmission.	RTCSA	1997	DBLP DOI BibTeX RDF	inter processor communication controller, optimal message length, distributed large-scale multiprocessors, ATM adaptation layer, message error rate, message retransmission rate, asynchronous transfer mode, ATM switch, asynchronous transfer mode switches
3	Sekhar R. Sarukkai, Jerry C. Yan, Melisa Schmidt	Automated instrumentation and monitoring of data movement in parallel programs. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	data-structure alignments, inter-processor data-structure interactions, compiler front end tools, tracking data-structure movements, NAS benchmarks, parallel programming, parallel programs, data structures, message passing, data flow analysis, software performance evaluation, program diagnostics, performance tools, message passing programs, inter-processor communications, data movement
2	Mahmut T. Kandemir, Yuanrui Zhang, Sai Prashanth Muralidhara, Ozcan Ozturk, Sri Hari Krishna Narayanan	Slicing based code parallelization for minimizing inter-processor communication.	CASES	2009	DBLP DOI BibTeX RDF	automatic code parallelization, code analysis and optimization, iteration space slicing, parallelizing compilers
2	Frank E. B. Ophelders, Samarjit Chakraborty, Henk Corporaal	Intra- and inter-processor hybrid performance modeling for MPSoC architectures.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	simulation, performance analysis, system-on-chip
2	Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin	Adaptive set pinning: managing shared caches in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	inter-processor, intra-processor, set pinning, CMP, shared cache
2	Guilin Chen, Mahmut T. Kandemir	An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors.	T. HiPEAC	2007	DBLP DOI BibTeX RDF
2	Eryk Laskowski, Marek Tudruj	Inter-processor Communication Optimization in Dynamically Reconfigurable Embedded Parallel Systems.	PPAM	2007	DBLP DOI BibTeX RDF
2	Syed Misbahuddin, Nizar Al-Holou	Improving Inter-processor Data Transfer Rates over Industrial Networks.	AICCSA	2007	DBLP DOI BibTeX RDF
2	Eryk Laskowski, Marek Tudruj	Efficient Parallel Embedded Computing through Look-Ahead Configured Dynamic Inter-Processor Connections.	PARELEC	2006	DBLP DOI BibTeX RDF
2	Eryk Laskowski, Marek Tudruj	Assessment of Dynamic Look-Ahead Inter-Processor Connection Reconfiguration for Different Control Paradigms.	ISPDC	2006	DBLP DOI BibTeX RDF
2	Guilin Chen, Mahmut T. Kandemir	Optimizing inter-processor data locality on embedded chip multiprocessors.	EMSOFT	2005	DBLP DOI BibTeX RDF	chip multiprocessors, data locality, stencil computation
2	Eunseuk Oh, Hongsik Choi, David Primeaux	An All-Reduce Operation in Star Networks Using All-to-All Broadcast Communication Pattern.	International Conference on Computational Science	2005	DBLP DOI BibTeX RDF	all-reduce, distributed memory parallel computing systems, all-to-all broadcast, star network, inter-processor communication
2	Jih-Fu Tu, Chih-Yung Chen	An Effective Bus-Band Arbiter for Processors Communication.	AINA	2004	DBLP DOI BibTeX RDF	Bus-based arbitration circuit, multistage bus network (MBN), M-to-B Arbiter and inter-processor communication
2	Eryk Laskowski, Marek Tudruj	Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches.	FPL	2003	DBLP DOI BibTeX RDF
2	Marek Tudruj	Embedded Cluster Computing through Dynamic Reconfigurability of Inter-Processor Connections.	IWCC	2001	DBLP DOI BibTeX RDF
2	Mark D. Hill	How computer architecture trends may affect future distributed systems: from infiniBand clusters to inter-processor speculation (abstract).	PODC	2000	DBLP DOI BibTeX RDF
2	Ken'ichirou Kimura, Hirofumi Amano, Akifumi Makinouchi	Dynamic Performance Optimization Mechanism for Parallel Object-Oriented Database Programming Languages. (PDF / PS)	IDEAS	2000	DBLP DOI BibTeX RDF	dynamic performance optimization, parallel object-oriented database programming languages, distributed-memory parallel processor, remote object referencing, biased distribution, object relocation, simulation tests, topology, parallel languages, performance degradation, inter-processor communication, load imbalance, object allocation
2	Yongwha Chung, Jin-Won Park	Solving Irregular Inter-processor Data Dependency in Image Understanding Tasks.	ACPC	1999	DBLP DOI BibTeX RDF
2	Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen	Tuning Compiler Optimizations for Simultaneous Multithreading.	MICRO	1997	DBLP BibTeX RDF	cyclic algorithm, fine-grained sharing, inter-thread instruction-level parallelism, loop-iteration scheduling, memory system resources, software speculative execution, performance, parallel programs, parallel architecture, compiler optimizations, shared-memory multiprocessors, processor architecture, instructions, simultaneous multithreading, latency hiding, loop tiling, optimising compilers, inter-processor communication, cache size
2	Hea-Sook Park, Sung-Jin Moon, Mee-Hye Lee, Kwang-Suk Song	The design and comparison of two IPC control methods in an ATM switching control system.	RTCSA	1996	DBLP DOI BibTeX RDF	IPC control methods, ATM switching control system, inter-processor communication control, asynchronous transfer mode switching system, indirect control method, local software, direct memory access, main control software, asynchronous transfer mode, local memory
2	Ben Lee, Chae Shin, Ali R. Hurson	A strategy for scheduling partially ordered program graphs onto multicomputers.	HICSS	1995	DBLP DOI BibTeX RDF	partially ordered program graphs, scalar performance, user code, compile-time scheduling heuristic, SISAL programs, scheduling, performance evaluation, scalability, parallel programming, message passing, reconfigurable architectures, program compilers, processor scheduling, multicomputers, communication overhead, simulation studies, BLAS, massively parallel processing, message-passing programming, inter-processor communication, message-passing multicomputers
2	Hatem Sellami, Sudhakar Yalamanchili	Time scale combining of conservative parallel discrete event simulations. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	time scale combining, inter-processor communication messages, distinct simulations, simulation trials, parallel processing, parallel architectures, discrete event simulation, discrete event simulations, parallel discrete event simulations
2	Ken-ichiro Murakami	A Pseudo Network Approach to Inter-processor Communication on a Shared-memory Multi-processor MacELIS.	Workshop on Parallel Lisp	1989	DBLP DOI BibTeX RDF
1	Stamatis G. Kavadias, Manolis Katevenis, Michail Zampetakis, Dimitrios S. Nikolopoulos	On-chip communication and synchronization mechanisms with cache-integrated network interfaces.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	explicit communication, inter-processor synchronization, cache, network interface
1	Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samarjit Chakraborty	Timing analysis of esterel programs on general-purpose multiprocessors.	DAC	2010	DBLP DOI BibTeX RDF	multiprocessor, timing analysis, synchronous language, esterel
1	Junjie Wu, Xiaohui Pan, Guanghui Liu, Baida Zhang, Xuejun Yang	Parallel Data Reuse Theory for OpenMP Applications.	SNPD	2009	DBLP DOI BibTeX RDF	Intra-processor, Inter-processor, Parallel, Locality, Reuse, OpenMP
1	Slo-Li Chu, Chih-Chieh Hsiao, Pin-Hua Chiu	Design a Hardware Mechanism to Utilize Multiprocessors on a Uni-processor Operating System.	ICA3PP	2009	DBLP DOI BibTeX RDF	Xilinx ML310, FPGA, Linux, Multi-core, Inter-Processor Communication
1	Ronny Ronen	Larrabee: a many-core Intel architecture for visual computing.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	graphics architecture, many-core computing, parrallel processing, processor arechitecture, software rendering
1	Aleksandr Ovcharenko, Onkar Sahni, Christopher D. Carothers, Kenneth E. Jansen, Mark S. Shephard	Subdomain communication to increase scalability in large-scale scientific applications.	ICS	2009	DBLP DOI BibTeX RDF	asynchronous communication, mpi
1	Syed Khairuzzaman Tanbeer, Chowdhury Farhan Ahmed, Byeong-Soo Jeong	Parallel and Distributed Frequent Pattern Mining in Large Databases.	HPCC	2009	DBLP DOI BibTeX RDF
1	Jim M. Brandt, Ann C. Gentile, Jackson Mayo, Philippe P. Pébay, Diana Roe, David C. Thompson, Matthew Wong	Resource monitoring and management with OVIS to enable HPC in cloud computing environments.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Manolis Katevenis	Towards unified mechanisms for inter-processor communication.	ICSAMOS	2008	DBLP DOI BibTeX RDF
1	Saulo Oliveira Dornellas Luiz, Genildo de Moura Vasconcelos, Leandro Dias da Silva	Formal specification of DSP gateway for data transmission between processor cores of OMAP platform.	SAC	2008	DBLP DOI BibTeX RDF	OMAP161x platform, modelling, model checking, embedded systems, timed-automata, discrete event systems, inter-processor communication
1	Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Samuel C. Chang, Liang-Gee Chen	iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor.	DAC	2008	DBLP DOI BibTeX RDF	vision processor, VLSI, video analysis, SIMD, intelligent sensor
1	Mahmut T. Kandemir, Feihui Li, Mary Jane Irwin, Seung Woo Son	A novel migration-based NUCA design for chip multiprocessors.	SC	2008	DBLP DOI BibTeX RDF
1	Bingsheng He, Ke Yang, Rui Fang, Mian Lu, Naga K. Govindaraju, Qiong Luo, Pedro V. Sander	Relational joins on graphics processors.	SIGMOD Conference	2008	DBLP DOI BibTeX RDF	parallel processing, relational database, sort, join, graphics processors, primitive
1	Lars Arge, Michael T. Goodrich, Michael J. Nelson, Nodari Sitchinava	Fundamental parallel algorithms for private-cache chip multiprocessors.	SPAA	2008	DBLP DOI BibTeX RDF	parallel external memory, pem, private-cache cmp
1	Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan	Larrabee: a many-core x86 architecture for visual computing.	ACM Trans. Graph.	2008	DBLP DOI BibTeX RDF	graphics architecture, many-core computing, realtime graphics, software rendering, throughput computing, visual computing, parallel processing, GPGPU, SIMD
1	Farshad Safaei, Ahmad Khonsari, A. H. Shantia	Comparative performance evaluation of software-based fault-tolerant routing algorithms in adaptively-routed tori.	AICCSA	2008	DBLP DOI BibTeX RDF
1	Shihang Yan, Irfan Awan, Geyong Min	Performance Analysis of an Efficient Flow Control Mechanism with Job Threshold in InfiniBand Networks.	AINA	2008	DBLP DOI BibTeX RDF
1	Matin Hashemi, Soheil Ghiasi	Exact and Approximate Task Assignment Algorithms for Pipelined Software Synthesis.	DATE	2008	DBLP DOI BibTeX RDF
1	Hui Liu, Zili Shao, Meng Wang, Ping Chen	Overhead-Aware System-Level Joint Energy and Performance Optimization for Streaming Applications on Multiprocessor Systems-on-Chip.	ECRTS	2008	DBLP DOI BibTeX RDF
1	Kaiyu Chen, Sharad Malik, Priyadarsan Patra	Runtime validation of memory ordering using constraint graph checking.	HPCA	2008	DBLP DOI BibTeX RDF
1	Hamid R. Arabnia	A Scalable Network Topology for Medical Imaging.	HPCC	2008	DBLP DOI BibTeX RDF
1	Shujia Zhou, Bruce H. Van Aartser, Tom Clune	A lightweight scalable I/O utility for optimizing High-End Computing applications.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Awni Itradat, M. Omair Ahmad, Ali Shatnawi	Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Zhiyi Yu, Bevan M. Baas	A low-area interconnect architecture for chip multiprocessors.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Eryk Laskowski, Marek Tudruj	Optimized Communication Control in Programs for Dynamic Look-Ahead Reconfigurable SoC Systems.	ISPDC	2008	DBLP DOI BibTeX RDF
1	Lukasz Masko, Marek Tudruj	Task Scheduling for SoC-Based Dynamic SMP Clusters with Communication on the Fly.	ISPDC	2008	DBLP DOI BibTeX RDF
1	Pierre-André Mudry, Julien Ruffin, Michel Ganguin, Gianluca Tempesti	A Hardware-Software Design Framework for Distributed Cellular Computing.	ICES	2008	DBLP DOI BibTeX RDF
1	Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal	Enabling MPSoC Design Space Exploration on FPGAs.	IMTIC	2008	DBLP DOI BibTeX RDF	FPGAs, MPSoC, FIFO, FSL
1	Chengmo Yang, Alex Orailoglu	Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs.	CASES	2007	DBLP DOI BibTeX RDF	synchronization, interprocessor communication
1	Chen-Ling Chou, Radu Marculescu	Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	dynamic application mapping, low-power, networks-on-chip
1	Lisane B. de Brisolara, Sang-Il Han, Xavier Guerin, Luigi Carro, Ricardo Reis, Soo-Ik Chae, Ahmed Amine Jerraya	Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC.	SCOPES	2007	DBLP DOI BibTeX RDF
1	Guan Yu, Gauthier Lafruit, Peter Schelkens	Platform-scalable Task Partition and Multilevel Buffering in Multi-processor Plessey Corner Detector.	ACSD	2007	DBLP DOI BibTeX RDF
1	Shihang Yan, Irfan Awan, Geyong Min	Performance Analysis of an Active Flow Control Mechanism with Entry Threshold in InfiniBand Networks.	AINA	2007	DBLP DOI BibTeX RDF
1	Jue Wang, Changjun Hu, Jilin Zhang	Optimized scheduling for group communication in data parallelism.	CLUSTER	2007	DBLP DOI BibTeX RDF
1	Jan Willem van den Brand, Marco Bekooij	Streaming consistency: a model for efficient MPSoC design.	DSD	2007	DBLP DOI BibTeX RDF
1	Hristo Nikolov, Todor Stefanov, Ed F. Deprettere	Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips.	FPL	2007	DBLP DOI BibTeX RDF
1	Nitin Auluck	Duplication Based Integrated Task and Message Scheduling on a Heterogeneous Network of Workstations (NOWs).	HASE	2007	DBLP DOI BibTeX RDF
1	Farshad Safaei, Ahmad Khonsari, Mahmood Fathy, A. H. Shantia, Mohamed Ould-Khaoua	Evaluating the Performance of Adaptive Fault-Tolerant Routing Algorithms for Wormhole-Switched Mesh Interconnect Networks.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Awni Itradat, M. Omair Ahmad, Ali Shatnawi	Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional Units.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Chang-Duk Jung, You-Keon Park	Study on Sorting of A Parallel Computer Using Protocol in Ubiquitous Environment.	MUE	2007	DBLP DOI BibTeX RDF
1	Théodore Marescaux, Erik Brockmeyer, Henk Corporaal	The Impact of Higher Communication Layers on NoC Supported MP-SoCs.	NOCS	2007	DBLP DOI BibTeX RDF
1	Sanjoy K. Baruah	Techniques for Multiprocessor Global Schedulability Analysis.	RTSS	2007	DBLP DOI BibTeX RDF
1	Antonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	An Interrupt Controller for FPGA-based Multiprocessors.	ICSAMOS	2007	DBLP DOI BibTeX RDF
1	Parth Malani, Prakash Mukre, Qinru Qiu	Power optimization for conditional task graphs in DVS enabled multiprocessor systems.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement	Modeling of Interconnection Networks in Massively Parallel Processor Architectures.	ARCS	2007	DBLP DOI BibTeX RDF
1	Saeed Parsa, Shahriar Lotfi, Naser Lotfi	An Evolutionary Approach to Task Graph Scheduling.	ICANNGA	2007	DBLP DOI BibTeX RDF
1	Farshad Safaei, Mahmood Fathy, Ahmad Khonsari, Mohamed Ould-Khaoua	Stochastic Communication Delay Analysis of Adaptive Wormhole-Switched Routings in Tori with Faults.	ISPA	2007	DBLP DOI BibTeX RDF
1	Jue Wang, Changjun Hu, Jianjiang Li	Contention-Free Communication Scheduling for Group Communication in Data Parallelism.	OTM Conferences	2007	DBLP DOI BibTeX RDF	Distributed memory multi-computers, Group communication, Parallel compiling, Data parallelism, Communication scheduling
1	Wim Heirman, Joni Dambre, Jan M. Van Campenhout	Congestion modeling for reconfigurable inter-processor networks.	SLIP	2006	DBLP DOI BibTeX RDF	interconnection network, prediction, reconfiguration, congestion
1	Ashraf S. Hussein, Hisham El-Shishiny	A framework for visualization of large time-varying volume data for high performance computing.	CASCON	2006	DBLP DOI BibTeX RDF
1	Muhammad Farooq, Fabrice Muller, Michel Auguin	Contentions-conscious dynamic but deterministic scheduling of computational and communication tasks.	SAC	2006	DBLP DOI BibTeX RDF	deterministic scheduling, architecture, multiprocessor, SoC, RTOS
1	Shujia Zhou, Amidu Oloso, Megan Damon, Tom Clune	Poster reception - Application controlled parallel asynchronous IO.	SC	2006	DBLP DOI BibTeX RDF
1	Eryk Laskowski, Marek Tudruj	Embedded Parallel Systems Based on Dynamic Look-Ahead Reconfiguration in Redundant Communication Resources.	DSD	2006	DBLP DOI BibTeX RDF
1	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	On-FPGA Communication Architectures and Design Factors.	FPL	2006	DBLP DOI BibTeX RDF
1	Abhijit Sarkar, Nabil Benabbou, Roger Ghanem	Domain Decompostion Of Stochastic PDEs and its Parallel.	HPCS	2006	DBLP DOI BibTeX RDF
1	Kevin J. Barker, Scott Pakin, Darren J. Kerbyson	A Performance Model of the Krak Hydrodynamics Application.	ICPP	2006	DBLP DOI BibTeX RDF
1	Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihin	Helper thread prefetching for loosely-coupled multiprocessor systems.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Y. Yamamoto	Efficient parallel implementation of a weather derivatives pricing algorithm based on the fast Gauss transform.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Daewook Kim, Manho Kim, Gerald E. Sobelman	DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Alexey Lopich, Piotr Dudek	Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Awni Itradat, M. Omair Ahmad, Ali Shatnawi	A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures.	PARELEC	2006	DBLP DOI BibTeX RDF
1	Adam Smyk, Marek Tudruj, Lukasz Masko	Open MP Extension for Multithreaded Computing with Dynamic SMP Processor Clusters with Communication on the Fly.	PARELEC	2006	DBLP DOI BibTeX RDF
1	Razvan Racu, Rolf Ernst	Scheduling Anomaly Detection and Optimization for Distributed Systems with Preemptive Task-Sets.	IEEE Real Time Technology and Applications Symposium	2006	DBLP DOI BibTeX RDF
1	Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsunori Kubo	A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
1	Pengyong Ma, Xiao Hu, Shuming Chen, Yang Guo	Pseudo Share Data Cache in Multiprocessor: PSDMP.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
1	E. Seegyoung Seol, Mark S. Shephard	Efficient distributed mesh data structure for parallel automated adaptive analysis.	Eng. Comput. (Lond.)	2006	DBLP DOI BibTeX RDF
1	Guilin Chen, Guangyu Chen, Ozcan Ozturk, Mahmut T. Kandemir	Exploiting Inter-Processor Data Sharing for Improving Behavior of Multi-Processor SoCs.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee	Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs.	DAC	2005	DBLP DOI BibTeX RDF	heterogeneous, cache coherence, MPSoC, real-time and embedded systems, inter-processor communication
1	Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya	Scheduler implementation in MP SoC design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin	Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	data compression, chip multiprocessors, optimizing compiler
1	Feihui Li, Guilin Chen, Mahmut T. Kandemir, Mustafa Karaköy	Exploiting last idle periods of links for network power management.	EMSOFT	2005	DBLP DOI BibTeX RDF	compiler, interconnection network, energy optimization
1	Kai Shen	Parallel sparse LU factorization on second-class message passing platforms.	ICS	2005	DBLP DOI BibTeX RDF
1	Xiaoyang Gao, Swarup Kumar Sahoo, Chi-Chung Lam, J. Ramanujam, Qingda Lu, Gerald Baumgartner, P. Sadayappan	Performance modeling and optimization of parallel out-of-core tensor contractions.	PPOPP	2005	DBLP DOI BibTeX RDF	parallel algorithms, performance modeling, compiler optimization, out-of-core algorithms
1	Kevin J. Barker, Alan F. Benner, Raymond R. Hoare, Adolfy Hoisie, Alex K. Jones, Darren J. Kerbyson, Dan Li, Rami G. Melhem, Ramakrishnan Rajamony, Eugen Schenfeld, Shuyi Shao, Craig B. Stunkel, Peter Walker	On the Feasibility of Optical Circuit Switching for High Performance Computing Systems.	SC	2005	DBLP DOI BibTeX RDF
1	Duc Kien Nguyen, Ivan Lavallée, Marc Bui, Quoc Trung Ha	A General Scalable Parallelizing of Strassen's Algorithm for Matrix Multiplication on Distributed Memory Computers.	ACIS-ICIS	2005	DBLP DOI BibTeX RDF
1	Yi Zhang, David Parker, Marta Z. Kwiatkowska	A Wavefront Parallelisation of CTMC Solution Using MTBDDs.	DSN	2005	DBLP DOI BibTeX RDF
1	Boguslaw Butrylo, Marek Tudruj, Lukasz Masko, Laurent Nicolas	SSOR Preconditioned Conjugate Gradient Algorithm in Dynamic SMP Clusters with Communication on the Fly.	ISPDC	2005	DBLP DOI BibTeX RDF