Search results for "interconnect layout optimization"

Searching for phrase interconnect layout optimization (changed automatically) with no syntactic query expansion in all metadata.

Found 5 publication records. Showing 5 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Jason Cong, Cheng-Kok Koh	Interconnect layout optimization under higher-order RLC model.	ICCAD	1997	DBLP DOI BibTeX RDF	RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization
2	Jason Cong, Cheng-Kok Koh, Patrick H. Madden	Interconnect layout optimization under higher order RLC model forMCM designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Jason Cong, David Zhigang Pan	Interconnect performance estimation models for design planning.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo	Interconnect design for deep submicron ICs.	ICCAD	1997	DBLP DOI BibTeX RDF	required-arrival-time Steiner tree higher-order moment signal delay and integrity
1	Takumi Okamoto, Jason Cong	Buffered Steiner tree construction with wire sizing for interconnect layout optimization.	ICCAD	1996	DBLP DOI BibTeX RDF	Steiner Tree, Buffer Insertion, Interconnect Optimization, Wire Sizing

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