Search results for "interconnect modeling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Qinwei Xu, Pinaki Mazumder	Novel interconnect modeling by using high-order compact finite difference methods.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	differential quadrature method, discrete interconnect modeling, passivity, interconnect modeling, transient simulation
2	Mohammad S. Sharawi, Daniel N. Aloi	An 800 Mbps system interconnect modeling and simulation for high speed computing.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Guoan Zhong, Cheng-Kok Koh, Kaushik Roy	On-chip interconnect modeling by wire duplication.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
2	Guoan Zhong, Cheng-Kok Koh, Kaushik Roy	On-chip interconnect modeling by wire duplication.	ICCAD	2002	DBLP DOI BibTeX RDF
2	N. P. van der Meijs, T. Smedes	Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	Physical Design Verification, Interconnect Resistance Extraction, Interconnect Capacitance Extraction, Substrate Resistance Extraction, Interconnect Modeling
1	Luca P. Carloni, Andrew B. Kahng, Sudhakar Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma	Accurate Predictive Interconnect Modeling for System-Level Design.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Katalin Popovici, Ahmed Amine Jerraya	Flexible and abstract communication and interconnect modeling for MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Joseph Nayfach-Battilana, Jose Renau	SOI, interconnect, package, and mainboard thermal characterization.	ISLPED	2009	DBLP DOI BibTeX RDF	SOI modeling, package modeling, thermal modeling, interconnect modeling
1	Yuichi Tanji	Sparse and Passive Reduced-Order Interconnect Modeling by Eigenspace Method.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma	Interconnect modeling for improved system-level design optimization.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	James D. Ma, Rob A. Rutenbar	Interval-Valued Reduced-Order Statistical Interconnect Modeling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha	Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Laureline David, Stephane Martin, Corinne Cregut, Eric Balossier, Frederic Nyer, Fabrice Huret	Pre-Layout Inductive Corners for Advanced Digital Design Interconnect: Modeling and Silicon Validation.	ISQED	2006	DBLP DOI BibTeX RDF
1	Hao Yu, Yiyu Shi, Lei He, David Smart	A fast block structure preserving model order reduction for inverse inductance circuits.	ICCAD	2006	DBLP DOI BibTeX RDF	inductance and interconnect modeling, model order reduction
1	Zhuo Feng, Peng Li	Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Weiping Liao, Lei He	Microarchitecture Level Interconnect Modeling Considering Layout Optimization.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
1	James D. Z. Ma, Rob A. Rutenbar	Fast interval-valued statistical interconnect modeling and reduction.	ISPD	2005	DBLP DOI BibTeX RDF	interval-valued statistical interconnect analysis, manufacturing variation, affine arithmetic
1	Rong Jiang, Wenyin Fu, Charlie Chung-Ping Chen	EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Jeff Davis	Interconnect Modeling. (PDF / PS)	ISQED	2004	DBLP DOI BibTeX RDF
1	N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara	Interconnect Modeling for Copper/Low-k Technologies.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	James D. Ma, Rob A. Rutenbar	Interval-valued reduced order statistical interconnect modeling.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Lakshmi Kalpana Vakati, Janet Meiling Wang	A new multi-ramp driver model with RLC interconnect load.	ISPD	2004	DBLP DOI BibTeX RDF	inductance criteria, multi-ramp driver model, transmission line effects, interconnect modeling, effective capacitance
1	Joel R. Phillips	Variational interconnect analysis via PMTBR.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Tobias Thiel	Have I Really Met Timing? - Validating PrimeTime Timing Reports with Spice.	DATE	2004	DBLP DOI BibTeX RDF
1	Qinwei Xu, Pinaki Mazumder	Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng	Interconnect modeling and sensitivity analysis using adjoint networks reduction technique.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Qinwei Xu, Pinaki Mazumder	Efficient interconnect modeling by Finite Difference Quadrature methods.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Magdy A. El-Moursy, Eby G. Friedman	Shielding effect of on-chip interconnect inductance.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	on-chip inductance, shielding effect, propagation delay, interconnect modeling, gate delay
1	Pallav Gupta, Lin Zhong, Niraj K. Jha	A High-level Interconnect Power Model for Design Space Exploration.	ICCAD	2003	DBLP DOI BibTeX RDF
1	N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell	Benchmarks for Interconnect Parasitic Resistance and Capacitance.	ISQED	2003	DBLP DOI BibTeX RDF
1	Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang	Aggressive crunching of extracted RC netlists.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	RC reduction, TICER, crunching, node elimination, resistor shorting, time constants, interconnect modeling, elmore delay
1	Peter Meuris, Wim Schoenmaker, Wim Magnus	Strategy for electromagnetic interconnect modeling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Narain Arora, N. S. Nagaraj	Interconnect Modeling for Timing, Signal Integrity and Reliability. (PDF / PS)	ISQED	2001	DBLP DOI BibTeX RDF
1	W. H. Kao, Ch-Yuan Lo, R. Singh, M. Basel	Parasitic extraction: current state of the art and future trends.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Angelo Brambilla, Paolo Maffezzoni	Statistical method for the analysis of interconnects delay insubmicrometer layouts.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Charlie Chung-Ping Chen, Tae-Woo Lee, Narayanan Murugesan, Susan C. Hagness	Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's Equations Solver for VLSI Interconnect Modeling.	ICCAD	2000	DBLP BibTeX RDF
1	Eileen You, Lakshminarasimh Varadadesikan, John MacDonald, Wieze Xie	A practical approach to parasitic extraction for design of multimillion-transistor integrated circuits.	DAC	2000	DBLP DOI BibTeX RDF
1	Li-Fu Chang, Keh-Jeng Chang, Christophe J. Bianchi	A Proposal for Accurately Modeling Frequency-Dependent On-Chip Interconnect Impedance.	ISQED	2000	DBLP DOI BibTeX RDF
1	Nagaraj Ns, Frank Cano, Sudha Thiruvengadam, Deepak Kapoor	Performance and Reliability Verification of C6201/C6701 Digital Signal Processors.	ICCD	1999	DBLP DOI BibTeX RDF
1	Dennis Sylvester, Kurt Keutzer	Getting to the bottom of deep submicron.	ICCAD	1998	DBLP DOI BibTeX RDF	ASIC, power dissipation, signal integrity, interconnect modeling, wirelength, gate delay, CMOS scaling
1	Nuno Alexandre Marques, Mattan Kamon, Jacob White, Luis Miguel Silveira	An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models.	DATE	1998	DBLP DOI BibTeX RDF	Passive Model Order Reduction, Modified Nodal Analysis, PEEC, Extraction, Interconnect Modeling
1	Jason Cong, Lei He	An efficient technique for device and interconnect optimization in deep submicron designs.	ISPD	1998	DBLP DOI BibTeX RDF
1	E. Aykut Dengi, Ronald A. Rohrer	Hierarchical 2-D Field Solution for Capacitance Extraction for VLSI Interconnect Modeling.	DAC	1997	DBLP DOI BibTeX RDF
1	Keith Nabors, Tze-Ting Fang, Hung-Wen Chang, Kenneth S. Kundert	Lumped Interconnect Models Via Gaussian Quadrature.	DAC	1997	DBLP DOI BibTeX RDF
1	Mattan Kamon, Steve S. Majors	Package and Interconnect Modeling of the HFA3624, a 2.4GHz RF to IF Converter.	DAC	1996	DBLP DOI BibTeX RDF
1	Martin Bächtold, Jan G. Korvink, Henry Baltes	Enhanced multipole acceleration technique for the solution of large Poisson computations.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
1	Tai-Yu Chou, Jay Cosentino, Zoltan J. Cendes	High-Speed Interconnect Modeling and High-Accuracy Simulation Using SPICE and Finite Element Methods.	DAC	1993	DBLP DOI BibTeX RDF
1	Soo-Young Oh, Keh-Jeng Chang, Norman Chang, Ken Lee	Interconnect Modeling and Design in High-Speed VLSI/ULSI Systems.	ICCD	1992	DBLP BibTeX RDF